AT32UC3C0512C Atmel Corporation, AT32UC3C0512C Datasheet - Page 874
AT32UC3C0512C
Manufacturer Part Number
AT32UC3C0512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512C
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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32.6.1.2
32.6.1.3
32.6.1.4
32117C–AVR-08/11
Interrupts
Frozen clock
Speed control
• Device mode
The USBC can be disabled at any time by writing a zero to USBCON.USBE, this acts as a hard-
ware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, and UIMOD bits in USBCON,
and the LS bits in UDCON are not reset.
One interrupt vector is assigned to the USBC.
See
There are two kinds of general interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing general interrupts are:
The exception general interrupts are:
See
When the USB clock is frozen, it is still possible to access the following bits: OTGPADE,
VBUSPO, UIDE, UIMOD, FRZCLK, and USBE in the USBCON register, and LS in the UDCON
register.
When FRZCLK is set, only the asynchronous interrupts can trigger a USB interrupt (see
32.5.4).
When the USBC interface is in device mode, the speed selection is done by the UDCON.LS bit,
connecting an internal pull-up resistor to either DP (full-speed mode) or DM (low-speed mode).
The LS bit shall be written before attaching the device, which can be simulated by clearing the
UDCON.DETACH bit.
• The ID Transition Interrupt (IDTI)
• The VBUS Transition Interrupt (VBUSTI)
• The SRP Interrupt (SRPI)
• The Role Exchange Interrupt (ROLEEXI)
• The VBUS Error Interrupt (VBERRI)
• The B-Connection Error Interrupt (BCERRI)
• The HNP Error Interrupt (HNPERRI)
• The Suspend Time-Out Interrupt (STOI)
Section 32.6.2.18
Section 32.5.4
for asynchronous interrupts.
and
Section 32.6.3.16
for further details about device and host interrupts.
AT32UC3C
Section
874
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