AT32UC3C0512C Atmel Corporation, AT32UC3C0512C Datasheet - Page 411
AT32UC3C0512C
Manufacturer Part Number
AT32UC3C0512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512C
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Price
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21.3.4
21.4
21.4.1
21.4.2
21.4.3
32117C–AVR-08/11
Functional Description
Debug Operation
Bus Interfaces
Transferring Data
Arbitration
When an external debugger forces the CPU into debug mode, the MDMA continues normal
operation. If the MDMA is configured in a way that requires it to be periodically serviced by the
CPU through interrupts or similar, improper operation or data loss may result during debugging.
The MDMA has three bus interfaces, two High-Speed Bus interfaces for data and descriptor
transfer, and one Peripheral Bus interface for writing control information to and reading status
information from the controller.
Once a channel (x) is selected by the arbiter, data of the size given by the SIZE field in the
Channel Control Register (CCRx.SIZE) will be transferred from consecutive addresses starting
as specified in the Read Address Register (RARx) to consecutive addresses starting as speci-
fied in the Write Address Register (WARx). The number of data to be transferred is given by the
Transfer Count field (CCRx.TCNT). The MDMA will try to transfer data in bursts with burst length
given by CCRx.BURST. The MDMA is free to use bursts of shorter length if this is required by
the bus semantics or if TCNT is not perfectly divisible by BURST.
During transfers, TCNT is continuously decremented until it reaches zero, indicating that the
transfer has completed. RARx and WARx are not changed by hardware during transfers.
Data read from the bus is put into a FIFO before being written to the bus. The FIFO has word-
sized entries, so any halfwords or bytes transferred from the bus will be zero-extended before
being put in the FIFO. Words are not extended in any way. The Byte Swap (BSWP) field in
CCRx determines if any modifications are to be performed on the read data from the zero-exten-
sion unit. This allows data reformatting such as endianness-conversion.
Figure 21-1. Byte Swapping the FIFO Inputs
Arbitration between the channels is performed at the end of each burst. If no other channels
have pending transfers, the current channel continues uninterrupted.
In Fixed Priority Mode, if a channel of higher priority is enabled when another channel is trans-
ferring data, the channel of higher priority will preempt the other channel. When the preempting
channel has completed, the arbiter will grant control to the original channel so it can complete its
transfer.
Write data
FIFO
swap
Byte
extend
Zero-
AT32UC3C
Read data
411
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