AT32UC3B1256 Atmel Corporation, AT32UC3B1256 Datasheet - Page 440
AT32UC3B1256
Manufacturer Part Number
AT32UC3B1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1256-AUR
Manufacturer:
OMRON
Quantity:
12 000
Company:
Part Number:
AT32UC3B1256-AUT
Manufacturer:
ATMEL
Quantity:
1 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
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- Download datasheet (11Mb)
22.8.2.20
Register Name:
Access Type:
Offset:
Reset Value:
• CHBYTECNT: Channel Byte Count
• DESCLDSTA: Descriptor Loaded Status
• EOCHBUFFSTA: End of Channel Buffer Status
• EOTSTA: End of USB Transfer Status
• CHACTIVE: Channel Active
• CHEN: Channel Enabled
32059L–AVR32–01/2012
31
23
15
7
-
-
This field contains the current number of bytes still to be transferred for this buffer.
This field is decremented at each dma access.
This field is reliable (stable) only if the CHEN bit is zero.
This bit is set when a Descriptor has been loaded from the HSB bus.
This bit is cleared when read by the user.
This bit is set when the Channel Byte Count counts down to zero.
This bit is automatically cleared when read by software.
This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if
UDDMAnCONTROL.BUFFCLOSEINEN is one. Note that for OUT endpoint, if the UECFGn.AUTOSW is set, any received zero-
length-packet will be cancelled by the DMA, and the EOTSTA will be set whatever the UDDMAnCONTROL.CHEN bit is.
This bit is automatically cleared when read by software.
0: the DMA channel is no longer trying to source the packet data.
1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a
packet transfer cannot be completed due to an EOCHBUFFSTA, this bit stays set during the next channel descriptor load (if
any) and potentially until USB packet transfer completion, if allowed by the new descriptor.
When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is running
(the endpoint is free for IN transaction, the endpoint is full for OUT transaction).
This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded.
This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end.
Device DMA Channel n Status Register
DESCLD
STA
30
22
14
6
-
UDDMAnSTATUS, n in [1..6]
Read/Write
0x031C + (n - 1) * 0x10
0x00000000
EOCHBUFF
STA
29
21
13
5
-
EOTSTA
CHBYTECNT[15:8]
28
20
12
CHBYTECNT[7:0]
4
-
27
19
11
3
-
-
26
18
10
2
-
-
CHACTIVE
25
17
9
1
-
CHEN
24
16
8
0
-
440
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