AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 22

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.4
6.4.1
6.4.2
32059L–AVR32–01/2012
Programming Model
Register File Configuration
Status Register Configuration
The AVR32UC register file is shown below.
Figure 6-3.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
page 22
code flags and the R, T, and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 6-4.
Application
Bit 31
Bit 31
SP_APP
INT0PC
INT1PC
FINTPC
SMPC
0
-
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LC
Bit 0
1
0
-
and
0
Supervisor
Bit 31
-
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
Figure 6-5 on page
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
The AVR32UC Register File
The Status Register High Halfword
0
-
Bit 0
DM
0
INT0
Bit 31
SP_SYS
D
0
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
0
-
M2
0
INT1
Bit 31
SP_SYS
FINTPC
23. The lower word contains the C, Z, N, V, and Q condition
INT0PC
INT1PC
SMPC
R12
R11
R10
M1
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
0
Bit 0
M0
1
INT2
Bit 31
EM
1
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
I3M
0
SS_STATUS
Bit 0
SS_SP_SYS
SS_SP_APP
SS_ADRR
SS_ADRF
SS_ADR0
SS_ADR1
SS_RAR
SS_RSR
I2M
FE
0
INT3
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
I1M
SMPC
0
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
I0M
0
Bit 16
GM
Exception
Bit 31
1
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit name
Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Exception Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
Bit 0
NMI
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Figure 6-4 on
Secure
Bit 31
SP_SEC
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
22