AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 65

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
bus latency may cause a memory access to be seen by a slave many cycles after it has been
executed by the pipeline. In some cases, this may lead to UNPREDICTABLE behavior in the
system.
One example of this is found in interrupt handlers. One usually wants to make sure that the inter-
rupt request has been cleared before executing the rete instruction, otherwise the same interrupt
may be serviced immediately after executing the rete instruction. In this case a DMB must be
inserted between the code clearing the interrupt request and the rete.
All accesses to HSB space are strongly ordered. This is used to implement DMBs. A DMB after
a store to a HSB slave is implemented by performing a dummy read from the same slave. Any
critical code after the read will stall until the read has been performed.
Consider an interrupt request made by a peripheral. This peripheral will disassert the interrupt
r e q u e s t a s s o o n a s t h e i n t e r r u p t h a n d l e r h a s w r i t t e n a s p e c i f i c b i t m a s k t o i t s
PERIPH_INTCLEAR register. A read from the same peripheral performs a bus transfer that
implements the DMB. The rete instruction can be executed after the DMB.
Code 6-1.
// Using data memory barriers in the IRQ handler to make sure that the
// request has been disasserted before returning from the handler
// Assume that the IRQ is cleared by writing a bitmask to PERIPH_INTCLEAR.
// r0 points to this register, r1 contains the correct bitmask.
irq_handler:
<some instructions>
st.w r0[0], r1
ld.w r12, r0[0] // data memory barrier
rete
Clearing IRQs using data memory barriers
AVR32
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