AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 9

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7745C–AVR32–05/09
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If external events (power-on reset, external reset, OCD reset, JTAG reset or JTAG
hardware reset) are among the reset causes, the boot process checks if the
ISP_IO_COND_EN GP fuse bit is 1, and if so it launches the USB DFU ISP or the
application according to the ISP I/O configuration specified by the User page. If
ISP_IO_COND_EN is 0, the application is launched.
Else, if the watchdog timer (WDT) is one of the reset causes, the boot process
launches the application. The watchdog timer is not stopped if the application was
running before reset.
Else, i.e. if an error (BOD or CPU error) is one of the reset causes, the boot process
launches the one that was running before reset among the USB DFU ISP and the
application.
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