AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 134

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

134
AVR32
ANDH, ANDL – Logical AND into high or low half of register
Architecture revision:
Architecture revision1 and higher.
Description
Performs a bitwise logical AND between the high or the low halfword in the specified register and
a constant. The result is stored in the high or the low halfword of the destination register while
the other bits remain unchanged. The Clear Other Half (COH) parameter allows the other half to
be cleared.
Operation:
I.
II.
III.
IV.
Syntax:
I.
II.
III.
IV.
Operands:
I, II, III, IV.
Status Flags:
Opcode
31
15
1
Rd[31:16] ← Rd[31:16] ∧ imm16;
Rd[31:16] ← Rd[31:16] ∧ imm16;
Rd[15:0] ← 0;
Rd[15:0] ← Rd[15:0] ∧ imm16;
Rd[15:0] ← Rd[15:0] ∧ imm16;
Rd[31:16] ← 0;
andh
andh
andl
andl
d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}
Q:
V:
N:
Z:
C:
Format I, II:
1
29
1
Rd, imm
Rd, imm, COH
Rd, imm
Rd, imm, COH
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
Not affected
28
0
0
26
1
COH
25
24
0
imm16
0
0
0
20
1
19
Rd
32000D–04/2011
0
16