AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 116

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 9-10.
116
st.b
st.b{cond4}
st.d
st.h
st.h{cond4}
st.w
st.w{cond4}
stcond
stdsp
sthh.w
AVR32
Load/Store Operations (Continued)
C
C
C
E
E
E
C
C
C
E
E
C
C
C
E
E
E
C
C
C
E
E
E
C
C
E
E
Rp++, Rs
--Rp, Rs
Rp[disp], Rs
Rp[disp], Rs
Rb[Ri<<sa], Rs
Rp[disp], Rs
Rp++, Rs
--Rp, Rs
Rp, Rs
Rp[disp], Rs
Rb[Ri<<sa], Rs
Rp++, Rs
--Rp, Rs
Rp[disp], Rs
Rp[disp], Rs
Rb[Ri<<sa], Rs
Rp[disp], Rs
Rp++, Rs
--Rp, Rs
Rp[disp], Rs
Rp[disp], Rs
Rb[Ri<<sa], Rs
Rp[disp], Rs
Rp[disp], Rs
SP[disp], Rs
Rp[disp], Rx:<part>,
Ry:<part>
Rb[Ri<<sa],
Rx:<part>, Ry:<part>
Store with post-increment.
Store with pre-decrement.
Store byte with displacement.
Indexed Store byte.
Store byte with displacement if condition
satisfied.
Store with post-increment.
Store with pre-decrement.
Store doubleword
Store double with displacement
Indexed Store double.
Store with post-increment.
Store with pre-decrement.
Store halfword with displacement.
Indexed Store halfword.
Store halfword with displacement if
condition satisfied.
Store with post-increment.
Store with pre-decrement.
Store word with displacement.
Indexed Store word.
Store word with displacement if condition
satisfied.
Conditional store with displacement.
Store with displacement from SP.
Combine halfwords to word and store with
displacement.
Combine halfwords to word and store
indexed.
*(Rp++) ← Rs[7:0]
*(--Rp) ← Rs[7:0]
*(Rp+ZE(disp3)) ← Rs[7:0]
*(Rp+SE(disp16)) ← Rs[7:0]
*(Rb+(Ri << sa2)) ← Rs[7:0]
if {cond4}
*(Rp+SE(disp9)) ← Rs[7:0]
*(Rp++) ← (Rs+1:Rs)
*(--Rp) ← (Rs+1:Rs)
*(Rp) ← (Rs+1:Rs)
*(Rp+SE(disp16)) ← (Rs+1:Rs)
*(Rb+(Ri << sa2)) ← (Rs+1:Rs)
*(Rp++) ← Rs[15:0]
*(--Rp) ← Rs[15:0]
*(Rp+(ZE(disp3)<<1)) ← Rs[15:0]
*(Rp+(SE(disp16))) ← Rs[15:0]
*(Rb+(Ri << sa2)) ← Rs[15:0]
if {cond4}
*(Rp+SE(disp9<<1)) ← Rs[15:0]
*(Rp++) ← Rs
*(--Rp) ← Rs
*(Rp+(ZE(disp4)<<2)) ← Rs
*(Rp+(SE(disp16))) ← Rs
*(Rb+(Ri << sa2)) ← Rs
if {cond4}
*(Rp+ZE(disp9<<2)) ← Rs
SREG[Z] ← SREG[L]
if (SREG[L])
*(Rp+(SE(disp16))) ← Rs
*( (SP && 0xFFFF_FFFC)
+(ZE(disp7)<<2)) ← Rs
*(Rp+(ZE(disp8)<<2)) ←
{Rx:<part>, Ry:<part>}
*(Rb+(Ri << sa2)) ← {Rx:<part>,
Ry:<part>}
32000D–04/2011
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