AT32UC3A1512 Atmel Corporation, AT32UC3A1512 Datasheet - Page 575
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AT32UC3A1512
Manufacturer Part Number
AT32UC3A1512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1512
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1512-U
Manufacturer:
ATMEL
Quantity:
2
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- Current page: 575 of 826
- Download datasheet (11Mb)
32058K AVR32-01/12
Shall be cleared by software (by setting the OVERFIC bit) to acknowledge the interrupt.
• STALLEDI: STALLed Interrupt Flag
Set by hardware to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by
setting the STALLRQS bit). This triggers an EPXINT interrupt if STALLEDE = 1.
Shall be cleared by software (by setting the STALLEDIC bit) to acknowledge the interrupt.
• CRCERRI: CRC Error Interrupt Flag
Set by hardware to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored
in the bank as if no CRC error had occurred. This triggers an EPXINT interrupt if CRCERRE = 1.
Shall be cleared by software (by setting the CRCERRIC bit) to acknowledge the interrupt.
• SHORTPACKET: Short Packet Interrupt Flag
For non-control OUT endpoints, set by hardware when a short packet has been received.
For non-control IN endpoints, set by hardware when a short packet is transmitted upon ending a DMA transfer, thus signal-
ing an end of isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable bit
(DMAEND_EN) and the Automatic Switch bit (AUTOSW) are set.
This triggers an EPXINT interrupt if SHORTPACKETE = 1.
Shall be cleared by software (by setting the SHORTPACKETC bit) to acknowledge the interrupt.
• DTSEQ: Data Toggle Sequence
Set by hardware to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to
the current bank.
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
Note that by default DTSEQ = 01b, as if the last data toggle sequence was Data1, so the next sent or expected data toggle
sequence should be Data0.
• NBUSYBK: Number of Busy Banks
Set by hardware to indicate the number of busy banks:
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this
triggers an EPXINT interrupt if NBUSYBKE = 1.
0
0
1
0
0
1
1
NBUSYBK
DTSEQ
X
0
1
0
1
0
1
Data Toggle Sequence
Data0
Data1
Reserved
Number of Busy Banks
0 (all banks free)
1
2
3
AT32UC3A
575
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