AT32UC3A1512 Atmel Corporation, AT32UC3A1512 Datasheet - Page 558
AT32UC3A1512
Manufacturer Part Number
AT32UC3A1512
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1512
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1512-U
Manufacturer:
ATMEL
Quantity:
2
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
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AT32UC3A
Note that this interrupt is generated even if the clock is frozen by the FRZCLK bit.
• EORSM: End of Resume Interrupt Flag
Set by hardware when the USB controller detects a valid “End of Resume” signal initiated by the host. This triggers a USB
interrupt if EORSME = 1.
Shall be cleared by software (by setting the EORSMC bit) to acknowledge the interrupt.
• UPRSM: Upstream Resume Interrupt Flag
Set by hardware when the USB controller sends a resume signal called “Upstream Resume”. This triggers a USB interrupt
if UPRSME = 1.
Shall be cleared by software (by setting the UPRSMC bit) to acknowledge the interrupt (USB clock inputs must be enabled
before).
• EPXINT, X in [0..6]: Endpoint X Interrupt Flag
Set by hardware when an interrupt is triggered by the endpoint X (UESTAX, UECONX). This triggers a USB interrupt if
EPXINTE = 1.
Cleared by hardware when the interrupt source is serviced.
• DMAXINT, X in [1..6]: DMA Channel X Interrupt Flag
Set by hardware when an interrupt is triggered by the DMA channel X. This triggers a USB interrupt if DMAXINTE = 1.
Cleared by hardware when the UDDMAX_STATUS interrupt source is cleared.
558
32058K AVR32-01/12
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