AT32UC3A1128 Atmel Corporation, AT32UC3A1128 Datasheet - Page 95

• Manufacturer Part Number: AT32UC3A1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

AT32UC3A
15.5
Functional Description
The WDT is enabled by writing the EN bit in the CTRL register to one. This also enables the RC
clock for the prescaler. The PSEL bitfield in the same register selects the watchdog timeout
period:
(PSEL+1)
T
= 2
/ f
WDT
RC
The next timeout period will begin as soon as the watchdog reset has occured and count down
during the reset sequence. Care must be taken when selecting the PSEL value so that the time-
out period is greater than the startup time of the chip, otherwise a watchdog reset can reset the
chip before any code has been run.
To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with
the KEY field set to 0x55, then 0xAA without changing the other bitfields. Failure to do so will
cause the write operation to be ignored, and CTRL does not change value.
The CLR register must be written with any value with regular intervals shorter than the watchdog
timeout period. Otherwise, the device will receive a soft reset, and the code will start executing
from the boot vector.
When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result
in entering Shutdown mode, leaving the WDT operational.
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32058K AVR32-01/12