PEF20532FV1.2 Infineon Technologies AG, PEF20532FV1.2 Datasheet
PEF20532FV1.2
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PEF20532FV1.2 Summary of contents
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... Edition 2000-09-14 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 9/14/00. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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PEB 20532 Revision History: Previous Version: Page Page Subjects (major changes since last revision) (previous (current Version) Version) 32-34 35-37 Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal ’OST’ is multiplexed with ’CTS’ (was vice versa corrected ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.2.13.2 FM0 and FM1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.4.4.2 In-band Flow Control by XON/XOFF Characters . . . . . . . . . . . . . . . . 98 4.4.4.3 Out-of-band Flow Control . . . . . . . . . ...
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Table of Contents 7.7.2.2 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 43 HDLC Receive Data Processing in Address Mode Figure 44 SCC Transmit Data Flow (HDLC Modes ...
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List of Tables Table 1 Microprocessor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ...
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List of Registers Register 1 GCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Registers Register 43 RTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Registers Register 85 RSTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preface The 2 Channel Serial Optimized Communication Controller PEB 20532 (SEROCCO- Protocol Controller for a wide range of data communication and telecommunication applications. This document provides complete reference information on hardware and software related issues as well as ...
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Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (SEROCCO-M), device number (PEB ...
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Introduction The SEROCCO Serial Communication Controller with two independent serial 1) channels . The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and ...
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Channel Serial Optimized Communication Controller SEROCCO-M Version 1.2 1.1 Features Serial communication controllers (SCCs) • Two independent channels • Full duplex data rates on each channel Mbit/s sync - 2 Mbit/s with DPLL • 64 ...
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CRC generation and checking (CRC-CCITT or CRC-32) – Transparent CRC option per channel and/or per frame – Programmable Preamble (8 bit) with selectable repetition rate – Error detection (abort, long frame, CRC error, short frames) • Bit Synchronous PPP ...
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Protocol and Mode Independent – Data bit inversion – Data overflow and underrun detection – Timer Protocol Support • Address Recognition Modes – No address recognition (Address Mode 0) – 8-bit (high byte) address recognition (Address Mode 1) – ...
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Logic Symbol A(7:0) 1) ALE D(15: BHE Microprocessor 2) LDS Interface 2) UDS 2) R/W DTACK CS INT/INT CLK RESET 1) Intel bus mode 2) Motorola bus mode Figure 1 Logic Symbol Data Sheet ...
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Typical Applications SEROCCO-M devices can be used in LAN-WAN inter-networking applications such as Routers, Switches and Trunk cards and support the common V.35, ISDN BRI (S/T) and RFC1662 standards. Its new features provide powerful hardware and software interfaces to ...
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CPU RAM Bank Figure 3 System Integration With External DMA Controller Data Sheet Transceiver, Framer . . . SEROCCO-M PEB 20532 PEF 20532 . . . System Bus DMA Controller 23 PEB 20532 PEF 20532 Introduction 2000-09-14 ...
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Serial Configuration Examples SEROCCO-M supports a variety of serial configurations at Layer-1 and Layer-2 level. The outstanding variety of clock modes supporting a large number of combinations of external and internal clock sources allows easy integration in application environments. ...
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RxD CxD TxD Slave Figure 5 Point-to-Multipoint Bus Configuration . . . RxD CxD TxD Master 1 SEROCCO-M PEB 20532 PEF 20532 . . . Figure 6 Multimaster Bus Configuration Data Sheet . ...
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Differences between SEROCCO-M and the ESCC Family This chapter is useful for all being familiar with the ESCC family. 1.4.1 Enhancements to the ESCC Serial Core The SEROCCO-M SCC cores contain the core logic of the ESCC as the ...
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Pin Descriptions 2.1 Pin Diagram P-TQFP-100-3 (top view) P-TQFP-100-3 VDD VSS D12 D13 D14 80 D15 VDD VSS DRTA DACKA# 85 DRRA DRRB/GP1 DRTB/GP0 DACKB#/GP2 RTSB# 90 RxDB VDD VSS RxCLKB TxDB 95 TxCLKB CDB/FSCB/RCGB#/OSRB VDD TRST# TDI 100 ...
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Pin Definitions and Functions Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P-TQFP- 100-3 81 D15 80 D14 79 D13 78 D12 75 D11 74 D10 ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P-TQFP- 100 BLE UDS 42 BM ALE Data Sheet Function Out (O) I Address Line A0 (8-bit modes) In Motorola and in Intel 8-bit mode this signal represents ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P-TQFP- 100 BHE LDS R Data Sheet Function Out (O) I Data Strobe (8-bit Motorola bus mode only) This active low strobe signal ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P-TQFP- 100 WIDTH 55 CLK 20 INT/INT O 54 READY DTACK Data Sheet Function Out (O) I Write Strobe (Intel bus mode only) This signal indicates a ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P-TQFP- 100-3 19 RESET I Table 2 External DMA Interface Pin No. Symbol In (I) P-TQFP- 100-3 84 DRTA 86 DRRA Data Sheet Function Out (O) Reset With this active ...
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Table 2 External DMA Interface Pin No. Symbol In (I) P-TQFP- 100-3 85 DACKA I 88 DRTB GP0 87 DRRB GP1 89 DACKB GP2 Data Sheet Function Out (O) DMA Acknowledge Channel A A low signal on this pin informs ...
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Table 3 Serial Port Pins Pin No. Symbol In (I) P-TQFP- 100-3 17 TxCLK A 13 RxCLK A Data Sheet Function Out (O) I/O Transmit Clock Channel A The function of this pin depends on the selected clock mode and ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P-TQFP- 100-3 11 CDA FSCA RCGA OSRA Data Sheet Function Out (O) I Carrier Detect Channel A The function of this pin depends on the selected clock mode. It ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P-TQFP- 100-3 18 RTSA 10 CTSA CxDA TCGA OSTA Data Sheet Function Out (O) O Request to Send Channel A The function of this pin depends on the settings ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P-TQFP- 100-3 14 TxDA 12 RxDA 96 TxCLK B 94 RxCLK B 97 CDB FSCB RCGB OSRB 90 RTSB 5 CTSB CxDB TCGB OSTB 95 TxDB Data Sheet Function ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P-TQFP- 100-3 91 RxDB 8 XTAL1 7 XTAL2 Table 4 General Purpose Pins Pin No. Symbol In (I) P-TQFP- 100-3 23 GP10 24 GP9 25 GP8 26 GP6 Data ...
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Table 5 Test Interface Pins Pin No. Symbol In (I) P-TQFP- 100-3 99 TRST 2 TCK 100 TDI 1 TDO 46 TMS 68 TEST1 69 TEST2 Data Sheet Function Out (O) I JTAG Reset Pin (internal pull-up) For proper device ...
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Table 6 Power Pins Pin No. Symbol In (I) P-TQFP- 100-3 3, 15, V DD3 21, 27, 35, 40, 47, 49, 56, 62, 70, 76, 82 22, 28, 34, 41, 48, 50, 51, 57, ...
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Functional Overview The functional blocks of SEROCCO-M can be divided into two major domains: – the microprocessor interface of SEROCCO-M provides access to on-chip registers and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally these ...
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Serial Communication Controller (SCC) 3.2.1 Protocol Modes Overview The SCC is a multi-protocol communication controller. The core logic provides different protocol modes which are listed below: • HDLC Modes – HDLC Transparent Operation (Address Mode 0) – HDLC Address ...
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SCC Transmit FIFO The SCC transmit FIFO is divided into two parts of 32 bytes each (’transmit pools’). The interface between the two parts provides synchronization between the microprocessor accesses and the protocol logic working with the serial transmit ...
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Figure 10 SCC Receive FIFO New receive data is announced to the CPU with an interrupt latest when the FIFO fill level reaches a chosen threshold level (selected with bitfield ’RFTH(1..0)’ in register “CCR3H” on Page 167). Default value for ...
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SCC FIFO Access Figure 11 and Figure 12 accesses to the transmit and receive FIFOs. XFIFO . Byte Byte Byte Byte ...
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Clocking System The SEROCCO-M includes an internal Oscillator (OSC) as well as two independent Baud Rate Generators (BRG) and two Digital Phase Locked Loop (DPLL) circuits. The transmit and receive clock can be generated either • externally, and supplied ...
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The internal structure of each SCC channel consists of a transmit protocol machine clocked with the transmit frequency f receive frequency f . REC The clocks f and f TRM REC clock inputs e.g. f and TxCLK input pin. TRM ...
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Note: If one of the clock modes 0b selected, the internal oscillator (OSC) should be enabled by clearing bit GMODE:OSCPD. This allows connection of an external crystal to pins XTAL1-XTAL2. The output signal of the OSC ...
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The clocking concept is illustrated in a block diagram manner in the following figure: Additional control signals are not illustrated (please refer to the detailed clock mode descriptions below). settings controlled by: register CCR0, bit field 'CM' selects the clock ...
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Clock Modes 3.2.3.1 Clock Mode 0 (0a/0b) Separate, externally generated receive and transmit clocks are supplied to the SCC via their respective pins. The transmit clock may be directly supplied by pin TxCLK (clock mode 0a) or generated by the ...
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Clock Mode 1 Externally generated RxCLK is supplied to both the receiver and transmitter. In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK pin. These strobe signals work on a per bit ...
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Clock Mode 2 (2a/2b) The BRG is driven by an external clock (RxCLK pin) and delivers a reference clock for the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies the internal receive ...
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Clock Mode 3 (3a/3b) The BRG is fed with an externally generated clock via pin RxCLK. Depending on the value of bit ’SSEL’ in register DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) ...
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Clock Mode 4 Separate, externally generated receive and transmit clocks are supplied via pins RxCLK and TxCLK. In addition separate receive and transmit clock gating signals are supplied via pins RCG and TCG. These gating signals work on a ...
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Clock Mode 5a (Time Slot Mode) This operation mode has been designed for application in time-slot oriented PCM systems. Note: For correct operation NRZ data coding/encoding should be used. The receive and transmit clock are common for each channel ...
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TTSA0..3: Transmit Time Slot Assignment Register TTSA3 7 FSC RxCLK active time slot TS delay (transmit TTSN*8 + TCS (1...1024) TS delay (receive RTSN*8 + RCS (1...1024) RTSA0..3: Receive Time Slot Assignment Register RTSA3 7 Figure ...
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Note: If time-slot selected, the DELAY has long as the PCM frame itself to achieve synchronization (at least for the 2nd and subsequent PCM frames): DELAY = PCM frame length = 1 + ...
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TTSA0..3: Transmit Time Slot Assignment Register TTSA3 7 0 PCMTX0..3: Transmit PCM Mask Register PCMTX3 FSC ... RxCLK active time slot TS delay (transmit TTSN*8 + TCS (1..1024) TS delay (receive RTSN*8 + ...
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Time Slot Assigner (TSA) Ctrl RxCLK FSC internal tx strobe TxCLK TS-Control TxD internal rx strobe RxD Figure 21 Clock Mode 5a Configuration Note: The transmit time slot delay and width is programmable via bit ...
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The following figures provide a more detailed description of the TSA internal counter operation and exceptional cases: clock mode 5a bit TSCM='0' (continuous mode) FSC RxCLK, ... TxCLK ffs ...
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Each frame sync pulse starts the internal offset counter with (1024 - TSdelay) whereas TSdelay is the configured value defining the start position. Whenever the offset counter reaches its maximum value 1024, it triggers the duration counter to start operation. ...
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Clock Mode 5b (Octet Sync Mode) This operation mode has been designed for applications using Octet Synchronous PPP based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported, i.e. bits TTSA1.TEPCM and ...
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TTSA0..3: Transmit Time Slot Assignment Register TTSA3 7 PCMTX0..3: Transmit PCM Mask Register PCMTX3 31 OSR OST RxCLK ... TxCLK active time slot TS delay (transmit TTSN*8 + TCS (1...1024) TS delay (receive RTSN*8 + RCS ...
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Time Slot Assigner (RTSA) Time Slot Assigner Ctrl RxCLK TxCLK OSR OST internal tx strobe TxD internal rx strobe RxD Figure 25 Clock Mode 5b Configuration Note: The transmit time slot delay and width is ...
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Clock Mode 6 (6a/6b) This clock mode is identical to clock mode 2a/2b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator and delivers a reference clock ...
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Clock Mode 7 (7a/7b) This clock mode is identical to clock mode 3a/3b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator. Depending on the value of ...
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Baud Rate Generator (BRG) Each serial channel provides a baud rate generator (BRG) whose division factor is controlled by registers BRRL depends on the selected clock mode. Table 9 BRRL/BRRH Register and Bit-Fields Register Bit-Fields Offset Pos. Name BRRL ...
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Interference Rejection and Spike Filtering Two or more edges in the same directional data stream within a time period of 16 reference clocks are considered to be interference and consequently no additional clock adjustment is performed. Phase Adjustment (PA) Referring ...
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DPLL 0 Count 0 Correction DPLL Output Figure 28 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) DPLL Count 0 Correction DPLL Output ...
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DPLL Count 0 +PA Correction Transmit Clock Receive Clock Figure 30 DPLL Algorithm for FM0, FM1 and Manchester Encoding To supervise correct function when ...
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SCC Serial Bus Configuration Mode Beside the point-to-point configuration, the SCC effectively supports point-to-multipoint (pt-mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods pt-mpt configuration, comprising a central station (master) and several ...
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HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the first part of the frame is still present in the SCC transmit FIFO. If not, an XMR interrupt is generated. Since a ‘zero’ (‘low’) on ...
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Serial Bus Configuration Timing Modes If a bus configuration has been selected, the SCC provides two timing modes, differing in the time interval between sending data and evaluation of the transmitted data for collision detection. • Timing mode 1 ...
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Manchester (also known as Bi-Phase) The desired line coding scheme can be selected via bit field ’SC(2:0)’ in register CCR0H. 3.2.13.1 NRZ and NRZI Encoding NRZ: The signal level corresponds to the value of the data bit. By programming ...
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Transmit Clock Receive Clock FM0 FM1 1 Figure 33 FM0 and FM1 Data Encoding 3.2.13.3 Manchester Encoding Manchester: In the first half of the bit cell, the physical signal level corresponds to the logical value of the data bit. At ...
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Modem Control Signals (RTS, CTS, CD) 3.2.14.1 RTS/CTS Handshaking The SCC provides two pins (RTS, CTS) per serial channel supporting the standard request-to-send modem handshaking procedure for transmission control. A transmit request will be indicated by outputting logical ‘0’ ...
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TxCLK TxD RTS CTS Figure 35 RTS/CTS Handshaking Beyond this standard RTS function, signifying a transmission request of a frame (Request To Send), in HDLC mode the RTS output may be programmed for a special function via SOC1, SOC0 bits ...
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RxD) are connected, generating a local loopback result, the user can perform a self-test of the SCC. SCC receive logic SCC transmit logic Figure 36 SCC Test Loop Transmit data can be disconnected from pin TxD by setting ...
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Table 10 Data Bus Access 16-bit Intel Mode BHE BLE Register Access 1 0 Byte access (8 bit), even address data transfer Table 11 Data Bus Access 16-bit Motorola Mode UDS LDS Register Access 0 0 Word ...
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Interrupt Architecture For certain events in SEROCCO-M an interrupt can be generated, requesting the CPU to read status information from SEROCCO-M. The interrupt line INT/INT is asserted with the output characteristics programmed in bit field ’IPC(1..0)’ in register Page ...
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The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel related interrupts and general purpose port interrupts. 3.6 General Purpose Port Pins 3.6.1 GPP Functional Description General purpose port pins are provided on pins GP6, GP8, GP9 and ...
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Detailed Protocol Description The following Table 12 provides an overview of all supported protocol modes and . The desired protocol mode is selected via bit fields in the channel configuration registers CCR0L, CCR0H, CCR2L Table 12 Protocol Mode Overview ...
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HDLC/SDLC Protocol Modes The HDLC controller of each serial channel (SCC) can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the ...
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Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte address recognition 2-byte address field is selected, the high address byte is compared with the fixed value (group address) as well ...
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Address Mode 0 Characteristics: no address recognition No address recognition is performed and each complete frame will be stored in the SCC receive FIFO. 4.1.2 HDLC Receive Data Processing The following figures give an overview about the management of ...
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ADDR FLAG (high) to RFIFO registers RAH1,2 RAL1,2 involved Figure 40 HDLC Receive Data Processing in Address Mode 2 (16 bit) 8 bit ADDR FLAG (low) to RFIFO opt. 1) registers RAL1,2 involved (address compare) Figure 41 HDLC ...
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FLAG to RFIFO registers involved Figure 43 HDLC Receive Data Processing in Address Mode 0 option 1) The address field (8 bit address, 16 bit address or the high byte bit address) can optionally be forwarded to ...
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Frames with automatic bit Address and Control Byte Generation (Automode): 8 bit ADDR 16 bitADDR FLAG XFIFO registers XAD1 involved Frames without automatic Address and Control Byte Generation (Address Mode 2/1/0): ...
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The transmitted frame will be closed automatically only with a (closing) flag. Note: The SCC does not check whether the length of the frame, i.e. the number of bytes transmitted makes sense according ...
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CRC Generation and Checking In HDLC/SDLC mode, error protection is done by CRC generation and checking. In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at the end of each frame consists of two bytes of CRC ...
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SCC, and – the receive abort indication ’RAB’ in the Receive Status Byte (RSTA). Additionally an optional ’FLEX’ interrupt is generated prior to ’RME’, indicating that the maximum receive frame length was exceeded. ...
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For receive operation SEROCCO-M monitors the incoming data stream for the Opening Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data and are processed as normal HDLC packet including checking of CRC. ...
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HDLC frame, the unexpected characters are discarded before forwarded to the receive CRC checking unit. 7D (control-escape) and 7E H The sequence of mapping control logic is and 7E octets ACCM0..3, 3. UDAC0..3. This mechanism ...
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ACCM0..3: Async Control Character Map Register ACCM3 ... 0 0 ... UDAC0..3: User Defined Async Control Character Map Register 7 UDAC3 7Eh data in transmit FIFO: HDLC framing PPP mapping serial line received ...
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Extended Transparent Mode Characteristics: fully transparent When programmed in the extended transparent mode via the MDS1, MDS0, ADM = ‘111’), the SCC performs fully transparent data transmission and reception without HDLC framing, i.e. without • FLAG insertion and deletion ...
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D0 D1 (LSB Data Bits Start ( Bits with Parity) Bit Figure 46 Asynchronous Character Frame 4.4.2 Data Reception The SCC offers the flexibility to combine clock modes, data encoding and data sampling in ...
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Clock mode 2, 3a (DPLL mode) has to be used in conjunction with FM0, FM1 or Manchester encoding (register The isochronous mode uses the asynchronous character format. However, each data bit is only sampled once (no ...
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Additionally, the CTS signal may be used to control data transmission. 4.4.4 Special Functions 4.4.4.1 Break Detection/Generation Break generation: On issuing the transmit break command (bit ’XBRK’ in register CCR3L), the TxD pin is immediately forced to physical ‘0’ level ...
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In-Band Flow Control of Transmitted Characters: Recognition of an XON or XOFF character causes always a corresponding maskable interrupt status to be generated. Further action depends on the setting of control bit ’FLON’ (Flow Control On) in register CCR2H: 0: ...
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Transmission via this register is possible even when the transmitter is in XOFF state (however, CTS must be ‘low’). The ’TIC’ value is an eight-bit value. The number of significant bits is determined by the programmed asynch character length via ...
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DTE-A is receiving data and its receive FIFO threshold is reached, the RTS signal goes in-active ’HIGH’ forcing the CTS of DTE-B to become in-active indicating that transmission has to stop after finishing the current character. Both DTE devices should ...
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Figure 48 shows an SCC as a DTE connected to a DCE (MODEM equipment). The RTS feeds the RTS A directional flow control. So when the DTE-A’s receiver threshold is reached, the RTS signal goes inactive ’HIGH’ which is sensed ...
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MONOSYNC uses only one SYN. format. SYN SYN SOH (SYNL) (SYNH) 2 Leading Start SYN of Characters Header Figure 49 BISYNC Message Format The SYN character, its length, the length of data characters and additional parity generation are programmable: ...
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This is the user’s responsibility by appropriate software settings. Filling of the receive FIFO is controlled by a programmable threshold level. Reception is stopped if 1. the receiver is deactivated by ...
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FIFO. Inserted SYN characters are not part of the frame and thus not used for CRC calculation. 4.5.4 Special Functions 4.5.4.1 Preamble Transmission If enabled via register CCR2H transmitted with a selectable number ...
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Reception of Frames: The logical processing of received S-frames is performed by the SCC without interrupting the host. The host is merely informed by interrupt of status changes in the remote station (receiver ready / receiver not ready) and protocol ...
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RR , REJ SREJ , Y CRC Error or Abort ? N Y Prot. Error ? N Int PCE : RESET RRNR 1 Wait for N Acknowledge ? Y N N(R)=V (S)+ (S) +1 (S) ...
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Transmission of Frames: The SCC autonomously transmits S commands and S responses in the auto mode. Either transparent or I-frames can be transmitted by the user. The software timer has to be operated in the internal timer mode to transmit ...
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Rec. RNR Set RRNR 1 t Run Out n1-1 Load Rec. Ready ? Y Trm RR Trm RNR Command p=1 Command p=1 , ...
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Examples The interaction between SCC and the host during transmission and reception of I-frames is illustrated in the following two figures. The flow control with RR/RNR of I-frames during transmission/reception is illustrated in and protocol errors are shown in I ...
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Protocol Error Handling: Depending on the error type, erroneous frames are handled according to Table 14 Error Handling Frame Type Error Type I CRC error Aborted Unexpected N(S) Unexpected N(R) S CRC error Aborted Unexpected N(R) With I-field Note: The ...
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Note: The broadcast address may be programmed in register required. In this case registers The primary station has to operate in transparent HDLC mode. Reception of Frames: The reception of frames functions similarly to the LAPB/LAPD operation (see Duplex LAPB/LAPD ...
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RR(0)p=1 RR(0)f=1 Secondary Figure 54 No Data to Send: Data Reception/Transmission XIF RR(0)p=1 RR(1)p=0 ALLS Figure 55 Data Transmission (without error), Data Transmission (with error) 4.6.3 Signaling System #7 (SS7) Operation The SEROCCO-M supports the signaling system #7 (SS7) which ...
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Receive The SS7 protocol is supported by the following hardware features in receive direction: • Recognition of Signaling Unit type • Discard of repeatedly received FISUs and optionally of LSSUs if content is unchanged • Check if the length of ...
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FISUs continues. The internally generated FISUs contain FSN and BSN of the last transmitted signaling unit written to XFIFO. Using CMDRL.XREP=’1’, the contents of XFIFO (1..32 bytes) can be sent continuously. This cyclic transmission can be stopped with ...
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Register Description 5.1 Register Overview The SEROCCO-M global registers are used to configure and control the Serial Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation. All registers are 8-bit organized registers, but grouped and optimized for 16 ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write 12 62 STARL STARH CMDRL CMDRH CCR0L CCR0H ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write 27 77 UDAC3 TTSA0 TTSA1 TTSA2 TTSA3 RTSA0 ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write 44 94 AMRAL1 AMRAH1 AMRAL2 AMRAH2 RLCRL RLCRH ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write ... Reserved Channel specific DMA registers ... Reserved XBCL H ...
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Detailed Register Description 5.2.1 Global Registers Each register description is organized in three parts: • a head with general information about reset value, access type (read/write), offset address and usual handling; • a table containing the bit information (name ...
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Register 2 GMODE Global Mode Register CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU evaluated by SEROCCO-M Bit EDMA EDMA Enable External DMA Support This bit field controls the ...
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OSCPD Oscillator Power Down Setting this bit to ’0’ enables the internal oscillator. For power saving purposes (escpecially if clock modes are used which do not need the internal oscillator) this bit may remain set to ’1’. OSCPD=’0’ OSCPD=’1’ Note: ...
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Register 3 GSTAR Global Status Register CPU Accessibility: read only Reset Value Offset Address typical usage: written by SEROCCO-M evaluated by CPU Bit 7 6 GPI DMI GPI General Purpose Port Indication This bit indicates, that ...
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ISA2 Channel A Interrupt Status Register 2 ISA1 Channel A Interrupt Status Register 1 ISA0 Channel A Interrupt Status Register 0 ISB2 Channel B Interrupt Status Register 2 ISB1 Channel B Interrupt Status Register 1 ISB0 Channel B Interrupt Status ...
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Register 4 GPDIRL GPP Direction Register (Low Byte) CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU, evaluated by SEROCCO-M Bit Register 5 GPDIRH GPP Direction Register (High Byte) ...
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GPnDIR GPP Pin n Direction Control This bit selects between input and output function of the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet Register Description (GPDIRH) output input (reset value) 5-127 PEB 20532 PEF 20532 (-) ...
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Register 6 GPDATL GPP Data Register (Low Byte) CPU Accessibility: read/write Reset Value: - Offset Address typical usage: written by CPU(outputs) and SEROCCO-M(inputs), evaluated by SEROCCO-M(outputs) and CPU(inputs) Bit Register 7 GPDATH GPP Data ...
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GPnDAT GPP Pin n Data I/O Value This bit indicates the value of the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet Register Description (GPDATH) If direction is input: input level is ’low’; if direction is output: ...
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Register 8 GPIML GPP Interrupt Mask Register (Low Byte) CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU, evaluated by SEROCCO-M Bit Register 9 GPIMH GPP Interrupt Mask Register ...
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GPnIM GPP Pin n Interrupt Mask This bit controls the interrupt mask of the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet Interrupt generation is enabled. An interrupt is generated on any state transition of the corresponding ...
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Register 10 GPISL GPP Interrupt Status Register (Low Byte) CPU Accessibility: read only Reset Value Offset Address typical usage: written by SEROCCO-M, read and evaluated by CPU Bit Register 11 GPISH GPP ...
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GPnI GPP Pin n Interrupt Indiction This bit indicates if an interrupt event occured on the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet No interrupt indication is pending at this pin (no state transition has occured). ...
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Register 12 DCMDR DMA Command Register CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU, evaluated by SEROCCO-M Bit 7 6 RDTB 0 RDTB Reset DMA Transmit Channel B RDRB Reset DMA Receive ...
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Register 13 DISR DMA Interrupt Status Register CPU Accessibility: read only Reset Value Offset Address typical usage: written by SEROCCO-M, evaluated by CPU Bit RBFB Note: Interrupt indications are stored even if masked ...
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TDTEB Transmit DMA Transfer End Channel B TDTEA Transmit DMA Transfer End Channel A This bit set to ’1’ indicates that the data is completely moved from the transmit buffer to the on-chip transmit FIFO, i.e. the transmit byte count ...
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Register 14 DIMR DMA Interrupt Mask Register CPU Accessibility: read/write Reset Value Offset Address typical usage: Bit MRBFB MRBFB Mask Receive Buffer Full Interrupt Channel B MRBFA Mask Receive Buffer Full Interrupt Channel ...
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Channel Specific SCC Registers Each register description is organized in three parts: • a head with general information about reset value, access type (read/write), channel specific offset addresses and usual handling; • a table containing the bit information (name ...
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Receive FIFO (RFIFO) Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus mode only 16-bit accesses to RFIFO are allowed. Only ...
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If DMA operation is enabled, the SEROCCO-M autonomously requests data transfer to the XFIFO by asserting the DRT line to the external DMA controller. The DRT line remains active until the beginning of the last transmit data byte/word transfer. For ...
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Register 17 STARL Status Register (Low Byte) CPU Accessibility: read only Reset Value Channel A Offset Address typical usage: updated by SEROCCO-M read and evaluated by CPU Bit 7 6 Command Status H XREPE 0 XREPE ...
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XREPE Transmit Repetition Executing XREPE=’0’ XREPE=’1’ TEC TIC Executing TIC=’0’ TIC=’1’ CEC Command Executing CEC=’0’ CEC=’1’ Note: CEC will stay active if the SCC is in power-down mode serial clock, needed for command execution, is available. FCS ...
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XDOV Transmit FIFO Data Overflow XDOV=’0’ XDOV=’1’ XFW Transmit FIFO Write Enable XFW=’0’ XFW=’1’ CTS CTS (Clear To Send) Input Signal State CTS=’0’ CTS=’1’ Note: A transmit clock is necessary to detect the input level of CTS. Optionally this input ...
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SYNC Synchronization Status This bit indicates whether the receiver is in synchronized state. After a ’HUNT’ command ’SYNC’ bit is cleared and the receiver starts searching for a SYNC character. When found the ’SYNC’ status bit is set immediately, an ...
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WFA Wait For Acknowledgement This status bit is significant in Automode only. It indicates whether the Automode state machine expects an acknowledging I- or S-Frame for a previously sent I-Frame. WFA=’0’ WFA=’1’ XRNR Transmit RNR Status This status bit is ...
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Register 19 CMDRL Command Register (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU, evaluated by SEROCCO-M Bit 7 6 Timer H STI TRES A STI TRES B STI ...
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For a write access to the register, the new value gets OR’ed with the current register contents. The ’CEC’ bit in register STARL/STARH STI Start Timer Command Self-clearing command bit: HDLC Automode: In HDLC Automode the timer is used internally ...
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TXOFF Transmit Off Command Self-clearing command bit: This command bit is significant if in-band flow-control is selected. TXOFF=’1’ TXON Transmit On Command Self-clearing command bit: This command bit is significant if in-band flow-control is selected. TXON=’1’ XRES Transmitter Reset Command ...
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XME Transmit Message End Self-clearing command bit: XME=’1’ XREP Transmission Repeat Command Self-clearing command bit: XREP=’1’ RMC Receive Message Complete Self-clearing command bit: RMC=’1’ RNR Receiver Not Ready Command NON self-clearing command bit: This command bit is significant in HDLC ...
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HUNT Enter Hunt State Command Self-clearing command bit: HUNT=’1’ RFRD Receive FIFO Read Enable Command Self-clearing command bit: RFRD=’1’ RRES Receiver Reset Command Self-clearing command bit: RRES=’1’ Data Sheet Register Description (CMDRH) This command forces the receiver to enter its ...
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Register 21 CCR0L Channel Configuration Register 0 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit 7 6 misc. H VIS PSD VIS ...
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VIS Masked Interrupts Visible VIS=’0’ VIS=’1’ Note: Interrupts masked in registers interrupt. PSD DPLL Phase Shift Disable This option is only applicable in the case of NRZ or NRZI line encoding is selected. PSD=’0’ PSD=’1’ BCR Bit Clock Rate This ...
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TOE Transmit Clock Out Enable For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock can be monitored on pin TxCLK as an output signal. In clock mode 5, a time slot control signal marking ...
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SC(2:0) Serial Port Configuration This bit field selects the line coding of the serial port. Note, that special operation modes and settings may require or exclude operation in special line coding modes. Refer to the ’prerequisites’ in the dedicated mode ...
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Register 23 CCR1L Channel Configuration Register 1 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit CRL C32 0 0 ...
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CRL CRC Reset Value This bit defines the initial value of the internal transmit/receive CRC generators: CRL=’0’ CRL=’1’ C32 CRC 32 Select This bit enables 32-bit CRC operation for transmit and receive. C32=’0’ C32=’1’ Note: The internal ’valid frame’ criteria ...
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DIV Data Inversion This bit is only valid if NRZ data encoding is selected via bit field SC(2:0) in register CCR0H. DIV=’0’ DIV=’1’ ODS Output Driver Select The transmit data output pin TxD can be configured as push/pull or open ...
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FRTS Flow Control (using signal RTS) Bit ’FRTS’ together with bit ’RTS’ determine the function of signal RTS: RTS, FRTS FCTS Flow Control (using signal CTS) This bit controls the function of ...
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CAS Carrier Detect Auto Start CAS = ’0’ CAS = ’1’ Note: (1) In clock mode 1, 4 and 5 this bit must be set to ’0’. (2) A receive clock must be provided for the autonomous receiver control function ...
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Register 25 CCR2L Channel Configuration Register 2 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit MDS(1: ...
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MDS(1:0) Mode Select This bit field selects the HDLC protocol sub-mode including the ’extended transparent mode’. MDS = ’00’ MDS = ’01’ MDS = ’10’ MDS = ’11’ Note: ’MDS(1:0)’ must be set to ’10’ if any PPP mode is ...
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PPPM(1:0) PPP Mode Select This bit field enables and selects the HDLC PPP protocol modes: PPPM = ’00’ No PPP protocol operation. The HDLC sub-mode is PPPM = ’01’ Octet synchronous PPP protocol operation. PPPM = ’10’ Asynchronous PPP protocol ...
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SLEN SYNC Character Length This bit selects the SYNC character length in BISYNC/MONOSYNC operation mode: SLEN = ’0’ SLEN = ’1’ BISNC Select MONOSYNC/BISYNC Mode This bit selects BISYNC or MONOSYNC operation mode: BISNC = ’0’ BISNC = ’1’ MCS ...
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NPRE(1:0) Number of Preamble Repetitions This bit field determines the number of preambles transmitted: NPRE = ’00’ 1 preamble. NPRE = ’01’ 2 preambles. NPRE = ’10’ 4 preambles. NPRE = ’11’ 8 preambles. ITF Interframe Time Fill This bit ...
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XCRC Transmit CRC Checking Mode XCRC=’0’ XCRC=’1’ FLON Flow Control Enable In ASYNC mode, in-band flow control is supported: FLON=’0’ FLON=’1’ CAPP CRC Append In BISYNC mode the CRC generator can be activated: CAPP = ’0’ CAPP = ’1’ Data ...
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CRCM CRC Mode Select In BISYNC mode the CRC generator can be configured for two different generator polynoms: CRCM = ’0’ CRCM = ’1’ Data Sheet CRC-16 The polynominal CRC-CCITT The polynominal is ...
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Register 27 CCR3L Channel Configuration Register 3 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ELC AFX TCDE 0 ...
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ELC Enable Length Check This bit is only valid in HDLC SS7 mode: If the number of received octets exceeds 272 + 7 within one Signaling Unit, reception is aborted and bit RSTA.RAB is set. ELC=’0’ ELC=’1’ TCDE Termination Character ...
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SLOAD Enable SYN Character Load In BISYNC mode, SYN characters might be filtered out or stored to the SCC receive FIFO. SLOAD=’0’ SLOAD=’1’ CSF Compare Status Field This bit is only valid in HDLC SS7 mode: If the status fields ...
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DXS Disable Storage of XON/XOFF Characters In ASYNC mode, XON/XOFF characters might be filtered out or stored to the SCC receive FIFO: DXS=’0’ DXS=’1’ XBRK Transmit Break XBRK=’0’ XBRK=’1’ ESS7 Enable SS7 Mode This bit is only valid in HDLC ...
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PAR(1:0) Parity Format This bit field selects the parity generation/checking mode: PAR = ’00’ PAR = ’01’ PAR = ’10’ PAR = ’11’ The received parity bit is stored in the SCC receive FIFO depending on the selected character format: ...
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RADD Receive Address Forward to RFIFO This bit is only valid – HDLC sub-mode with address field support is selected (Automode, Address Mode 2, Address Mode 1) – in SS7 mode RADD=’0’ RADD=’1’ DPS Data Parity Storage Only ...
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RFDF Receive FIFO Data Format In ASYNC mode, the character format is determined as follows: RFDF='0' Data Byte Char7 7 Char8 (no parity bit stored) P: Parity bit stored ...
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RFTH(1:0) Receive FIFO Threshold This bit field defines the level up to which the SCC receive FIFO is filled with valid data before an ’RPF’ interrupt is generated. (In case of a ’frame end / block end’ condition the SEROCCO-M ...
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Register 29 PREAMB Preamble Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit PRE(7:0) Preamble This bit ...
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Register 30 TOLEN Time Out Length Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit TOIE B 0 ...
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Register 31 ACCM0 PPP ASYNC Control Character Map 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ...
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Register 33 ACCM2 PPP ASYNC Control Character Map2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ...
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ACCM ASYNC Character Control Map This bit field is valid in HDLC asynchronous and octet-synchronous PPP mode only: Each bit selects the corresponding character (indicated as hex value 1F ..00 in the register description table) as control character which has ...
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Register 35 UDAC0 User Defined PPP ASYNC Control Character Map 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ...
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Register 37 UDAC2 User Defined PPP ASYNC Control Character Map 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ...
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AC3..0 User Defined ASYNC Character Control Map This bit field is valid in HDLC asynchronous and octet-synchronous PPP mode only: These bit fields define user determined characters as control characters which have to be mapped into the transmit data stream. ...
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Register 39 TTSA0 Transmit Time Slot Assignment Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ...
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Register 41 TTSA2 Transmit Time Slot Assignment Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit Register 42 ...
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The following register bit fields allow flexible assignment of bit- or octet-aligned transmit time-slots to the serial channel. For more detailed information refer to chapters Mode 5a (Time Slot Mode)” on Page 55 on Page 62. TCS(2:0) Transmit Clock Shift ...
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Register 43 RTSA0 Receive Time Slot Assignment Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ...
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Register 45 RTSA2 Receive Time Slot Assignment Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit Register 46 ...
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The following register bit fields allow flexible assignment of bit- or octet-aligned receive time-slots to the serial channel. For more detailed information refer to chapters Mode 5a (Time Slot Mode)” on Page 55 on Page 62. RCS(2:0) Receive Clock Shift ...
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Register 47 PCMTX0 PCM Mask Transmit Direction Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit T07 T06 T07 T06 ...
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Register 49 PCMTX2 PCM Mask Transmit Direction Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit T23 T22 T23 T22 ...
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PCMTX PCM Mask for Transmit Direction This bit field is valid in clock mode 5 only and the PCM mask must be enabled via bit ’TEPCM’ in register TTSA1. Each bit selects one of 32 (8-bit) transmit time-slots. The offset ...
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Register 51 PCMRX0 PCM Mask Receive Direction Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit R07 R06 R07 R06 ...
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Register 53 PCMRX2 PCM Mask Receive Direction Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit R23 R22 R23 R22 ...
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PCMRX PCM Mask for Receive Direction This bit field is valid in clock mode 5 only and the PCM mask must be enabled via bit ’REPCM’ in register RTSA1. Each bit selects one of 32 (8-bit) receive time-slots. The offset ...
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Register 55 BRRL Baud Rate Register (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit ...
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BRM(3:0) Baud Rate Factor ’M’ BRN(5:0) Baud Rate Factor ’N’ These bit fields determine the division factor of the internal baud rate generator. The baud rate generator input clock and the usage of baud rate generator output depends on the ...
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Register 57 TIMR0 Timer Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit Register 58 TIMR1 Timer Register ...
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Register 59 TIMR2 Timer Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-M Bit Register 60 TIMR3 Timer Register ...
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SRC Clock Source (valid in clock mode 5 only) This bit selects the clock source of the internal timer: SRC = ’0’ SRC = ’1’ TMD Timer Mode This bit must be set to ’1’ if HDLC Automode operation is ...
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TVALUE Timer Expiration Value (23:0) This bit field determines the timer expiration period ’t’: (’CP’ is the clock period, depending on bit ’SRC’.) Data Sheet Register Description (TIMR3 × t TVALUE 5-200 PEB 20532 ...