PXB4360FV1.1 Infineon Technologies AG, PXB4360FV1.1 Datasheet
PXB4360FV1.1
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PXB4360FV1.1 Summary of contents
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ICs for Communications Content Addressable Memory Element CAME PXB 4360 F Version 1.1 Data Sheet 07.2000 Version 1.1 ...
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... Critical components of Infineon Technologies AG, may only be used in life-support devices or systems express written approval of Infineon Technologies AG critical component is a component used in a life-support device or system whose failure can reasonably be ex- pected to cause the failure of that life-support device or system affect its safety or effectiveness of that device or system ...
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Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 Chipset Configuration for Main ATM Layer Functionality . . . . . . . . . . . . . . . . . . . 7 Figure 2 Chipset Configuration for Main ATM Layer Functionality Plus Full ...
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Table 1: Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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The PXB 4360 F ATM Content Addressable Memory Element (CAME member of the Infineon ATM622 chip set. The entire chip set consists of: • PXB 4330 E ATM Buffer Manager (ABM) • PXB 4340 E ATM OAM Processor ...
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Conn. RAM UTOPIA PXB 4350 E PHYs Conn. RAM UTOPIA PXB 4350 E PHYs Data Sheet Pol. Conn. RAM RAM UTOPIA PXB 4340 E ALP AOP Conn. Conn. RAM RAM Pol. CAME Conn. RAM RAM UTOPIA PXB 4340 E ALP ...
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The ATM 622 Layer devices can be used as .... ...a full switch in: ADSL Concentrators / Multiplexers (DSLAM) Access Multiplexers Access Concentrators Multiservice switches ...Line card in: Workgroup Switches Edge Switches Core Switches UTOPIA Data Sheet UTOPIA 1-9 UTOPIA ...
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UTOPIA UTOPIA Due to their immensely flexible scaling facilities, feature set, and throughput, the Infineon ATM622 layer chips are ideal devices for almost any ATM system solution. Data Sheet UTOPIA 1-10 07.2000 ...
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ALP Co-processor for Address Reduction to search for a Port Number PN, VPI and VCI the corresponding Local Connection Identifier LCI • Delivers search result during one cell cycle for Bit rates up to 686 MBit/s • CAME supports ...
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Test/JTAG Interface PXB 4360 CAME ALP - Data Interface Data Sheet F ALP - Address Interface 1-12 CAME Cascade Interface 07.2000 ...
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TMD0 109 GND 110 V 111 CC 112 GND TMD1 113 V 114 CC TMD2 115 GND 116 TMD3 117 V 118 CC TMD4 119 GND 120 TMD5 121 V 122 CC TMD6 123 GND 124 TMD7 125 ...
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The following explanations apply to all pins within a field in the following table: 1) Pins with a attached are connected with an internal pull up resistor. 20 RES 54 CLK 99, 97, 95, 93, 91, DAT 89, 87, 85, ...
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CA 137, 135, 133 CI (2:0) 131, 129, 127 CO (2: TRST 1) 3 TDI 1) 7 TCK 1) 5 TMS 144 TDO 125, 123, 121, TMD 119, 117, 115, (7:0) 113, 109 139 VBIAS 140 RBIAS ...
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11, 15, 19, 23, 27, 29, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 73, 78, 80, 84, 88, 92, 96, 100, 102, 105, 108, 111, 114, 118, 122, 126, 130, 134, 138, 142 ...
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One CAME chip is connected to the ALP if only 8k connections are supported. For 16k connections, a second CAME is cascaded to the first CAME. The ALP is the master device that controls the CAME. If two CAME chips ...
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ARCCLK ARCCS ARCWE ARCOE ARCRES ARCADR(3:0) ARCDAT(16:0) ALP Data Sheet CLK CS WE CAME OE (Master) RES ADR(3:0) EN16 1 k GND DAT(16:0) DAT(32:17 3.3 V CI(2:0) CO(2:0) CO(2:0) CI(2:0) CLK CS CAME WE (Slave) OE RES ...
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The PXB 4360 Content Addressable Memory Element (CAME) that searches for a programmable 32-bit pattern the corresponding programmable 14-bit pattern; or vice versa. Additionally, two search bits are provided to support the search for unused entries and ...
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The CAME can be configured, operated, and tested using six Request Commands. Each Request Command is a combination of various write and read commands transmitted via the Data bus of the CAME. The Address bus selects the Request Commands. The ...
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The auxiliary bit VCON defines whether an entry is valid or invalid. This mechanism is used to prevent overwriting a valid connection, if the corresponding configuration bit CEE TESTMODE register is set. A second configuration bit, CLE available to prevent ...
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Configure the response on Write Request Command number 4 • Configure the response on Search Request Command number 3 • Configure the test functions of the CAME. Two Search Request Commands are supported by the CAME. Search Request Command ...
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CAME Data bit (16) is used as parity line and completes the ARCDAT(1:15) and ACRADR(0:3) to odd parity. Note: Shaded fields represent unused bits. bit Write to address C H Wait for ...
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Write to address 2 H Write to address B H Write to address 3 H Wait for command execution Read from address 6 H Read from address E H bit ...
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Note: Shaded fields represent unused bits. 1) bit: Write to address 4 of CAME H PN(3:0) VPI(11:0) Wait for command execution Read from address 6 of CAME H bit: Write to address 5 of CAME H PN(3:0) VPI(11:0) Wait for ...
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Write to address 2 of CAME H Write to address 3 of CAME H PN(3:0) VPI(11:0) Wait for command execution Read from address 6 of CAME H bit: Write to address 0 of CAME H Wait for command execution ...
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A request command is a sequence of write and read commands at different addresses. The address selects the register and the consequent action performed by the CAME. Therefore, different request commands can write to or read from the same register. ...
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Valid Connection flag: 0 Connection not valid. 1 Connection valid. Path Intermediate point flag: 0 Address reduction is performed over PN, VPI and VCI. 1 Path intermediate point; address reduction is performed only over PN and VPI. Port Number VPI ...
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These registers contain the PN, VPI, VCI combination which will be compared to all lines in CAME during search requests #1,#2 and #3. The registers are loaded from the bus interface at the beginning of the respective search request. Write ...
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This register contains the address of the line to which data is written in a write request #4, or from which data is read in a read request #5. The DLCI register is loaded from the bus interface at the ...
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The result of searching in the memory array is the LCI value of the first line that matches the data in the SPN/SVPI/SVCI registers. This result is stored in the SLCI register. At the end of all search requests (#1..3), ...
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These registers contain a complete entry consisting of PN/VPI/VCI, the P_IP flag and the VCON flag. The read data contained in the CAME memory line, selected with the DLCI register contents, is transferred to these registers. At the end of ...
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Port Number Virtual Path Identifier value of the ATM Header. PN and VPI are in a 16-bit field. Any subdivision within the 16 bits for the PN and VPI is allowed. Virtual Channel Identifier Data Sheet 5-33 07.2000 ...
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Status information generated by the control logic in the CAME indicates the success of commands or detected failures. At the end of each command cycle, status information about the current operation is transferred from the CAME to the ALP. The ...
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Error 6) (parity) Transition conditions: Read Address Value after reset 0000 H 16-Bit Mode request request 6: 32-Bit Mode request ...
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:S1/ Busy 10 Alarm Error Data Sheet Command was executed without problems. Indication in S1/S0: S1/S0 = 0/0. Command execution is still in progress. ...
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The testmode register is used in the test request #6. The testmode register acts as an intermediate stage for access to the configuration (MODE, TMODE), test (TMUX) and version (VER0..3) registers which are selected by the selection field. The control ...
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Control field 0 1 Control field 0 1 Data field Data Sheet Modify and Read; not usable for selection (100:111) Read Master is accessed Slave is accessed 5-38 07.2000 ...
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For request #1, the VSET portion for comparison is VCED set request #2, the settings VSET = 1, VCED = 0 and VPED = 0 are used. For request #3, all three VSET, VCED and VPED modes ...
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Disturbed Parity Generation. Generate a bus parity error in the read access at the end of this command cycle. This bit is automatically reset. DPG is not supported by the ALP! 0 Default CI(2) / CO(2) data If this bit ...
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TMODE register use is allowed only if the MODE register is set to the default values mentioned in on page 39. The TMODE register bits cause the following functional changes: reserved(4:0) Reserved, do not activate. 000000 Default Test Write Enable. ...
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For test only. This register should be set to 0 for normal operation (TMUX disabled): 000000000 0 Version number, octet 0. Version number bits 7..0 contain 2F Data Sheet TMUX(7:0) Default VER0(7:0) Value . H 5-42 TMUX(8) VER0(8) 07.2000 ...
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Value Version number, octet 1. Version number bits 15..8 contain 70 0 Value Version number, octet 2. Version number bits 23..16 contain 0B Data Sheet VER1(7: VER2(7: 5-43 VER1(8) VER2(8) 07.2000 ...
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Version number, octet 3. Version number bits 31..24 contain 0B Data Sheet VER3(7:0) Value . H 5-44 VER3(8) 07.2000 ...
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All communication with ALP is done using the data interface. The data interface consists of the following signals, as shown in DAT(0) Odd parity. Selected to create parity over ADR and DAT bidirectional 1) DAT(31..1) Data Bus DAT(32) Data Bus ...
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For more demanding applications, two CAME chips can be cascaded to build up one virtual device with double capacity and the identical physical bus interface to an external controller. The Cascade Interface is used for this purpose and consists of ...
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For single chip applications, the CAME device must be configured as master by CA and the CI(1..0) inputs must be supplied with low level, pretending an “always mismatch” condition of the non-existent slave. The CI(2) input is not evaluated by ...
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ALP. Therefore, the chip not selected chip must also wait for the end of the current request before a new request may be started. In search cycles, ...
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Mismatch Master.CO(1.. Mismatch Master: Mismatch Slave.CO(1.. Slave: inactive Single Match Master: inactive Slave.CO(1.. Slave: Single Match Multimatch Master: inactive Slave.CO(1.. Slave: Multimatch In summary, the condition for the CAME to become active ...
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CO(1.. (requests with searching) CO(1.. See table 4 CO(1.. Cascade error CO(1.. Cascade error Data Sheet CO(1.. CO(1.. (requests without (No request searching) processed) ...
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The system clock is passed to CAME at the CLK input. For typical applications, it will be equal to ALP SYS_CLK/2 = 25.92 MHz. This is the only clock supply for the CAME (if the BSCAN interface clock is ignored). ...
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Factory test is supported by the Boundary Scan Interface. It consists of four inputs for control of the TAP-controller and one output described in table 6. The TAP-controller is a part of the BSCAN logic. TCK Clock input TDI Serial ...
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104 78 106 79 109 80 113 81 115 82 117 83 119 84 121 ...
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No Microprocessor Interface is implemented in the CAME. In the CAME, data and control interfaces are identical. For the interface description, refer to "Data Bus and Address Bus Interface" on page 6-45. The CAME mode register ...
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Supply Voltage Input Voltage Output Voltage Power Dissipation Storage Temperature Supply Voltage Ground Input Voltage Output Voltage Input low Voltage Input high Voltage Ambient Temperature Junction Temperature Data Sheet -0.5 to 4.6 CC -0 OUT <0.3 ...
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Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Current at high Voltage Output Current at low Volt- age Input Leakage Current at low Voltage (all inputs except TCK, TMS, TDI, TRSTN) Input Leakage Current at ...
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Input Capacitance Input/Output Capacitance = 3.3 V ± 5 All inputs are driven to = 2.4 V for a logical 1 IH and to = 0.4 V for a logical 0 IL All ...
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Period TCK TCK 1A : Frequency TCK TCK 2 Set up time TMS, TDI before TCK rising 3 Hold time TMS, TDI after TCK rising 4 Delay TCK falling to TDO valid 5 Delay TCK falling to TDO ...
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CLK ADR(3:0) DAT(16:0) Start (first write) Request number 1: Cell processing search for PN/VPI reduction Request number 2: Cell processing search for, PN/VPI/VCI reduction Request number 3: Search request by the microprocessor Request number 4: CAME Write ...
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CLK ADR(3:0) DAT(16:0) CLK ADR(3:0) DAT(16:0) Data Sheet 7- 07.2000 ...
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CLK frequency 2 CLK duty cycle 3 Set up time of CS, WE, ADR and DAT in read and write cycle to CLK 4 Hold time of CS, WE, ADR and DAT in read and write cycle from CLK ...
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CLK frequency 2 CO change from CLK 3 Set up time to CLK 4 Hold time from CLK Data Sheet 0. 7-64 25.92 MHz 07.2000 ...
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Thin Plastic Quad Flatpack) Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 8-65 Dimensions in mm 07.2000 ...
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Joint Test Action Group JTAG standard IEEE Std. 1149.1 ABM PXB 4330 E TM uffer ALP PXB 4350 E TM ayer rocessor AOP PXB 4340 E TM ARC ddress eduction ircuit byte octet = 8 bits CAME ontent ddressable ...