ISL59444IBZ-T13 Intersil, ISL59444IBZ-T13 Datasheet - Page 10

• Manufacturer Part Number: ISL59444IBZ-T13
• Description: IC AMP MULTIPLEX 1GHZ 16SOIC
• Manufacturer: Intersil

Specifications of ISL59444IBZ-T13

• Applications: 4:1 Multiplexer-Amplifier
• Number Of Circuits: 1
• -3db Bandwidth: 1GHz
• Slew Rate: 1515 V/µs
• Current - Supply: 18mA
• Current - Output / Channel: 180mA
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Latch State
The latched control signals allow for synchronized channel
switching. When LE1 is low the master control latch loads the
next switching address (S0, S1), while the closed (assuming
LE2 is the inverse of LE1) slave control latch maintains the
current state. LE2 switching low closes the master latch (with
previous assumption), loads the now open slave latch, and
switches the crosspoint to the newly selected channel. Channel
selection is asynchronous (changes with any control signal
change) if both LE1 and LE2 are low.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dv/dt triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dv/dt triggered clamp imposes a maximum supply
turn-on slew rate of 1V/µs. Damaging currents can flow for
power supply rates-of-rise in excess of 1V/µs, such as
during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 23) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
V+ SUPPLY
V- SUPPLY
POWER
SIGNAL
LOGIC
GND
DE-COUPLING
CAPS
10
PROTECTION
SCHOTTKY
FIGURE 23. SCHOTTKY PROTECTION CIRCUIT
GND
S0
IN0
IN1
V+
V-
V+
V-
ISL59444
V+
V-
V+
V-
PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
• Minimize signal trace lengths. Trace inductance and
• Match channel-channel analog I/O trace lengths and
• Maximize use of AC de-coupled PCB layers. All signal I/O
• Use proper value and location of termination resistors.
• When testing use good quality connectors and cables,
• Minimum of 2 power supply de-coupling capacitors are
• The NIC pins are placed on both sides of the input pins.
CONTROL
resistors and chip capacitors is strongly recommended.
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip
lines are used.
layout symmetry. This will minimize propagation delay
mismatches.
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
Termination resistors should be as close to the device as
possible.
matching cable types and keeping cable lengths to a
minimum.
recommended (1000pF, 0.01µF) as close to the devices
as possible. Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
LOGIC
V+
V-
OUT
EXTERNAL
CIRCUITS
September 21, 2005
FN7451.1