ATT3030 ETC ETC, ATT3030 Datasheet
ATT3030
Available stocks
Related parts for ATT3030
ATT3030 Summary of contents
Page 1
... All FPGAs processed on a QML-certified line Extensive packaging options Table 1. ATT3000 Series FPGAs Max Typical Gate FPGA Logic Range Gates ATT3020 1,500 1,000—1,500 ATT3030 2,000 1,500—2,000 ATT3042 3,000 2,000—3,000 ATT3064 4,500 3,500—4,500 ATT3090 6,000 5,000—6,000 ...
Page 2
ATT3000 Series Field-Programmable Gate Arrays Contents Features ..................................................................... 1 Description ................................................................. 1 Architecture ................................................................ 3 Configuration Memory................................................ 4 I/O Block ..................................................................... 5 Summary of I/O Options ......................................... 6 Configurable Logic Block ............................................ 7 Programmable Interconnect ....................................... 9 General-Purpose Interconnect ............................. ...
Page 3
Data Sheet February 1997 Architecture The perimeter of configurable I/O blocks (IOBs) pro- vides a programmable interface between the internal logic array and the device package pins. The array of configurable logic blocks (CLBs) performs user- specified logic functions. The ...
Page 4
ATT3000 Series Field-Programmable Gate Arrays Configuration Memory The static memory cell used for the configuration mem- ory in the FPGA has been designed specifically for high reliability and noise immunity. Integrity of the FPGA configuration memory based on this design ...
Page 5
Data Sheet February 1997 I/O Block Each user-configurable I/O block (IOB), shown in Figure 3, provides an interface between the external package pin of the device and the internal user logic. Each IOB includes both registered and direct input paths ...
Page 6
ATT3000 Series Field-Programmable Gate Arrays I/O Block (continued) For reliable operation, inputs should have transition times of less than 100 ns and should not be left float- ing. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This ...
Page 7
Data Sheet February 1997 Configurable Logic Block The array of configurable logic blocks (CLBs) provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. The ATT3020 ...
Page 8
ATT3000 Series Field-Programmable Gate Arrays Configurable Logic Block ANY FUNCTION VARIABLES ANY FUNCTION VARIABLES ANY ...
Page 9
Data Sheet February 1997 Programmable Interconnect Programmable interconnection resources in the FPGA provide routing paths to connect inputs and outputs of the IOBs and logic blocks into logical networks. Inter- connections between blocks are composed from a two- layer grid ...
Page 10
ATT3000 Series Field-Programmable Gate Arrays Programmable Interconnect General-Purpose Interconnect General-purpose interconnect, as shown in Figure 9, consists of a grid of five horizontal and five vertical metal segments located between the rows and col- umns of logic and IOBs. Each ...
Page 11
Data Sheet February 1997 Programmable Interconnect Direct Interconnect Direct interconnect (shown in Figure 11) provides the most efficient implementation of networks between adjacent logic or IOBs. Signals routed from block to block using the direct interconnect exhibit minimum interconnect propagation ...
Page 12
ATT3000 Series Field-Programmable Gate Arrays Programmable Interconnect Figure 12. ATT3020 Die Edge I/O Blocks with Direct Access to Adjacent CLB 12 (continued) February 1997 Lucent Technologies Inc. ...
Page 13
Data Sheet February 1997 Programmable Interconnect Long Lines The long lines bypass the switch matrices and are intended primarily for signals which must travel a long distance, or must have minimum skew among multiple destinations. Long lines, shown in Figure ...
Page 14
ATT3000 Series Field-Programmable Gate Arrays Programmable Interconnect A buffer in the upper left corner of the FPGA chip drives a global net which is available to all .k inputs of logic blocks. Using the global buffer for a clock signal ...
Page 15
Data Sheet February 1997 Programmable Interconnect Figure 15A. 3-State Buffers Implement a Wired-AND Function WEAK KEEPER CIRCUIT Figure 15B. 3-State Buffers Implement a Multiplexer BIDIRECTIONAL GLOBAL NET INTERCONNECT BUFFERS GG HG P40 P41 Lucent Technologies Inc. ...
Page 16
ATT3000 Series Field-Programmable Gate Arrays Programmable Interconnect Crystal Oscillator Figure 16 shows the location of an internal high-speed inverting amplifier which may be used to implement an on-chip crystal oscillator associated with the auxil- iary buffer in the ...
Page 17
Data Sheet February 1997 Configuration Initialization Phase An internal power-on-reset circuit is triggered when power is applied. When V reaches the voltage where CC portions of the FPGA begin to operate (2 V), the programmable I/O output ...
Page 18
ATT3000 Series Field-Programmable Gate Arrays Configuration (continued) USER I/O PINS WITH HIGH-IMPEDANCE PULL-UP INIT = LOW INITIALIZATION POWER-ON TIME DELAY CLEAR RESET CONFIGURATION ACTIVE MEMORY YES Figure 18. State Diagram of Configuration Process for Powerup and Reprogram Length count control ...
Page 19
Data Sheet February 1997 Configuration (continued) Configuration Data Configuration data to define the function and interconnection within an FPGA are loaded from an external storage at powerup and on a reprogram signal. Several methods of automatic and controlled loading of ...
Page 20
... An additional final postamble bit is added for each slave device, and the result rounded up to byte boundary. The length count is two less than the number of resulting bits. Timing of the assertion of DONE and termination of the internal RESET may each be programmed to occur one cycle before or after the I/O outputs become active. 20 ATT3030 ATT3042 2000 3000 ...
Page 21
Data Sheet February 1997 Configuration (continued) The specific data format for each device is produced by the bit stream generation program, and one or more of these files can then be combined and appended to a length count preamble and ...
Page 22
ATT3000 Series Field-Programmable Gate Arrays Configuration Modes Master Mode In master mode, the FPGA automatically loads configu- ration data from an external memory device. There are three master modes which use the internal timing source to supply the configuration clock ...
Page 23
Data Sheet February 1997 Configuration Modes (continued GENERAL- PURPOSE USER I/O PNS SYSTEM RESET Lucent Technologies Inc. ATT3000 Series Field-Programmable Gate Arrays +5 V USER CONTROL OF HIGHER ORDER FROM ADDRESS BITS CAN BE USED TO SELECT FROM ...
Page 24
ATT3000 Series Field-Programmable Gate Arrays Configuration Modes (continued) Peripheral Mode Peripheral mode provides a simplified interface through which the device may be loaded byte-wide processor peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded ...
Page 25
Data Sheet February 1997 Configuration Modes (continued) Slave Mode Slave mode provides a simple interface for loading the FPGA configuration as shown in Figure 24. Serial data is supplied in conjunction with a synchronizing input clock. Most slave mode applications ...
Page 26
ATT3000 Series Field-Programmable Gate Arrays Configuration Modes (continued) Daisy Chain The ORCA Foundry for ATT3000 Development System is used to create a composite configuration bit stream for selected FPGAs including a preamble, a length count for the total bit stream, ...
Page 27
Data Sheet February 1997 Special Configuration Functions The configuration data includes control over several special functions in addition to the normal user logic functions and interconnects: Input thresholds Readback enable DONE pull-up resistor DONE timing RESET timing Oscillator frequency divided ...
Page 28
ATT3000 Series Field-Programmable Gate Arrays Special Configuration Functions (continued) Reprogram The FPGA configuration memory can be rewritten while the device is operating in the user’s system. To initiate a reprogramming cycle, the dual-function pack- age pin DONE/ must be given ...
Page 29
Data Sheet February 1997 Performance Device Performance The high performance of the FPGA is due in part to the manufacturing process, which is similar to that used for high-speed CMOS static memories. Performance can be measured in terms of minimum ...
Page 30
ATT3000 Series Field-Programmable Gate Arrays Performance (continued) Logic Block Performance Logic block performance is expressed as the propaga- tion time from the interconnect point at the input of the combinatorial logic to the output of the block in the interconnect ...
Page 31
Data Sheet February 1997 Performance (continued) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 –55 – TEMPERATURE (°C) Figure 28. Change in Speed Performance CLB R1 TIMING: INCREMENTAL AND ...
Page 32
ATT3000 Series Field-Programmable Gate Arrays Power Power Distribution Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated V ground ring surrounding the logic array ...
Page 33
Data Sheet February 1997 Power (continued) Power Dissipation The FPGA exhibits the low power consumption charac- teristic of CMOS ICs. The configuration option of TTL chip input threshold requires power for the threshold reference. The power required by the static ...
Page 34
ATT3000 Series Field-Programmable Gate Arrays Pin Information Table 4. Permanently Dedicated Pins Symbol V Two to eight (depending on package type) connections to the nominal +5 V supply voltage. All CC must be connected. GND Two to eight (depending on ...
Page 35
Data Sheet February 1997 Pin Information (continued) Table 5. I/O Pins with Special Functions Symbol M2 Mode 2. This input has a passive pull-up during configuration. Together with M0 and M1 sampled before the start of configuration to ...
Page 36
ATT3000 Series Field-Programmable Gate Arrays Pin Information (continued) Table 5. I/O Pins with Special Functions (continued) Symbol RCLK During master parallel mode configuration, memory device (normally not used). RDY/ BUSY During peripheral parallel mode configuration, this pin indicates when the ...
Page 37
Data Sheet February 1997 Pin Information (continued) Table 6A. ATT3000 Family Configuration (44, 68, and 84 PLCC; 100 QFP; and 100 TQFP) Configuration Mode (M2:M1:M0) Slave Master-Serial Peripheral (1:1:1) (0:0:0) (1:0:1) PWRDWN PWRDWN PWRDWN ...
Page 38
ATT3000 Series Field-Programmable Gate Arrays Pin Information (continued) Table 6B. ATT3000 Family Configuration (132 PPGA, 144 TQFP, 160 QFP, 175 PPGA, 208 SQFP) Configuration Mode (M2:M1:M0) Slave Master-Serial Peripheral (1:1:1) (0:0:0) (1:0:1) PWRDWN PWRDWN PWRDWN ...
Page 39
... Data Sheet February 1997 Pin Assignments Table 7. ATT3030 44-Pin PLCC Pinout Pin No TCLKIN–I M0–RTRIG Notes: Peripheral mode and master parallel mode are not supported in the M44 package. Parallel address and data pins are not assigned. ...
Page 40
... ATT3000 Series Field-Programmable Gate Arrays Pin Assignments (continued) Table 8. ATT3020, ATT3030, and ATT3042; 68-Pin PLCC and 84-Pin PLCC Pinout Pin Numbers 68 PLCC 84 PLCC — — — — ...
Page 41
... Note: Table 8 describes the pin assignments for three different chips in two different packages. The function column lists 84 of the 118 pads on the ATT3042 and 84 of the 98 pads on the ATT3030. Ten pads [indicated with a dagger (†)] do not exist on the ATT3020, which has 74 pads ...
Page 42
... M2–I/O 34 HDC–I/O 35 I/O 36 –I/O LDC 37 I/O 38 I/O 39 I/O * Different pin definition than ATT3020/ATT3030/ATT3042 PC84 package. Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-limited Function PLCC 40 I/O 41 –I/O* INIT 42 V ...
Page 43
... Only 100 of the 118 pads on the ATT3042 are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the ATT3030, which has 98 pads; therefore, the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the ATT3020, which has 74 pads; therefore, the corresponding pins have no connections. ...
Page 44
... ATT3000 Series Field-Programmable Gate Arrays Pin Assignments (continued) Table 11. ATT3030, ATT3042, and ATT3064 100-Pin TQFP Pinout 100 Function TQFP 13 GND 14 A13–I/O 15 A6–I/O 16 A12–I/O 17 A7–I/O 18 I/O 19 I/O 20 A11–I/O 21 A8–I/O 22 A10–I/O 23 A9–I GND 26 PWRDWN 27 TCLKIN– ...
Page 45
... I/O D14 LDC–I/O E13 I/O* * Indicates unconnected package pins for the ATT3030. Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-limited. Lucent Technologies Inc. ATT3000 Series Field-Programmable Gate Arrays 132 ...
Page 46
ATT3000 Series Field-Programmable Gate Arrays Pin Assignments (continued) Table 13. ATT3042 and ATT3064 144-Pin TQFP Pinout 144 144 Function TQFP TQFP 1 37 PWRDWN 2 TCLKIN— ...
Page 47
Data Sheet February 1997 Pin Assignments (continued) Table 14. ATT3064 and ATT3090 160-Pin QFP Pinout 160 160 Function QFP QFP I/O ...
Page 48
ATT3000 Series Field-Programmable Gate Arrays Pin Assignments (continued) Table 15. ATT3000 Family 175-Pin PPGA Pinout 175 175 Function PPGA PPGA B2 D13 PWRDWN D4 TCLKIN–I/O B14 B3 I/O C14 C4 I/O B15 B4 I/O D14 A4 I/O C15 D5 I/O ...
Page 49
Data Sheet February 1997 Pin Assignments (continued) Table 16. ATT3000 Family 208-Pin SQFP Pinout 208 208 SQFP Function SQFP 1 — GND 54 3 PWRDWN 55 4 TCLKIN– I/O 59 ...
Page 50
ATT3000 Series Field-Programmable Gate Arrays Package Thermal Characteristics When silicon die junction temperature is below the rec- ommended junction temperature of 125 °C, the temperature-activated failure mechanisms are mini- mized. There are four major factors that affect the ther- mal ...
Page 51
Data Sheet February 1997 Package Thermal Characteristics Table 17. ATT3000 Plastic Package Thermal Characteristics Package 0 fpm 44-Pin PLCC 49 68-Pin PLCC 43 84-Pin PLCC 40 100-Pin QFP 81 100-Pin TQFP 61 132-Pin PPGA 22 144-Pin TQFP 52 160-Pin QFP ...
Page 52
ATT3000 Series Field-Programmable Gate Arrays Package Parasitics (continued) Table 18. Package Parasitics Package Type L W 44-Pin PLCC 3 68-Pin PLCC 3 84-Pin PLCC 3 100-Pin QFP 3 100-Pin TQFP 3 132-Pin PPGA 3 144-Pin TQFP 3 160-Pin QFP 4 ...
Page 53
Data Sheet February 1997 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or ...
Page 54
... Input Signal Transition Time Powerdown Supply Current ATT3020 ATT3030 ATT3042 ATT3064 ATT3090 Quiescent FPGA Supply Current (in addition to ICCPD) CMOS Inputs ATT3020 ATT3030 ATT3042 ATT3064 ATT3090 TTL Inputs Leakage Current Input Capacitance* All Packages Except 175-PGA: All Pins Except XTL1/XTL2 XTL1 and XTL2 175-PGA Package: ...
Page 55
Data Sheet February 1997 Electrical Characteristics Table 20. CLB Switching Characteristics (-50, -70, -100, and -125) Commercial 5.0 V ± 5%; 0 °C CC Description Combinatorial Delay Sequential Delay Clock K to Outputs Clock K ...
Page 56
ATT3000 Series Field-Programmable Gate Arrays Electrical Characteristics Table 21. CLB Switching Characteristics (-3, -4, and -5) Commercial 5.0 V ± 5%; 0 °C CC Description Combinatorial Delay Sequential Delay Clock K to Outputs Clock K ...
Page 57
Data Sheet February 1997 Electrical Characteristics CLB OUTPUT (X,Y) (COMBINATORIAL) CLB INPUT ( CLB CLOCK CLB INPUT (DIRECT IN) CLB INPUT (ENABLE CLOCK) CLB OUTPUT (FLIP-FLOP) CLB INPUT (RESET DIRECT) CLB OUTPUT (FLIP-FLOP) Lucent Technologies Inc. ...
Page 58
ATT3000 Series Field-Programmable Gate Arrays Electrical Characteristics Table 22. IOB Switching Characteristics (-50, -70, -100, and -125) Commercial 5.0 V ± 5%; 0 °C CC Description Symbol Input Delays Pad to Direct In 3 Pad to Registered In ...
Page 59
Data Sheet February 1997 Electrical Characteristics Table 23. IOB Switching Characteristics (-3, -4, and -5) Commercial 5.0 V ± 5%; 0 °C CC Description Symbol Input Delays Pad to Direct In 3 Pad to Registered In — Clock ...
Page 60
ATT3000 Series Field-Programmable Gate Arrays Electrical Characteristics I/O BLOCK (I) I/O PAD INPUT I/O CLOCK (IK/OK) I/O BLOCK (RI) RESET I/O BLOCK (O) I/O PAD OUTPUT (DIRECT) I/O PAD OUTPUT (REGISTERED) I/O PAD TS I/O PAD OUTPUT 60 (continued) 3 ...
Page 61
Data Sheet February 1997 Electrical Characteristics Table 24. Buffer (Internal) Switching Characteristics Commercial 5.0 V ± 5%; 0 °C CC Description Global and Alternate Clock Distribution*: Either Normal IOB Input Pad to Clock Buffer Input or Fast (CMOS ...
Page 62
ATT3000 Series Field-Programmable Gate Arrays Electrical Characteristics RESET M0/M1/M2 VALID DONE/PROG INIT USER STATE (OUTPUT) PWRDWN V (VALID powerup, V must rise from low until V has reached 4 ...
Page 63
Data Sheet February 1997 Electrical Characteristics CCLK (OUTPUT DSCK SERIAL DIN SERIAL DOUT (OUTPUT) Figure 36. Master Serial Mode Switching Characteristics Table 26. Master Serial Mode Switching Characteristics Signal Description CCLK Data-in Setup Data-in Hold Notes: At powerup, ...
Page 64
ATT3000 Series Field-Programmable Gate Arrays Electrical Characteristics A[15:0] D[7:0] RCLK (OUTPUT) CCLK (OUTPUT) DOUT (OUTPUT) Note: The EPROM requirements in this timing diagram are extremely relaxed; EPROM access time can be longer than 4000 ns. EPROM data output has no ...
Page 65
Data Sheet February 1997 Electrical Characteristics CS1/CS0 CS2 WS D[7:0] CCLK RDY/BUSY DOUT Note: The requirements in this timing diagram are extremely relaxed; data need not be held beyond the rising edge of within 60 ns after the end of ...
Page 66
ATT3000 Series Field-Programmable Gate Arrays Electrical Characteristics DIN T 1 DCC CCLK DOUT (OUTPUT) Figure 39. Slave Mode Switching Characteristics Table 29. Slave Mode Switching Characteristics Commercial 5.0 V ± 5%; 0 °C CC Signal Description CCLK To ...
Page 67
Data Sheet February 1997 Electrical Characteristics DONE/PROG (OUTPUT) RTRIG (M0 CCL CCLK (1) RDATA (OUTPUT) Figure 40. Program Readback Switching Characteristics Table 30. Program Readback Switching Characteristics Commercial 5.0 V ± 5%; 0 °C CC Signal ...
Page 68
ATT3000 Series Field-Programmable Gate Arrays Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. ...
Page 69
Data Sheet February 1997 Outline Diagrams (continued) 68-Pin PLCC Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 1.27 TYP Lucent Technologies Inc. ATT3000 Series Field-Programmable Gate Arrays 25.27 MAX 24.33 MAX 0.53 MAX ...
Page 70
ATT3000 Series Field-Programmable Gate Arrays Outline Diagrams (continued) 84-Pin PLCC Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 1.27 TYP 70 30.35 MAX 29.16 MAX 0.51 MIN 0.53 MAX February 1997 74 29.16 ...
Page 71
Data Sheet February 1997 Outline Diagrams (continued) 100-Pin QFP Dimensions are in millimeters. 17.20 ± 0.20 14.00 ± 0.20 PIN #1 IDENTIFIER ZONE 100 DETAIL A 0.65 TYP Lucent Technologies Inc. ATT3000 Series Field-Programmable Gate Arrays 81 ...
Page 72
ATT3000 Series Field-Programmable Gate Arrays Outline Diagrams (continued) 100-Pin TQFP Dimensions are in millimeters. 16.00 ± 0.20 14.00 ± 0.20 PIN #1 IDENTIFIER ZONE 100 DETAIL A DETAIL B 0.50 TYP GAGE PLANE SEATING ...
Page 73
Data Sheet February 1997 Outline Diagrams (continued) 132-Pin PPGA Dimensions are in millimeters. 37.08 ± 0.38 1.78 ± 0.20 TYP 4 PLACES PIN A1 CORNER Lucent Technologies Inc. ATT3000 Series Field-Programmable Gate Arrays 37.08 ± 0.38 TYPICAL THERMAL VIA PACKAGE ...
Page 74
ATT3000 Series Field-Programmable Gate Arrays Outline Diagrams (continued) 144-Pin TQFP Dimensions are in millimeters. 22.00 ± 0.20 20.00 ± 0.20 PIN #1 IDENTIFIER ZONE 144 DETAIL A 0.50 TYP 74 109 108 20.00 ± 0.20 22.00 ± ...
Page 75
Data Sheet February 1997 Outline Diagrams (continued) 160-Pin QFP Dimensions are in millimeters. 31.20 ± 0.20 28.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL A 0.65 TYP Lucent Technologies Inc. ATT3000 Series Field-Programmable Gate Arrays 121 120 ...
Page 76
ATT3000 Series Field-Programmable Gate Arrays Outline Diagrams (continued) 175-Pin PPGA Dimensions are in inches. 42.16 ± 0.40 1.78 ± 0.20 TYP 4 PLACES PIN A1 CORNER 76 42.16 ± 0.40 TYPICAL THERMAL VIA PACKAGE ID PIN A1 INDICATOR INDEX MARK ...
Page 77
Data Sheet February 1997 Outline Diagrams (continued) 208-Pin SQFP Dimensions are in millimeters. 30.60 ± 0.20 28.00 ± 0.20 PIN #1 IDENTIFIER ZONE 208 DETAIL A 0.50 TYP Lucent Technologies Inc. ATT3000 Series Field-Programmable Gate Arrays 157 ...
Page 78
ATT3000 Series Field-Programmable Gate Arrays Ordering Information The ATT3000 Series includes standard and high- performance FPGAs. The part nomenclature uses two different suffixes for speed designation. The lower- speed ATT3000 Series devices use a flip-flop toggle rate (-50, -70, -100, ...
Page 79
... M44 M68 -70 — CI -100 — CI -125 — CI ATT3020 -5 — — — -100 CI CI -125 CI CI ATT3030 - -70 — — -100 — — -125 — — ATT3042 -5 — — -4 — — -3 — — -70 — ...
Page 80
ATT3000 Series Field-Programmable Gate Arrays For FPGA technical applications support, please call 1-800-327-9374. Outside the U.S.A., please call 1-610-712-4331. For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro/fpga U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 ...