GM5020 ETC ETC, GM5020 Datasheet
GM5020
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GM5020 Summary of contents
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... Sections in this document and all other related documentation that mention HDCP refer only to the gm5020-H (HDCP-enabled) chip. All other sections apply to both the gm5020-H chip and the gm5020 (non-HDCP) chip. 165 Commerce Valley Dr. West • Thornhill • ON • Canada L3T 7V8 • Tel: (905) 889-5400 • Fax: (905) 889-5422 2150 Gold Street • ...
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Trademarks: RealColor and Ultra-Reliable DVI are trademarks of Genesis Microchip Inc. © Copyright 2002, Genesis Microchip Inc. Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice the customer’s responsibility to obtain ...
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... Cosmetic changes to Table 18 - Maximum Speed of Operation • Modified recommended HSYNC input circuit in Figure 6 - Example Signal Terminations • Modified Figure 4 –Clock Generation Options for gm5020 • Added note “(400mV typical hysteresis)” to all Schmitt trigger inputs in Section 3 - Pin List. • Amended I/O column in Table 6 – Display Port Signals • ...
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... In Section 4.2.2, added definitions of bits PA, CRO, and RO. • Added note in Section 4.17. • In Table 1, added description of REXT pin. • In Table 2, modified description of REXT pin. February 2002 paragraph in section 4.19.1. paragraph of section 4.2.1. iv gm5020 / gm5020-H Data Sheet Nov 2001 Dec 2001 Jan 2002 Feb 2002 C5020-DAT-01Q ...
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... Genesis Microchip 1. Overview ................................................................................................................................... 1 1.1 gm5020 System Design Example....................................................................................... 2 1.2 gm5020/gm5020-H Features .............................................................................................. 3 2. Pinout Diagram ......................................................................................................................... 4 3. Pin List ...................................................................................................................................... 6 4. Functional Description............................................................................................................. 12 4.1 Clocking Options............................................................................................................... 13 4.1.1 TCLK Requirements............................................................................................... 13 4.1.2 Synthesized Clocks ................................................................................................ 16 4.2 Hardware and Software Resets ........................................................................................ 17 4.2.1 Hardware Reset ..................................................................................................... 17 4.2.2 Software Reset....................................................................................................... 17 4.3 Analog to Digital Converter ............................................................................................... 19 4.3.1 Pin Connection ....................................................................................................... 19 4.3.2 ADC Characteristics ............................................................................................... 20 4.3.3 Sync. Signal Support.............................................................................................. 21 4 ...
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... Configuration ............................................................................................. 63 4.18.2 6-Wire Configuration ............................................................................................ 66 4.19 Miscellaneous Functions ................................................................................................ 69 4.19.1 General Purpose Inputs and Outputs (GPIO’s) .................................................... 69 4.19.2 Pulse Width Modulation (PWM) Back Light Control ............................................. 69 4.19.3 Low Power State .................................................................................................. 69 5. Electrical Specifications .......................................................................................................... 70 5.1 DC Characteristics............................................................................................................ 70 5.2 Preliminary AC Characteristics ......................................................................................... 72 6. Ordering Information ............................................................................................................... 76 7. Mechanical Specifications....................................................................................................... 77 February 2002 gm5020/gm5020-H Data Sheet vi C5020-DAT-01Q ...
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... DVI Receiver Characteristics .................................................................................. 25 Table 13. Framestore Bandwidth and Data Widths for Various Formats ................................ 41 Table 14. Bootstrap Signals.................................................................................................... 62 Table 15. Instruction Byte Map ............................................................................................... 64 Table 16. Absolute Maximum Ratings (Both gm5020 and gm5020-H) .................................. 70 Table 17. DC Characteristics.................................................................................................. 71 Table 18. Maximum Speed of Operation ................................................................................ 72 Table 19. ITU-R BT656 Input Port Timing .............................................................................. 74 Table 20. ...
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... Genesis Microchip Figure 1. gm5020 System Design Example............................................................................. 2 Figure 2. gm5020 Pinout Diagram ........................................................................................... 5 Figure 3. gm5020 Functional Block Diagram ......................................................................... 12 Figure 4. TCLK connection (with Crystal Resonator) ............................................................. 13 Figure 5. TCLK parasitic capacitances .................................................................................. 14 Figure 6. TCLK connection (with Optional Resistor) .............................................................. 15 Figure 7. TCLK connection (with Oscillator)........................................................................... 15 Figure 8. Internal Clock Sources............................................................................................ 16 Figure 9 ...
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... Direct Read............................................................................................................. 66 Figure 58. 6-Wire Write Operations (0x1x & 0x2x) .................................................................. 68 Figure 59. 6-Wire Read Operations (0x9x & 0xAx).................................................................. 68 Figure 60. Clock Reference Levels .......................................................................................... 72 Figure 61. Setup and Hold Reference Levels .......................................................................... 73 Figure 62. Propagation Delay Reference Levels ..................................................................... 73 Figure 63. gm5020 292-pin PBGA......................................................................................... 77 February 2002 gm5020/gm5020-H Data Sheet ix C5020-DAT-01Q ...
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... Genesis Microchip The gm5020 is a graphics processing IC providing high-quality images for LCD monitors and other pixelated displays. It combines a triple ADC, the Genesis Ultra-Reliable DVI high quality zoom and shrink scaling engine, frame rate conversion, an on-screen display (OSD) controller, a microprocessor and many other functions in a single device. This high level of integration enables simple, flexible, cost-effective solutions featuring fewer required components ...
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... The chip can be used in a variety of systems, ranging from 'single-chassis' solutions for XGA and SXGA monitors with frame store memory and video inputs. In addition, the gm5020 can be used in mid- range SXGA monitors with no frame store memory. ...
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... TM receiver (DVI 1.0) • • • • • • PACKAGE 3 gm5020/gm5020-H Data Sheet Auto-Configuration / Auto-Detection • Phase and image positioning • Input format detection • Compatibility with all graphic cards and standard VESA modes Frame Store Interface • Fully-programmable 48 / 32-bit wide data path • ...
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... Genesis Microchip 2. PINOUT DIAGRAM The gm5020 is available in a 292-pin PBGA (Ball Gate Array) package. Figure 2 below provides the ball locations for all signals. Power and Ground: DGND Periphery and Core Digital Ground DVDD_3.3 Periphery Digital VDD (3.3V supply) DVDD_2.5 Core Digital VDD (2.5V supply) ...
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... This is SCL for slave-only DDC communication. [Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] For the gm5020 (non-HDCP), this pin is an unused CMOS input that may be left unconnected. However preferred that this pin be connected to a known logic state. For the gm5020-H (HDCP-enabled), this pin is used for DDC Interface for DVI-HDCP communication ...
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... General purpose input/output signals. Open drain option via register bit. [Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant] General purpose input/output signals. Open drain option via register bit. [Bidirectional, 8mA drive output, Schmitt trigger input (400mV typical hysteresis0, 5V-tolerant] 7 gm5020 / gm5020-H Data Sheet C5020-DAT-01Q ...
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... Display output blue data (even or left pixel). [Tri-state output, programmable drive 0-24mA, not 5V-tolerant] Display output red data (odd or right pixel). [Tri-state output, programmable drive 0-24mA, not 5V-tolerant] Display output green data (odd or right pixel). [Tri-state output, programmable drive 0-24mA, not 5V-tolerant] 8 gm5020 / gm5020-H Data Sheet C5020-DAT-01Q ...
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... SDRAM to be byte oriented. This signal is active high. Bit 0 enables FSDATA(7:0). Bit 1 enables FSDATA(15:8). Bit 2 enables FSDATA(23:16). Bit 3 enables FSDATA(31:24). [Tri-state output, 8mA drive, 5V-tolerant] SDRAM multiplexed address bus. FSADDR[13:0] are used for bootstrapping configuration. See Section 4.17. [Bidirectional, 8mA drive output, 5V-tolerant] 9 gm5020 / gm5020-H Data Sheet C5020-DAT-01Q ...
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... W10 FSDATA10 V10 FSDATA9 Y9 FSDATA8 W9 FSDATA7 V9 FSDATA6 V8 FSDATA5 Y7 FSDATA4 W7 FSDATA3 V7 FSDATA2 Y6 FSDATA1 W6 FSDATA0 V6 February 2002 SDRAM data bus. Optionally programmable bits wide. Default is 32 bits wide. [Bidirectional, 8mA drive output, 100KΩ pull-down, 5V-tolerant] 10 gm5020 / gm5020-H Data Sheet C5020-DAT-01Q ...
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... Digital Ground (Periphery and Core Logic) Digital VDD, 2.5VDC (Core Logic. Bypass to DGND, 0.1uF) Digital VDD, 3.3VDC (I/O pins. Bypass to DGND, 0.1uF) Table 9. No Connects Ball # Description No Connect. Leave these pins floating. 11 gm5020 / gm5020-H Data Sheet Bypass to PLLGND (0.1uF) Bypass to AGND (0.1uF) Bypass to AGND (0.1uF) C5020-DAT-01Q ...
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... Recovery Image Digital Capture DVI DVI Rx HDCP Digital YUV Video ITU656 Decoder (8-bits) . Figure 3. gm5020 Functional Block Diagram February 2002 gm5020 / gm5020-H Data Sheet Serial SDRAM Interface Interface Micro- Frame Host processor Store Interface (MCU) Interface RGB Input YUV Frame Rate ...
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... TCLK connection (with Crystal Resonator) The size of C and C are determined from the crystal manufacturer’s specification and the L1 L2 parasitic capacitance of the gm5020 and PCB traces. To avoid start up problems with the internal oscillator, the C parameter specified by the crystal manufacturer should not be exceeded. LOAD C includes well as the parasitic capacitances ...
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... LOAD1 L1 PCB PIN (i.e LOAD2 LOAD1 L2 L1 The following values can be used for the gm5020 9pF SHUNT C ~ 5.3 pF ESD PAD C ~ 1.1 pF PIN C is layout dependent (usually pF) PCB In addition to the above requirement, the crystal should be a parallel resonate cut and the equivalent series resistance must be less than 90 ohms ...
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... A 2.7 kohm resistor from the TCLK pin to ground provides additional bias to keep the clock symmetrical. 2 DVDD_33 TCLK MHz H4 Oscillator XTAL Figure 7. TCLK connection (with Oscillator) February 2002 gm5020 / gm5020-H Data Sheet Vdd 100 K 180 uA TCLK Distribution gm5020 Vdd 100 K 180 uA 15 OSC_OUT OSC_OUT TCLK Distribution ...
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... Genesis Microchip 4.1.2 Synthesized Clocks The gm5020 synthesizes all additional clocks internally: Clock inputs to the DDDS and FCLK PLL (as shown in the figure below) are selected via a host interface register. Note that even when the system is designed without a frame store interface, an internally synthesized frame store clock (FS_CLK) is required to clock data in and out of internal FIFOs. ...
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... Read only status bit. These are read only registers. No effect to the chip will occur if an attempt is made to write to these bits 2. Each clock domain in the gm5020 is internally reset for 64 local clock domain cycles, before returning to normal operation. Software Reset will NOT reset the analog components of the RCLK PLL, FCLK PLL, SDDS, DDDS, DVI, or ADC blocks ...
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... Genesis Microchip gm5020 Supply Voltage Ramp 3.3 Volts Reset Signal 0 Volts Reset held low until after Supply voltage is stable Figure 9. Hardware Reset February 2002 gm5020 / gm5020-H Data Sheet Oscillator Startup time 18 C5020-DAT-01Q ...
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... VSYNC Vertical Sync (Terminate as with HSYNC illustrated in Figure 11) The gm5020 HSync and VSync input pins contain Schmitt trigger with typical hysteresis of 350 mV possible to encounter some combinations of video sources, cable, and PCB layout that will exhibit ringing or glitching at the sync signal edges. In severe cases, the glitching may exceed the internal hysteresis provided and cause “ ...
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... Channel to Channel Matching Effective Number of Bits (ENOB) (*) Guaranteed by design (**) Independent of full scale RGB input The gm5020 ADC has a built in clamp circuit. By inserting series capacitors (10 nF), the DC offset of the video source can be removed. The clamp position and width are programmable. February 2002 RED + ...
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... Digital Composite Sync In general, the gm5020 supports standard implementations of both OR/AND type and XOR type composite sync signals. Sync status information is available through host registers to interpret the signal type and program its support. ...
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... Figure 15. Positive and negative polarity "serration with equalization”-type CSYNC Sync-On-Green (Analog Composite Sync) The gm5020 supports standard implementations of both OR/AND type and XOR type SOG signals. The voltage level of the sync tip during the vertical sync period can range from -0.3V to – ...
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... Genesis Microchip Patented digital clock synthesis technology makes the gm5020 clock circuits resistant to temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock recovery circuit can generate any IPCLK clock frequency within the range of 10MHz to 162MHz. 10 MHz <= SDDS_CLK <= 30 MHz 40 MHz <= Fout < ...
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... Piece-wise linear connected lines. In this case, the resultant curve can be approximated with a number of line segments connected vertix-to-vertix. The firmware would be responsible to select the appropriate line (and therefore the appropriate equation) based on total delay required. Please contact Genesis for line equations if required. February 2002 gm5020 / gm5020-H Data Sheet 24 C5020-DAT-01Q ...
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... The Ultra-Reliable DVI receiver block of the gm5020 is compliant with DVI1.0 single link specifications. Digital Visual Interface (DVI standard that uses Transition Minimized Differential Signaling protocol (TMDS). This block supports an input clock frequency ranging from 20 MHz to 165 MHz. Analog ...
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... Note: This section refers only to the gm5020-H chip. The HDCP system allows for authentication of a video receiver, decryption of encoded video data at the receiver, and renew-ability of that authentication during transmission. The gm5020-H implements circuitry to allow for authentication and decryption of video as specified by the HDCP 1 ...
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... HDCP Digital YUV Video ITU656 Decoder (8-bits) . Figure 19. ITU-R BT656 Block 4.5.1 YCbCr Input Clamping YCbCr input to the gm5020 is always automatically clamped to restrict the input data to ITU-R BT601 levels: Y Bottom clamping: Y Top clamping: CbCr Bottom clamping: CbCr Top clamping: February 2002 ...
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... Figure 20. Image Capture Block The gm5020 Active Window Decoder (AWD) is responsible for identifying “active” or “non- blanking” data to the subsequent blocks in the gm5020. Only active data is processed by the chip. There are several programming methods of the AWD based on the selected input. These are described below ...
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... HSYNC / VSYNC Delay The active input region captured by the gm5020 is specified with respect to internal HSYNC and VSYNC. By default, internal syncs are equivalent to the HSYNC and VSYNC driven in at the selected input port, and forces the captured region to be bounded by HSYNC and VSYNC timing ...
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... Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with respect to HSYNC. VSYNC and HSYNC are generally driven coincidentally, but may arrive at slightly different times to the gm5020 because of different conditioning at the PCB level result, VSYNC may be seen earlier or later, or possibly jitter relative to HSYNC. Because VSYNC is used to reset the line counter and HSYNC is used to increment it, any difference in the relative position of HSYNC and VSYNC is seen on-screen as vertical jitter ...
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... Figure 24. ITU-R BT656 Input February 2002 SAV 1715 1437 1438 1439 1440 1441 1442 1443 Active Video 31 gm5020 / gm5020-H Data Sheet EAV Blanking 1444 Preamble Timing Reference word EAV (End of Active Video) C5020-DAT-01Q ...
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... It is also capable of detecting the field type of interlaced formats. The IFM features a host programmable reset, separate from the regular gm5020 soft reset. The IFM is capable of operating while the rest of the gm5020 is running in power down mode. Horizontal measurements are measured in terms of the selected IFM_CLK (either T_CLK or R_CLK/4) ...
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... EVEN field is indicated (the interpretation of odd and even can be reversed). The window start and end points are selected from a predefined set of values. For ADC interlaced inputs, the gm5020 may be programmed to automatically determine the field type (even or odd) from the VSYNC/HSYNC relative timing. HS ...
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... Genesis Microchip 4.7.2 Input Data Measurement The gm5020 provides a number of pixel measurement functions intended to assist in configuring system parameters such as pixel clock, sample clocks per line, sampling phase, centering the image, or adjusting the contrast and brightness. 4.7.2.1. Input Boundary Detection Since there signal present in the analog source, the data from the ADC must be examined to determine when the active data starts and ends ...
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... Genesis Microchip 4.7.2.3. Image Minimum/Maximum The gm5020 performs measurements on the input data that is used to adjust brightness and contrast. The MINMAX registers return the minimum or maximum Red/Green/Blue pixel values in the programmed active region. In practice, if the active region is reduced in size, they provide a less sensitive alternative to the ADC overflow and underflow flags. ...
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... The gm5020 provides digital adjustment of the captured image data, allowing control over the image black level, contrast, brightness, hue and saturation. Analog RGB Triple ADC Clock Recovery Image Digital Capture DVI DVI Rx HDCP Digital YUV ...
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... The human eye is more sensitive to variations of flesh tones than other colors; for example, the user may not care if the color of grass is modified slightly during image capture and/or display. However, if skin tones are modified by even a small amount unacceptable. The gm5020 features flesh tone adjustment capabilities. This feature is not based on lookup tables, but rather a manipulation of YUV-channel parameters ...
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... Section 4.12.2. Please contact Genesis for appropriate software to determining the LUT entries when implementing this function. RGB Color RGB Data Controls from RealColor TM Block INLUT_BYPASS Figure 31. Input LUT and Dithering February 2002 gm5020 / gm5020-H Data Sheet black Input Input 8:10 LUT RANDOM_EN DITHER_DISABLE 38 contrast Dither FRC/SCALER C5020-DAT-01Q ...
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... XGA 1024 pixels. Shrinking the image prior to frame-rate conversion reduces the bandwidth required in the DRAM interface. Note that horizontal shrink and horizontal zoom (See Section 4.12) cannot be performed simultaneously. Note also that the pre-filter OSD overlay occurs after horizontal shrink has been performed. February 2002 gm5020 / gm5020-H Data Sheet 39 C5020-DAT-01Q ...
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... FSC). 4.10.3 Frame Store Bandwidth Requirements All data coming into and flowing out of the gm5020 frame rate converter must pass through the frame store interface. Therefore, this interface must provide enough bandwidth to support the combined bandwidth demands of the input and display ports. ...
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... SDRAM devices have a power-on sequence that must be performed before they can be reliably accessed. This consists of a pre-charge cycle, 20 refresh cycles, and a MRS cycle. (The MRS – mode register setting – programs the DRAM for burst size, access latency, etc.) The gm5020 automatically performs this sequence. ...
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... Static mesh de-interlacing takes lines from an odd and even field pair and meshes them together, doubling the number of output lines. This technique is often used to de-interlace static graphics inputs. February 2002 gm5020 / gm5020-H Data Sheet Source Width Ignored Lines Scaler Input Width ...
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... Vertical Shrink The gm5020 also provides an arbitrary vertical shrink down to (50 line) of the original image size. Together with the arbitrary horizontal shrink, this allows the gm5020 to capture and display images one VESA standard format larger than the native display resolution. ...
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... Figure 35. Gamma Correction LUT Block After the scaling block, the gm5020 provides 10-bit look up table (LUT) for each input color channel. Although any arbitrary transfer function may be programmed, this LUT is primarily used for two purposes: Gamma correction of the display device and moire cancellation. ...
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... Grey Level Figure 36. Gamma Response Curve The gm5020 Gamma Correction LUT may typically be programmed with an inverse function to compensate for the gamma effect. 4.12.2 Moiré Cancellation The “moire” effect occurs as a result of resampling (scaling) the input image to a different display resolution ...
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... Figure 37. Display Timing and Control Blocks The Display Output Port provides data and control signals that permit the gm5020 to connect to a variety of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit RGB pixels, either single or double pixel wide. All display data and timing signals are synchronous with the DCLK output clock. 4.13.1 Display Clock Generation – ...
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... DDDS will synthesize the correct display clock frequency to satisfy the above relationship. 4.13.2 Display Synchronization The gm5020 supports two display synchronization modes: • Free Run Mode: No synchronization. This mode is used when there is no valid input timing, or for testing purposes. • ...
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... The programmable input Lock Event and display Lock Load parameters represent the mechanism for frame synchronization. The Lock Event represents a chosen pixel location within the input field or frame. When the Lock Event location is reached, the gm5020 Display Timing Generator is reloaded with the Lock Load values. Hence, the display timing is “corrected” or “aligned” to the proper location ...
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... Lock Event location. 4.13.2.3. Manual Synchronization The gm5020 Display Timing Generator (DTG) may be forced to the lock load values by asserting the DFSYNCn pin. This may be thought “manual” lock event. This manual mechanism is separately enabled via a host register bit. This feature is provided by complex configurations such as slaving gm5020 timing to other devices ...
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... DH_ACTIV_WIDTH DCLK (Output) DEN (Output) DARED/BLU/GRN rgb2 rgb3 rgb4 (Output) DBRED/BLU/GRN XXX (Output) 50 gm5020 / gm5020-H Data Sheet DV_VS_END DV_BKGND_START DV_ACTIV_START DV_ACTIV_LNGTH DV_BKGND_END ** DEN is not asserted during vertical blanking * program desired pixels - 1) when in double wide output mode, even pixel start XXX ...
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... The gm5020 has three available bypass capabilities in addition to the standard data flow: 1) Capture-only Mode: In this mode, captured input signals and data are transferred, with a nominal register latency, directly to the display output port. No image processing of any type is performed and the display clock is identical to the input clock. The output port is automatically configured for single-pixel data width in this configuration ...
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... Clock Recovery Image Digital Capture DVI TMDS Rx HDCP Digital YUV Video ITU656 Decoder (8-bits) . Figure 44. Scaler Bypass Mode February 2002 gm5020 / gm5020-H Data Sheet Serial SDRAM Interface Interface Micro- Frame Host processor Store Interface (MCU) Interface RGB Input YUV Frame Rate ...
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... Figure 45. OSD Block The gm5020 OSD controller supports both character-mapped and bitmapped modes. A user programmable palette of 256 true colors (255 colors transparent) is available. In character mapped mode, a maximum of four colors per character are available. In 8-bit bitmapped mode, any pixel can be assigned any one of 256 user-defined true colors. In 4-bit bitmapped mode, any pixel can be assigned any one of 16 user-defined true colors (15 colors plus one transparent) ...
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... Note that when using on-chip programmable fonts, the character map and the font table share the same on-chip RAM. Thus, the size of the character map can be traded off against the number of February 2002 gm5020 / gm5020-H Data Sheet 0 rotated fonts) Address 25: ...
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... Character Attribute Word (Two bit-per-pixel mode) In two bit-per-pixel mode, each character attribute word defines the character index, the background color, three foreground colors, and the blink status for a visible character. February 2002 gm5020 / gm5020-H Data Sheet SDRAM fonts are processed 55 C5020-DAT-01Q ...
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... One Bit Per Pixel On-chip Programmable SRAM Based Fonts The gm5020 OSD controller has SRAM available to store up to 256, one bit per pixel character mapped fonts. Figure 47 shows the font definition for a character in the on chip SRAM font table, using one bit per pixel protocol ...
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... When using 2-bits per pixel SRAM resident fonts, the designer defines each pixel using a 2-bit code. Bit codes “11”, “10”, and “01” are mapped to foreground colors 3, 2 and 1 respectively. Bit February 2002 gm5020 / gm5020-H Data Sheet Font BitMask 0000000000000000 ...
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... Blink frequency and duty cycle is programmable through host registers. When a character is blinking, foreground colors periodically revert to the background color of the character. Blinking frequency is proportional to the display frame rate. February 2002 gm5020 / gm5020-H Data Sheet 58 C5020-DAT-01Q ...
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... Blend percentage level refers the percentage of the output data that is OSD. For example, 0001 yields an output data stream whose blended pixel data is 93.75% OSD and 6.25% underlying image data. This OSD would be only slightly translucent. February 2002 gm5020 / gm5020-H Data Sheet 59 C5020-DAT-01Q ...
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... The OSD data can be merged before or after the scaling engine. Character mapped image would typically be merged after the scaling engine. Merge location is common for all OSD images (bitmapped and character mapped) at any given time. February 2002 gm5020 / gm5020-H Data Sheet 60 C5020-DAT-01Q ...
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... The gm5020 incorporates an embedded microprocessor, or OCM (On-Chip Microprocessor). This processor is intended to simplify the gm5020 system software implementation by providing embedded macro functions such as complex OSD menu configurations (bitmapped or proportional fonts not intended to replace the system microprocessor. Analog RGB Triple ...
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... During hardware reset, the frame store address lines (FSADDR [13:0]) are configured as inputs. On the de-assertion of reset (rising edge of RESETn), the value on the address lines is captured by the gm5020. The designer should install a 10K pull-up resistor to indicate a ‘1’and connect to ground to indicate a ‘0’. The captured values are latched into readable host registers. The value on FSADDR [6:0] specifies the 2-wire host protocol device address ...
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... The bus master drives the SCL clock and either the master or slave may drive the SDA line (open drain). The gm5020 operates as a slave on the interface and the external MCU as the master. The SDA and SCL lines are shared with the 6-wire communication lines HFSn and HCLK respectively, as illustrated below ...
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... These form an instruction byte (described in Table 15), a device register address and/or one or more data bytes. The first byte of each transfer indicates the type of operation to be performed by the gm5020. The table below lists the instruction codes and the type of transfer operation. The content of bytes that follow the instruction byte will vary depending on the instruction chosen ...
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... Increment, the address pointer is automatically incremented after each byte has been sent and written. The transmission data stream for this mode is illustrated below. The highlighted sections of the waveform represent moments when the transmitting device must release the SDA line and wait for an acknowledgement from the gm5020 (the slave receiver). SCL 1 ...
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... The 6-wire interface connection features four bi-directional data lines HDATA[3:0], one clock (HCLK), and one chip select / framing signal (HFSn). Four bits are transferred on each clock edge. The gm5020 operates as a slave on the interface with the external MCU expected to generate HCLK. ...
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... The data transfers using the 6-Wire protocol consist of an instruction byte indicating the type of operation to be performed by the gm5020. Table 15 above lists the instruction codes and the type of transfer operation. The content of bytes that follow the instruction byte will vary depending on the instruction chosen ...
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... OPERATION CODE [5] DON'T CARE HDATA[0] OPERATION CODE [4] REGISTER ADDRESS [8] MASTER MASTER TRANSMIT TRANSMIT Figure 59. 6-Wire Read Operations (0x9x & 0xAx) February 2002 gm5020 / gm5020-H Data Sheet SLAVE SLAVE RECEIVE RECEIVE REGISTER ADDRESS [7] REGISTER ADDRESS [3] REGISTER ADDRESS [6] REGISTER ADDRESS [2] REGISTER ADDRESS [5] REGISTER ADDRESS [1] ...
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... RC integrator to generate a variable DC voltage for a LCD back light inverter. The display HSYNC signal (DHS) or TCLK may be used as the clock for a counter generating this output signal. 4.19.3 Low Power State The gm5020 provides a low power state in which the clocks to selected parts of the chip may be disabled. See Table 17. February 2002 n ...
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... Table 16. Absolute Maximum Ratings (Both gm5020 and gm5020-H) PARAMETER Supply Voltage AVDD_3.3 & DVDD_3.3 & PLLVDD_3.3 Supply Voltage AVDD_2.5 & DVDD_2.5 Input Voltage (5V tolerant inputs) Input Voltage (non 5V tolerant inputs) Electrostatic Discharge Latchup Ambient Operating Temperature Storage Temperature Operating Junction Temp ...
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... INPUTS V 2 GND IL V 2.4 IHC V GND ILC OUTPUTS ** V 2 GND ) 3.45V, V VDD_33 V VDD_33 71 gm5020 / gm5020-H Data Sheet TYP MAX UNITS 3.3 3.45 V 2.5 2.65 V 1.75 2.6 W 1.55 2 440 575 190 80 110 20 30 410 510 115 80 110 ...
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... R_CLK Reference Clock F_CLK Frame Store Clock FRC/non-FRC configuration OCM_CLK On-Chip MCU DCLK Display Clock V DD 90% CLK 10 Clock Duty Cycle C Rise Time = t Figure 60. Clock Reference Levels February 2002 gm5020 / gm5020-H Data Sheet ...
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... Figure 62. Propagation Delay Reference Levels February 2002 V DD GND and the falling setup time ( and the falling hold time ( 1. and the falling (T ) delay times gm5020 / gm5020-H Data Sheet C5020-DAT-01Q ...
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... FSDATA* Minimum Setup (ns) FSDATA* Minimum Hold (ns) FSREAD_TIMING Tap 3 FSDATA* Minimum Setup (ns) FSDATA* Minimum Hold (ns) Note: FSOUTTIMING and FSREADTIMING are controlled by the SYS_TIMING register. February 2002 gm5020 / gm5020-H Data Sheet ITU-R BT656 Input Port Timing Minimum Hold Requirement (ns) 4.0 Tap 0 Tap 1 (default) Min ...
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... HFSn from HCLK Hold HDATA to HCLK Setup HDATA from HCLK Hold Propagation delay from HCLK to HDATA The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) February 2002 gm5020 / gm5020-H Data Sheet Display Timing and DCLK Adjustments Tap 0 Tap 1 (default) Min Max ...
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... Genesis Microchip 6. ORDERING INFORMATION Order Code Application gm5020 SXGA gm5020-H SXGA with HDCP February 2002 gm5020 / gm5020-H Data Sheet Package Temperature Range 292-pin PBGA 292-pin PBGA 76 0-70°C 0-70°C C5020-DAT-01Q ...
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... Genesis Microchip 7. MECHANICAL SPECIFICATIONS Gold plate marks ball Figure 63. gm5020 292-pin PBGA February 2002 gm5020 / gm5020-H Data Sheet Symbol MIN A 2. 26. ...