CX28225-14 Mindspeed Technologies, CX28225-14 Datasheet
CX28225-14
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CX28225-14 Summary of contents
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CX28224/5/9 Inverse Multiplexing for ATM (IMA) Family Data Sheet 28229-DSH-001-D March 2004 ...
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... Ordering Information Manufacturing Part Model Number Number CX28224 CX28224-14 CX28225 CX28225-14 CX28229 CX28229-14 Revision History Revision Level Date A Preliminary July 2001 B Preliminary September 2001 C Preliminary September 2001 D Preliminary April 2002 E Preliminary May 2002 F Preliminary September 2002 A Released January 2003 C Released August 2003 ...
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... JTAG Mindspeed Technologies ™ Distinguishing Features Complete IMA solution in a single package 2 port, CX28224, 17mm BGA 4 port, CX28225, 17mm BGA 8/32 port, CX28229, 17mm BGA Field tested software available Supports ports using external TC PHYs IMA groups Supports the IMA standard requirements ...
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... Supports variable link data rates (64K– 3.072 Mb/s) Internal memory Connects directly to the Mindspeed SARs for inexpensive CPE solutions CX28224 2 ports CX28225 4 ports CX28229 32 ports Memory expandable bytes via external bus independent groups (using external PHYs): Each group can have links. ...
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... Source Loopback (UTOPIA-to-Serial Configuration Only 2-35 2.6 Far-End Line Loopback (Serial Configuration Only 2-36 2.7 Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.8 Reference Designs 2-37 3 IMA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.1 T1/E1 Using Internal Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.1.1 Using IMA_SysClk as the Transmit Clock 3-4 3.1.1.2 Using IMA_RefClk as the Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.2 DSL/T1/E1 Using UTOPIA-to-UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 28229-DSH-001-D Mindspeed Technologies ™ v ...
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... Control Register 7-41 0x10—TXHDR1 (Transmit Cell Header Control Register 7-41 0x11—TXHDR2 (Transmit Cell Header Control Register 7-42 0x12—TXHDR3 (Transmit Cell Header Control Register 7-42 0x13—TXHDR4 (Transmit Cell Header Control Register 7-43 vi Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... Interface Control Register 7-65 0x202—ATMINTFC (ATM-side Interface Control Register 7-65 0x203—OUTSTAT (Output Status Control Register 7-65 0x204—SUMPORT (Summary Port Interrupt Status Register 7-66 0x205—ENSUMPORT (Summary Port Interrupt Control Register 7-66 0x208—PART/VER (Part Number/Version Register 7-67 28229-DSH-001-D Mindspeed Technologies ™ vii ...
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... IMA_TX_GRPn_FIRST_PHY_ADDR (Transmit First PHY Address 7-94 IMA_TX_GRPn_ID (Transmit Group ID 7-95 IMA_TX_GRPn_STAT_CTL (Transmit Group Status and Control 7-96 IMA_TX_GRPn_TIMING_INFO (Transmit Timing Information 7-97 IMA_TX_GRPn_TEST_CTL (Transmit Test Control 7-98 IMA_TX_GRPn_TX_TEST_PATTERN (Transmit Group Tx Test Pattern 7-98 IMA_TX_GRPn_CELL_COUNT_LSB (Transmit Cell Count LSBs 7-99 IMA_TX_GRPn_CELL_COUNT_MSB (Transmit Cell Count MSBs 7-99 viii Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... UTOPIA Interface Timing (ATM Layer 8-11 8.1.4 UTOPIA Interface Timing (PHY Layer 8-15 8.1.5 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.1.6 One-second Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 8.2 Expansion Memory Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.3 Absolute Maximum Ratings 8-21 8.4 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 8.5 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 A IMA Version 1.1 PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.3 Symbols and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.4 Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.5 IMA PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 28229-DSH-001-D Mindspeed Technologies ™ ix ...
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... A.5.1 Global Statement of Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.5.2 Instructions for Completing the PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.5.3 IMA Protocol Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.6 PICS Proforma References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21 B Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 x Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... Interrupt Indication Diagram (TC Block 6-5 Figure 8-1. Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Figure 8-2. Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Figure 8-3. Microprocessor Timing Diagram—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Figure 8-4. MIcroprocessor Timing Diagram—Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Figure 8-5. Microprocessor Timing Diagram—Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Figure 8-6. Microprocessor Timing Diagram—Synchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Figure 8-7. Framer (Line) Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 28229-DSH-001-D Mindspeed Technologies ™ xi ...
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... UTOPIA Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Figure 8-12. UTOPIA Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Figure 8-13. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Figure 8-14. One-second Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Figure 8-15. Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Figure 8-16. CX28224/5/9 Mechanical Drawing (Bottom View 8-23 Figure 8-17. CX28224/5/9 Mechanical Drawing (Top and Side Views 8-24 xii Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... Microprocessor Timing Table—Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Table 8-4. Microprocessor Timing Table—Synchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Table 8-5. Framer (Line) Transmit Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Table 8-6. Framer (Line) Receive Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Table 8-7. UTOPIA Transmit Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Table 8-8. UTOPIA Receive Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Table 8-9. UTOPIA Transmit Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 28229-DSH-001-D Mindspeed Technologies ™ xiii ...
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... Expansion Memory Port Read/Write Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Table 8-14. Absolute Maximum Ratings (General 8-21 Table 8-15. Absolute Maximum Ratings (CX28229/CX28225/CX28224 8-21 Table 8-16. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Table A-1. Basic IMA Protocol (BIP) Definition Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Table A-2 ...
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... Rx Block IMA Engine Tx Block IMA clocks 28229-DSH-001-D IMA Block 1 TC Counters OneSec Micro interface JTAG Mindspeed Technologies ™ TC Block cell processor Line interface 0 cell processor Line interface 1 cell processor Line interface 2 cell processor Line interface 3 cell processor Line interface 4 cell processor ...
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... M values), the bringing up of the IMA group, and the graceful addition/recovery and deletion of links to and from the group. For the CX28229, this function is performed in the host software. The software itself is available from Mindspeed. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... IMA virtual link. It allows for smooth introduction of each link in the group. It also allows graceful handling of error conditions and removal of a link. This function is performed internally by the CX28229 1.544 Mb Mindspeed Technologies ™ Introduction to IMA 4.5 Mb/s 500027_053 - 1 ...
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... Always at least 1 ICP cell per frame ATM ATM ATM ICP ATM IMA control Protocol Cell ICP n IFSN = n Mindspeed Technologies CX28224/5/9 Data Sheet Figure 1-3. It ATM ATM ATM This cell was in the previous frame ATM ...
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... Bit 7 Set to 1 for ICP cell Bits 6–5 Unused and set to 0 Bits 4–0 Logical ID for physical link range (0... 31) Cyclical counter 255 Indicates position of ICP cell within the IMA frame of size M cells. Range: (0... M – 1) Mindspeed Technologies Introduction to IMA Table 1-2 lists format of ™ ...
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... Bits 1–0 11: Reserved IMA Frame Length 00: M=32 01: M=64 10: M=128 11: M=256 Transmit Clock Information Bits 7–6 Unused, set to 00 Bit 5 Transmit Clock Mode (0: ITC mode, 1: CTC mode) Bits 4–0 Tx LID of the timing reference link (TRL)—Range Mindspeed Technologies CX28224/5/9 Data Sheet ™ 28229-DSH-001-D ...
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... Version 1.1 Bit 7 Set to 0 for IMA Filler cell Bits 6–0 Unused and set to 0 Set to 0x6A (as defined in ITU-T I.432) Bits 15-10 Reserved field for future use—default value is all zeros Bits 9-0 CRC-10 as defined in ITU-T Recommendation I.610 Mindspeed Technologies Introduction to IMA ™ ...
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... Chapter 3 and in the ATM standard on IMA. Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... DSL links generally follow the same path and have nearly identical delays. 28229-DSH-001-D Table 1-4 shows the memory requirements for differential delay 68. 128 K 256 K 512 K Mindspeed Technologies ™ Introduction to IMA 110 ms 220 ms 137.5 ms 275 128 K 128 K 256 K ...
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... This function provides a direct interface to retrieve the Subsystem parameters. This function executes a specified IMA diagnostic test. This function provides a direct interface to set the parameters. This function provides a direct interface to retrieve the parameters. Mindspeed Technologies CX28224/5/9 Data Sheet Short Description initialization structure to default CX28224/5/9 Subsystem CX28224/5/9 ...
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... This is an application defined function that disables interrupts from the IMA hardware device. This is an application defined function that enables interrupts from the IMA hardware device. This is an application defined function that accepts asynchronous event CX28224/5/9 messages from the Mindspeed Technologies ™ Introduction to IMA CX28224/5/9 Group CX28224/5/9 Group ...
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... Upon initializing the CX28229TAP, the Failure indications required by the ATM MIB are enabled and the activation and decay times are set at 2.5 and 10 seconds, respectively. 1-12 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... Both ends have accepted the group parameters and are waiting for the LSM to provide active links Blocked The host controller has inhibited the group (probably for maintenance reasons) Operational Fully operational and able to pass data 28229-DSH-001-D Table Chapter 3 and in the ATM standard on IMA. Description Mindspeed Technologies ™ Introduction to IMA 1-6. Again, this will be covered - 1 13 ...
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... Introduction to IMA 1-14 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... CX2822x Hardware Description Three versions of Mindspeed's IMA solution are available: CX28224, CX28225, and the CX28229. All use the same software drivers and are basically pin compatible. Table 2-1 Table 2-1. Available Parts Device Internal memory CX28224 128 Kbytes CX28225 256 Kbytes CX28229 256 Kbytes ...
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... IMA Clocks IMA_SysClk TxTRL[1:0] IMA_RefClk External Memory Interface MemAddr[19:0] MemData[15:0] MemCtrl_CE* MemCtrl_OE* ExtMemSel MemCtrl_WE* MemCtrl_CLK MemCtrl_ADSC Mindspeed Technologies ™ CX28224/5/9 Data Sheet I/O One Second Input/Output I PHY Transmit Cell Available O PHY Transmit Start Of Cell O PHY Transmit Data Bus I PHY Receive Cell Available I ...
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... Configuration information is shown in 28229-DSH-001-D is the pinout diagram for the CX28229 when operating in the UTOPIA-to- UTOPIA-to-UTOPIA configuration is selected by tying the PhyIntFcSel pin low block diagram port IMA solution using the device in the Table 2-2. Mindspeed Technologies ™ CX2822x Hardware Description - 2 3 ...
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... Figure 2-2. IMA Block Diagram Table 2-2. UTOPIA-to-UTOPIA Configuration Information ATMMux [7,6] PhyIntFcSel (ATMINTFC, 0x202) (Pin R4) 01 Low Use of external memory is optional. GENERAL NOTE: 2-4 Description IMA UTOPIA using the PHY Side UTOPIA; Internal TC block and serial ports not used. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... MemData[2] MemData[7] OneSecIO phyURxClk MemData[11] phyURxData[2] phyURxAddr[0] phyURxAddr[3] MemData[6] phyURxData[4] MemData[0] phyURxAddr[1] MemData[10] phyURxData[ Mindspeed Technologies CX2822x Hardware Description atmUTxClk atmUTxData[7] atmUTxData[14] A atmUTxPrty atmUTxData[15] atmUTxEnb* atmUTxData[4] atmUTxData[2] B atmUTxData[6] atmUTxData[3] atmUTxClAv atmUTxData[0] phyUTxEnb[1]* C ExtMemSel ...
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... When asserted high, the device will not respond to input signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*. Additionally, when MCS* is asserted high, the MicroData[7:0] pins are in a high- impedance state but the MicroInt* pin remains operational. Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... When active low, the device needs servicing. It remains active until the pending interrupt is processed by the Interrupt Service Routine. This pin is an open drain output for an external wired OR logic implementation. An external pull-up resistor is required for this pin. Mindspeed Technologies ™ CX2822x Hardware Description Description - ...
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... Differential delay SRAM Data Bus. ATM cells extracted from the Receive data stream are stored in the SRAM for P6 the purpose of differential delay compensation N10 T10 R10 P11 N11 T11 R11 P12 N12 A6 B6 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... This signal is enabled by pulling the ExtMemSel pin high Receive SRAM clock signal. This signal is enabled by pulling the ExtMemSel pin high Receive SRAM address enable (active low) address strobe. This signal is enabled by pulling the ExtMemSel pin high. Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 9 ...
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... O Receive PHY Cell Bus address. The following limitations apply: T7 Device P8 T8 CX28224 R8 CX28225 CX28229 N9 I Cell Available signals for Receive PHY interfaces. phyURxClAv{n] is active when one or more complete cells T16 I/PD can be transferred. To support different PHY devices, separate cell available signals are provided. This allows expansion to 32 points ...
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... Transmit PHY Cell Bus address. The following limitations apply: T13 Device R13 L15 CX28224 K13 CX28225 CX28229 R14 I Cell Available signals for Transmit ATM cells. When phyUTxClAv[n] is active high, the PHY has space available R15 I/PD for one or more complete cells. To support different PHY devices, separate cell available signals are provided ...
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... K14 I/PD When using the PHY UTOPIA mode, this pin is a no- connect. L16 K15 J13 K16 J14 J16 I/PD When using the PHY UTOPIA mode, this pin is a no- connect. J15 H13 H14 H16 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description Chapter 3. 3. 28229-DSH-001-D ...
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... A13 I Parity status signal bit Utopia mode, a parity calculation is performed over atmUTxData[7:0] for each clock cycle of atmUTxClk. Odd parity is used bit Utopia mode, this signal is the parity of atmUTxData[15:0]. This signal is optional. Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 13 ...
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... ATM Utopia addresses 8–15 only. In this mode, atmURxClAv[1] will threestate for addresses 0– Data transfer and output enable for receive ATM cells (active low). Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... This signal is optional Receive ATM Cell Bus address. This address determines the source channel of the Receive ATM cells output from A4 the IMA subsystem and also selects the channel sourcing the atmURxClAv signal Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 15 ...
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... G12 H5 H6 H11 H12 J5 J6 J11 J12 K5 K6 K11 K12 E5 Power supply connections. (3 E10 E11 E12 F10 F11 F12 L10 L11 L12 M10 M11 M12 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... Table 2-3. CX2822x Pin Descriptions (12 of 12) Pin Label Signal Name V GND Ground ss VGG Electrostatic Discharge (ESD) Supply Voltage FOOTNOTE: (1) This bus is enabled by pulling the ExtMemSel pin high. External Memory is disabled on the CX28224 and CX28225 versions of the device. 28229-DSH-001-D No. I/O G7 Ground connections G10 ...
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... Mindspeed reference design available online. Configuration information is shown in Table 2-4. 2-18 illustrates a pinout diagram for the CX28229 when operating in UTOPIA- UTOPIA-to-Serial configuration is selected by tying the PhyIntFcSel pin high block diagram link IMA solution using the device in the Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... IMA Clocks IMA_SysClk TxTRL[1:0] IMA_RefClk External Memory Interface MemAddr[19:0] MemData[15:0] MemCtrl_CE* MemCtrl_OE* ExtMemSel MemCtrl_WE* MemCtrl_Clk MemCtrl_ADSC Mindspeed Technologies ™ CX2822x Hardware Description I/O One Second Input/Output I Transmit Clock O Transmit Data I/O Transmit Data Marker I Transmit Clock O Transmit Data I/O Transmit Data Marker ...
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... Extended Memory IMA Block 1 TC Counters Micro interface JTAG IMA UTOPIA using Internal TC block; UTOPIA-to-Serial mode using 8 internal serial ports. Mindspeed Technologies ™ CX28224/5/9 Data Sheet TC Block cell processor Line interface 0 cell processor Line interface 1 cell processor Line interface 2 cell processor ...
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... SPRxClk[1] MemData[2] SPTxData[5] MemData[7] SPRxSync[1] OneSecIO MemData[11] SPTxClk[0] SPRxData[1] SPRxSync[0] SPTxData[0] SPTxData[4] MemData[6] MemData[0] SPTxData[2] MemData[10] SPRxData[ Mindspeed Technologies CX2822x Hardware Description atmUTxData[7] atmUTxData[14] A atmUTxPrty atmUTxData[15] atmUTxData[4] atmUTxData[2] B atmUTxData[6] atmUTxData[3] phyUTxEnb[1]* atmUTxData[0] C ExtMemSel atmUTxData[1] atmUTxAddr[1] atmUTxAddr[3] ...
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... When asserted high, the device will not respond to input signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*. Additionally, when MCS* is asserted high, the MicroData[7:0] pins are in a high- impedance state but the MicroInt* pin remains operational. Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... When active low, the device needs servicing. It remains active until the pending interrupt is processed by the Interrupt Service Routine. This pin is an open drain output for an external wired OR logic implementation. An external pull-up resistor is required for this pin. Mindspeed Technologies ™ CX2822x Hardware Description Description - ...
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... Receive data stream are stored in the SRAM for P6 the purpose of differential delay compensation. R6 This bus is enabled by pulling the ExtMemSel pin high N10 T10 R10 P11 N11 T11 R11 P12 N12 A6 B6 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... This signal is enabled by pulling the ExtMemSel pin high Receive SRAM clock signal. This signal is enabled by pulling the ExtMemSel pin high Receive SRAM address enable (active low) address strobe. This signal is enabled by pulling the ExtMemSel pin high. Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 25 ...
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... Most of the IMA logic circuits use this clock (or a derivative of it). It can also be used as a T1/E1 reference clock. Refer to Chapter 3. L14 I If Ref_Xclk used as a reference clock, set the frequency as shown Transmit Reference Clocks. A3 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description Chapter 3. 28229-DSH-001-D ...
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... When the PHY serial interface is enabled, this is the receive line clock input Note that Ports 2–7 are no-connects in the CX28224 and K14 I/PD ports 4–7 are no-connects in the CX28225. L16 I/PD K15 I/PD J13 I/PD K16 I/PD J14 I/PD Mindspeed Technologies ™ CX2822x Hardware Description ...
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... When the PHY serial interface is enabled, this is the transmit line data output T13 R13 R7 I When the PHY serial interface is enabled, this is the transmit line clock input. N13 N14 R14 R15 T15 T16 R16 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... A13 I Parity status signal bit Utopia mode, a parity calculation is performed over atmUTxData[7:0] for each clock cycle of atmUTxClk. Odd parity is used bit Utopia mode, this signal is the parity of atmUTxData[15:0]. This signal is optional. Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 29 ...
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... ATM Utopia addresses 8–15 only. In this mode, atmURxClAv[1] will threestate for addresses 0– Data transfer and output enable for Receive ATM cells (active low). Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... Receive ATM Cell Bus address. This address determines the source channel of the Receive ATM cells output from A4 the IMA subsystem and also selects the channel sourcing the atmURxClAv signal. All 5 bits are not required in every B4 application Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 31 ...
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... G12 H5 H6 H11 H12 J5 J6 J11 J12 K5 K6 K11 K12 E5 Power supply connections. (3 E10 E11 E12 F10 F11 F12 L10 L11 L12 M10 M11 M12 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
Page 61
... Table 2-5. CX28229 Pin Descriptions (12 of 12) Pin Label Signal Name V GND Ground ss VGG Electrostatic Discharge (ESD) Supply Voltage FOOTNOTE: (1) This bus is enabled by pulling the ExtMemSel pin high. External Memory is disabled on the CX28224 and CX28225 versions of the device. 28229-DSH-001-D No. I/O G7 Ground connections G10 ...
Page 62
... IMA software drivers are not required. Configuration information is shown IMA Block Disabled TC Counters Micro interface JTAG TC Block Direct; Device used as Stand-alone cell delineator with 8 serial ports; IMA block not used. Mindspeed Technologies CX28224/5/9 Data Sheet inTable 2-6. TC Block cell processor Line interface 0 cell processor Line interface 1 ...
Page 63
... Purpose mode and MicroClk used as the clock to loop back cells result of the automatic mode switch and clock used, the data on the Tx serial lines will be corrupted. ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening Mindspeed Technologies ™ CX2822x Hardware Description UTOPIA Level 2 Interface Host Interface atmUTxClk ...
Page 64
... SPTxClk, SPRxClk, SPTxSync, and SPRxSync must be present for the loopback mode to function properly for a given port. ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening Mindspeed Technologies ™ CX28224/5/9 Data Sheet UTOPIA Level 2 Interface IMA Interface atmUTxClk Transmit ...
Page 65
... Please contact Mindspeed for information on reference designs and schematic examples. 28229-DSH-001-D CX28398 Port 0 Port 1 Port 2 Port 3 IMA Octal T1/E1 Framer Port 4 Port 5 Port 6 Port 7 Mindspeed Technologies ™ CX2822x Hardware Description Figure 2-10 CX28380 LIU 1 TX1 RX1 LIU 2 TX2 RX2 Quad LIU LIU 3 TX3 RX3 ...
Page 66
... CX2822x Hardware Description 2-38 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 67
... IMA frame rate of the received IMA group. Using this option for the Transmit IMA group frame rate results in a 'line timed' configuration. 28229-DSH-001-D Figure 8 kHz) reference clock from which nominal Transmit x Mindspeed Technologies ™ 3-1. While this can appear ...
Page 68
... This block generates a bit rate clock that is phase locked to the PHY side RxClAv signal. It can monitor Loop all 32 ports on the bus. Any port can be selected as the group timing reference. 3-2 shows the details of the CX28229's IMA clock block from Table Description Mindspeed Technologies ™ CX28224/5/9 Data Sheet Figure 1-1. This 3-1: 28229-DSH-001-D ...
Page 69
... CX28224/5/9 Data Sheet Figure 3-1. CX28229 Clock Diagram IMA Engine RX Mux Note 1 28229-DSH-001-D TX Mux Note 1 Mindspeed Technologies ™ IMA Clocks 500027_072 - 3 3 ...
Page 70
... The device is configured using a software driver. The following code is an example of calls to the driver: IMA_LINK_TYPE = IMA_DS1 IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE IMA_DSL_REF_GENERATOR = IMA_INACTIVE IMA_ALT_RX_TRL = IMA_INACTIVE IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#) IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#) 3-4 illustrates T1/E1 with internal serial ports, using IMA_SysClk equal to Mindspeed Technologies ™ CX28224/5/9 Data Sheet 8 kHz) clock x 28229-DSH-001-D ...
Page 71
... Figure 3-2. T1/E1 using Internal Serial ports; IMA_SysClk equals 24x line rate SPRxClk 0 IMA_RefClk NOT USED; tie to ground IMA_SysClk 24 x line rate General Note: 1. SPRxClk 1-7 are identical but not shown for clarity. 28229-DSH-001-D Transition Synchronizer Detector ref /16 /24 Mindspeed Technologies ™ IMA Clocks Note 1 Note 1 500027_073 - 3 5 ...
Page 72
... The device is configured using a software driver. The following code is an example of calls to the driver: IMA_LINK_TYPE = IMA_DS1 IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE IMA_DSL_REF_GENERATOR = IMA_INACTIVE IMA_ALT_RX_TRL = IMA_INACTIVE IMA_GRP_TX_TRL_SRC = IMA_REF_CLK1 (grp#) IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#) 3-6 illustrates T1/E1 with internal serial ports, using IMA_RefClk. There are Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 73
... Figure 3-3. T1/E1 using Internal Serial ports; IMA_RefClk equals line rate Transition SPRxClk 0 Detector IMA_RefClk IMA_SysClk > line rate Transition Detector General Note: 1. SPRxClk 1-7 are identical but not shown for clarity. 28229-DSH-001-D Synchronizer ref ref Synchronizer Mindspeed Technologies ™ IMA Clocks Note 1 Note 1 500027_074 - 3 7 ...
Page 74
... IMA_LINK_TYPE = IMA_VAR_RATE IMA_DSL_REF_CLK_FREQUENCY = 40960000 IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE IMA_DSL_REF_GENERATOR = IMA_ACTIVE IMA_ALT_RX_TRL = IMA_ACTIVE IMA_GRP_LINK_BANDWIDTH = 2304 (grp#) IMA_GRP_CLK_REF_FACTOR = IMA_NO_DIV (grp#) IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#) IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#) 3-8 illustrates the configuration most commonly used with applications that Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 75
... SPRxClk 1-7 are identical but not shown for clarity. 2. NCO - Numerically controlled oscillator; controlled by parameters in Register 416 and 417. 28229-DSH-001-D up/down adjust n*8kHz NCO See Note 2. Synchronizer ref n*8kHz NCO See Note 2. Mindspeed Technologies ™ IMA Clocks Phase Comparitor /424 Note 1 Note 1 500027_075 - 3 9 ...
Page 76
... IMA Clocks 3-10 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 77
... CX28229 IMA engine to address ports on the line side. 28229-DSH-001-D By convention, data being transferred from the PHY to the ATM layer is considered received data, while data from the ATM layer to the PHY is called transmitted data. Mindspeed Technologies ™ Figure 4-1 and described below. - ...
Page 78
... In 16-bit mode, the cell consists of 54 bytes. The first five bytes contain header information. The sixth byte, UDF2, is required to maintain alignment but is not read by the CX2822x. The remaining bytes are used for payload. 4-2 Figure 4-1. CX28224 only supports 8 bit UTOPIA. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 79
... The UTOPIA address should be changed only when the device or port is in the reset state. 28229-DSH-001-D Figure 4-1 illustrates the connections to/from the ATM Layer device. 0x1F can be assigned as a valid port address to enable 32 port bypass. and Section 2.4. It interfaces to the ATM layer as a normal UTOPIA Level Mindspeed Technologies UTOPIA Interfaces ™ ...
Page 80
... IMA UTOPIA using the PHY Side UTOPIA; UTOPIA-to-UTOPIA; TC block/serial ports not used. IMA UTOPIA using Internal TC block; UTOPIA-to-Serial mode; 8 internal serial ports TC only; Device used as Stand-alone cell delineator with 8 serial ports; IMA block not used. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 81
... ATM Layer UTOPIA bus General Note: Only the Transmit side is shown for clarity. The Receive side is identical. 28229-DSH-001-D UTOPIA data/ address bus phyUTxClav_0 phyUTxEnb_0 CX28229 phyUTxClav_1 phyUTxEnb_1 Mindspeed Technologies ™ UTOPIA Interfaces Figure 4-1. This effectively IMA Link Number 1 RS8228 UTOPIA Port 0− RS8228 UTOPIA Port 8− ...
Page 82
... UTOPIA Interfaces 4-6 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 83
... ATM layer. Whether the original header cells or replacement cells are sent is controlled by bits 0–4 in the HDRFIELD (0x09) register. 28229-DSH-001-D When operating in the UTOPIA-to-UTOPIA mode, the ATM Cell processor block is disabled. Mindspeed Technologies ™ ...
Page 84
... Microprocessor Interface Status and Control ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening One Second Interface 8kHzIn TDO TDI Mindspeed Technologies ™ CX28224/5/9 Data Sheet Control Lines UTOPIA Level 2 Interface IMA Transmit atmUTxClk UTOPIA atmUTxClAv 4-cell Level 2 ...
Page 85
... Distributed Sample Scrambler [DSS]) unscrambled. This means that the only repetitive byte patterns in the data stream that meet the cell delineation criteria are valid headers (or just the HEC bytes in DSS). 28229-DSH-001-D 1 Correct HEC Pre-Sync 1 Errored HEC 7 Errored HECs Mindspeed Technologies ™ Transmission Convergence Block Figure 5-2). 6 Correct HECs Sync 500027_006 Figure 5-3 ...
Page 86
... CX28229 to be programmed for special applications. control bits function. 5-4 Cell Delineation in Sync State No Errors Detected (Pass Cell) Apparent Single-bit Error (Correct Error and Pass Cell) Apparent Multi-bit Error (Drop Cell) Mindspeed Technologies ™ CX28224/5/9 Data Sheet No Errors Detected (Pass Cell) Correction Mode 500027_007 ...
Page 87
... ATM cells. GENERAL NOTE: 1. The HEC Error Correction circuit is independent of the DisHECChk control bit. The CX28229 will correct single bit errors even when the DisHECChk is enabled (assuming that the EnHECCor bit is set to 1). 28229-DSH-001-D Description Mindspeed Technologies ™ Transmission Convergence Block - 5 5 ...
Page 88
... Table 5-3. Receive Cell Header Bit Cell Reject Header Match 0 Match 1 Fail 0 Fail 1 Mindspeed Technologies CX28224/5/9 Data Sheet Incoming Bit Result 0 Match 1 Fail 0 Fail 1 Match x Match Result Accept Cell Reject Cell Reject Cell Accept Cell ™ 28229-DSH-001-D ...
Page 89
... If DSS descrambling fails, the CX2822x defaults to unscrambled mode. 28229-DSH-001-D If both SSS and DSS are enabled, SSS overrides DSS scramble the payload, leaving the five + × polynomial to scramble the entire cell, except Mindspeed Technologies ™ Transmission Convergence Block - 5 7 ...
Page 90
... ATM cells from the UTOPIA bus. For the E1 mode, the ATM cells are mapped into time slots 1–15 and 17–31 as described in Recommendation G.804. For the T1 mode, the ATM cells are mapped into time slots 1–24. 5-8 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 91
... Tx Frame Marker SPTxSync Serial Data SPTxData Rx Frame Marker SPRxSync Serial Data SPRxData Clock SPTxClk, SPRxClk Clock Source TS0/1 MSB/F 255 192 TS0/1 MSB/F 255 192 Mindspeed Technologies ™ Transmission Convergence Block CX28229 PORT X LSB 248 185 LSB 248 185 500027_065 - 5 9 ...
Page 92
... T must have a minimum of 1 clock period. 2 For T , the hold time after the rising edge of the clock MSB Octet 1 bit 6 - Octet MSB Octet 1 bit 6 - Octet 1 Mindspeed Technologies CX28224/5/9 Data Sheet 3 500027_064 3 500027_066 ™ 28229-DSH-001-D ...
Page 93
... TxSync indicates the Start of Cell and Rx are asynchronous. 28229-DSH-001-D Tx Serial Data TxData SPTxData TxSync SPTxSync RxSync SPRxSync Rx Serial Data RxData SPRxData Clock SPTxClk TxClk SPRxClk Transparent Cell Transport Mindspeed Technologies ™ Transmission Convergence Block Figure 5-7. This mode CX28229 PORT X 500027_014 - 5 11 ...
Page 94
... Diagram shows default values for TxClkPol and RxClkPol (IOMODE register). 5-12 Tx Serial Data TSER SPTxData SPTxSync +3.3 V SPRxSync Rx Serial Data RSER SPRxData Clock SPTxClk BClk SPRxClk Transparent Cell Transport MSB Mindspeed Technologies CX28224/5/9 Data Sheet Figure 5-8. This CX28229 PORT X 500027_014a ™ 28229-DSH-001-D ...
Page 95
... The PrtLgcRst, bit 6, in the PMODE register (0x04) restarts all functions but leaves the port control registers unaffected. 28229-DSH-001-D The MicroClk is required for both modes. In asynchronous mode, a MicroClk frequency 50MHz, must be present but can be asynchronous to the other microprocessor signals. In synchronous mode, MicroClk is limited to 25MHz. Mindspeed Technologies ™ ...
Page 96
... See Bit 0 of the Mode register (0x200). NOTE: 6-2 When latching is disabled and a counter is wider than one byte, the LSB should be read first to retain the values of the other bytes for a subsequent read. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 97
... EnIntPin (bit 3) in the MODE register (0x202). Figure 6-1 illustrates the registers involved in the interrupt generation process. 28229-DSH-001-D The IMA block does not generate interrupts. illustrates the flow chart of the interrupt generation process and Mindspeed Technologies ™ General Issues Figure 6 ...
Page 98
... Set Individual Interrupt Indication Bit SUMINT No Interrupt Indication Enabled ? Yes Set SUMINT Interrupt Indication Bit SUMPORT No Port Indication Enabled ? Yes Set SUMPORT Interrupt Indication Bit Interrupt No Pin (MInt*) Enabled ? Yes Set Interrupt Pin (MInt*) Mindspeed Technologies ™ CX28224/5/9 Data Sheet Return 500027_015 28229-DSH-001-D ...
Page 99
... PortInt[0] by ENSUMPORT (0x0201) SUMINT (0x0000) Reserved 7 Reserved 6 EnIntPin Reserved 5 Reserved 4 OR OneSecInt 3 (1) ExInt 2 TxCellInt 1 RxCellInt 0 Input to latch Enabled by ENSUMINT (0x0001) Mindspeed Technologies ™ General Issues MInt Input to latch Enabled MODE (0x0202 500027_016 ...
Page 100
... OneSecInt and ExInt are cleared when the register is read. However, the TxCellInt and RxCellInt bits are cleared only when the corresponding Level 1 register is read and cleared. Level 3 bits are cleared when the entire corresponding Level 2 register has been read and cleared. 6-6 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 101
... IMA Control and Status Registers 28229-DSH-001-D Table 7-3 lists the port-level control and status registers. Control bits that do not have a documented function are reserved and must be written to a logical 0. Description Mindspeed Technologies ™ Table 7-1 lists Table 7-2 lists the device-level Port Base Address ...
Page 102
... Header Field Control Register — Transmit Idle Cell Payload Control Register — Error Pattern Control Register — Cell Validation Control Register — UTOPIA Control Register 1 — UTOPIA Control Register 2 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-64 page 7-65 page 7-65 page 7-65 page 7-66 page 7-66 ...
Page 103
... Transmit Cell Interrupt Indication Control Register — Receive Cell Interrupt Indication Control Register (1) Transmit Cell Status Control Register (1) Receive Cell Status Control Register (2) Idle Cell Receive Counter (low byte) Mindspeed Technologies ™ Registers Page Number page 7-41 page 7-41 page 7-42 page 7-42 page 7-43 ...
Page 104
... Non-Matching Cell Counter (high byte) — Reserved, set to a logical 0 — Reserved, set to a logical 0 lists several registers used for CX2822x’s basic functions, including Description lists the control registers used for transmission of traffic. Mindspeed Technologies CX28224/5/9 Data Sheet Page Number page 7-57 page 7-58 page 7-58 page 7-59 ...
Page 105
... Receive Idle Cell Mask Control Register 2 0x26 IDLMSK3 Receive Idle Cell Mask Control Register 3 0x27 IDLMSK4 Receive Idle Cell Mask Control Register 4 28229-DSH-001-D Description lists the control registers used for reception of traffic. Description Mindspeed Technologies Registers Page Number page 7-37 page 7-38 page 7-38 page 7-39 page 7-41 page 7-42 page 7-42 ...
Page 106
... UTOPIA operations. Description lists interrupt enables, interrupt indications, and status information. Description lists the CX2822x’s counters. When the counters fill, they saturate and do Description Mindspeed Technologies CX28224/5/9 Data Sheet Page Number page 7-40 page 7-40 Page ...
Page 107
... ATM Utopia Control Diff. Delay Control Address Diff. Delay Control Data DSL Clock Generator Control Address DSL Clock Generator Control Data Receive Translation Table Address Receive Translation Table Internal Channel Transmit Translation Table Address Mindspeed Technologies ™ Registers Page Number page 7-61 page 7-62 page 7-63 ...
Page 108
... IMA_GRP_13TO16_SEM 7-8 Description (Continued) Transmit Translation Table Internal Channel Link Table Control Groups 1–4 Table Control Groups 5–8 Table Control Groups 9–12 Table Control Groups 13–16 Table Control Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-86 page 7-109 page 7-88 page 7-89 page 7-90 ...
Page 109
... Tx GRP 3 Tx Test Pattern Tx GRP 4 Rx Test Pattern Tx GRP 4 Control Tx GRP 4 First Link Address Tx GRP 4 Tx Group ID Tx GRP 4 Status / Control Tx GRP 4 Timing Control Tx GRP 4 Test Control Tx GRP 4 Tx Test Pattern Mindspeed Technologies ™ Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 ...
Page 110
... Group 2 Receive Cell Count LSBs Group 2 Receive Cell Count MSBs Group 3 Receive Cell Count LSBs Group 3 Receive Cell Count MSBs Group 4 Receive Cell Count LSBs Group 4 Receive Cell Count MSBs Loss of PhyURxSOC Detector Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 111
... Rx Link 4 Status Rx Link 5 Status Rx Link 6 Status Rx Link 7 Status Rx Link 0 Defects Rx Link 1 Defects Rx Link 2 Defects Rx Link 3 Defects Rx Link 4 Defects Rx Link 5 Defects Rx Link 6 Defects Rx Link 7 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 112
... Rx Link 1 Captured GRP ID Rx Link 2 Captured GRP ID Rx Link 3 Captured GRP ID Rx Link 4 Captured GRP ID Rx Link 5 Captured GRP ID Rx Link 6 Captured GRP ID Rx Link 7 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 113
... Rx GRP 2 Rx Group ID Rx GRP 3 Configuration Rx GRP 3 Control Rx GRP 3 First Link Address Rx GRP 3 Rx Group ID Rx GRP 4 Configuration Rx GRP 4 Control Rx GRP 4 First Link Address Rx GRP 4 Rx Group ID Mindspeed Technologies ™ Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 ...
Page 114
... Rx GRP 3 Tx Test Pattern Rx GRP 4 Rx Test Pattern Rx GRP 4 SCCI Rx GRP 4 Rx Group ID Rx GRP 4 Status / Control Rx GRP 4 Timing Control Rx GRP 4 Test Control Rx GRP 4 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 115
... Tx GRP 7 Tx Test Pattern Tx GRP 8 Rx Test Pattern Tx GRP 8 Control Tx GRP 8 First Link Address Tx GRP 8 Tx Group ID Tx GRP 8 Status / Control Tx GRP 8 Timing Control Tx GRP 8 Test Control Tx GRP 8 Tx Test Pattern Mindspeed Technologies ™ Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 ...
Page 116
... Group 6 Receive Cell Count LSBs Group 6 Receive Cell Count MSBs Group 7 Receive Cell Count LSBs Group 7 Receive Cell Count MSBs Group 8 Receive Cell Count LSBs Group 8 Receive Cell Count MSBs Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 117
... Rx Link 12 Status Rx Link 13 Status Rx Link 14 Status Rx Link 15 Status Rx Link 8 Defects Rx Link 9 Defects Rx Link 10 Defects Rx Link 11 Defects Rx Link 12 Defects Rx Link 13 Defects Rx Link 14 Defects Rx Link 15 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 118
... Rx Link 9 Captured GRP ID Rx Link 10 Captured GRP ID Rx Link 11 Captured GRP ID Rx Link 12 Captured GRP ID Rx Link 13 Captured GRP ID Rx Link 14 Captured GRP ID Rx Link 15 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 119
... Rx GRP 6 Rx Group ID Rx GRP 7 Configuration Rx GRP 7 Control Rx GRP 7 First Link Address Rx GRP 7 Rx Group ID Rx GRP 8 Configuration Rx GRP 8 Control Rx GRP 8 First Link Address Rx GRP 8 Rx Group ID Mindspeed Technologies ™ Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 ...
Page 120
... Rx GRP 7 Tx Test Pattern Rx GRP 8 Rx Test Pattern Rx GRP 8 SCCI Rx GRP 8 Rx Group ID Rx GRP 8 Status / Control Rx GRP 8 Timing Control Rx GRP 8 Test Control Rx GRP 8 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 121
... Tx GRP 11 Tx Test Pattern Tx GRP 12 Rx Test Pattern Tx GRP 12 Control Tx GRP 12 First Link Address Tx GRP 12 Tx Group ID Tx GRP 12 Status / Control Tx GRP 12 Timing Control Tx GRP 12 Test Control Tx GRP 12 Tx Test Pattern Mindspeed Technologies Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 page 7-96 ...
Page 122
... Group 10 Receive Cell Count LSBs Group 10 Receive Cell Count MSBs Group 11 Receive Cell Count LSBs Group 11 Receive Cell Count MSBs Group 12 Receive Cell Count LSBs Group 12 Receive Cell Count MSBs Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 123
... Rx Link 20 Status Rx Link 21 Status Rx Link 22 Status Rx Link 23 Status Rx Link 16 Defects Rx Link 17 Defects Rx Link 18 Defects Rx Link 19 Defects Rx Link 20 Defects Rx Link 21 Defects Rx Link 22 Defects Rx Link 23 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 124
... Rx Link 17 Captured GRP ID Rx Link 18 Captured GRP ID Rx Link 19 Captured GRP ID Rx Link 20 Captured GRP ID Rx Link 21 Captured GRP ID Rx Link 22 Captured GRP ID Rx Link 23 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 125
... Rx GRP 10 Rx Group ID Rx GRP 11 Configuration Rx GRP 11 Control Rx GRP 11 First Link Address Rx GRP 11 Rx Group ID Rx GRP 12 Configuration Rx GRP 12 Control Rx GRP 12 First Link Address Rx GRP 12 Rx Group ID Mindspeed Technologies Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 page 7-101 ...
Page 126
... Rx GRP 11 Tx Test Pattern Rx GRP 12 Rx Test Pattern Rx GRP 12 SCCI Rx GRP 12 Rx Group ID Rx GRP 12 Status / Control Rx GRP 12 Timing Control Rx GRP 12 Test Control Rx GRP 12 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 127
... Tx GRP 15 Tx Test Pattern Tx GRP 16 Rx Test Pattern Tx GRP 16 Control Tx GRP 16 First Link Address Tx GRP 16 Tx Group ID Tx GRP 16 Status / Control Tx GRP 16 Timing Control Tx GRP 16 Test Control Tx GRP 16 Tx Test Pattern Mindspeed Technologies Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 page 7-96 ...
Page 128
... Group 14 Receive Cell Count LSBs Group 14 Receive Cell Count MSBs Group 15 Receive Cell Count LSBs Group 15 Receive Cell Count MSBs Group 16 Receive Cell Count LSBs Group 16 Receive Cell Count MSBs Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 129
... Rx Link 28 Status Rx Link 29 Status Rx Link 30 Status Rx Link 31 Status Rx Link 24 Defects Rx Link 25 Defects Rx Link 26 Defects Rx Link 27 Defects Rx Link 28 Defects Rx Link 29 Defects Rx Link 30 Defects Rx Link 31 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 130
... Rx Link 25 Captured GRP ID Rx Link 26 Captured GRP ID Rx Link 27 Captured GRP ID Rx Link 28 Captured GRP ID Rx Link 29 Captured GRP ID Rx Link 30 Captured GRP ID Rx Link 31 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 131
... Rx GRP 14 Rx Group ID Rx GRP 15 Configuration Rx GRP 15 Control Rx GRP 15 First Link Address Rx GRP 15 Rx Group ID Rx GRP 16 Configuration Rx GRP 16 Control Rx GRP 16 First Link Address Rx GRP 16 Rx Group ID Mindspeed Technologies Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 page 7-101 ...
Page 132
... Rx GRP 15 Tx Test Pattern Rx GRP 16 Rx Test Pattern Rx GRP 16 SCCI Rx GRP 16 Rx Group ID Rx GRP 16 Status / Control Rx GRP 16 Timing Control Rx GRP 16 Test Control Rx GRP 16 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 133
... TxCellInt register (0x2C). When a logical 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a summary interrupt and signifies that an interrupt indication occurred in the RxCellInt register (0x2D). Mindspeed Technologies ™ Registers - 7 ...
Page 134
... When written to a logical 1, this bit enables the receive cell interrupts located in the RxCellInt register (0x2D). These interrupts can appear on the MicroInt* pin (pin T1), provided that EnPortInt in the ENSUMPORT register (0x0201) is enabled for this port and EnIntPin (bit 3) in the MODE register (0x0202) is enabled. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 135
... Purpose In General Purpose Mode, the SPRxSync and SPTxSync pins are ignored. (However, good design practice would have them tied high.) Mindspeed Technologies ™ Registers 110—DSL Mode 111—Power Down - 7 ...
Page 136
... This bit determines the Transmitter Clock Input Polarity. When written to a logical 1, the active edge on the SPTxClk input is the falling edge. When written to a logical 0, the active edge is the rising edge. Reserved, set to 0. Reserved, set to 0. Reserved, set to 0. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 137
... When written to a logical 1, this bit enables the Transmit DSS Scrambler. When written to a logical 0, the Transmit DSS Scrambler is disabled. When written to a logical 1, this bit enables the Receive DSS Scrambler. When written to a logical 0, the Receive DSS Scrambler is disabled. Mindspeed Technologies ™ Registers - ...
Page 138
... When written to a logical 1, this bit inserts a Cell Loss Priority (CLP) bit in the outgoing header from the TXHDR registers. When written to a logical 0, the CLP field is not changed prior to transmission. Description These bits hold the Transmit Idle Cell Payload values for outgoing idle cells. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 139
... When written to a logical 1, this bit disables Loss of Cell Delineation. When disabled, cells are passed even if cell delineation has not been found. When written to a logical 0, cells are passed only while cell alignment has been achieved. See Table 5-1. Mindspeed Technologies ™ Registers Table 5-1. ...
Page 140
... These bits are the Multi-PHY Device Address. Each CX2822x port should have a unique address. These bits correspond to the URxAddr and UTxAddr pins. When the pin matches the bit values, the port is accessed. This port ignores any transactions meant for another port or PHY device. Mindspeed Technologies ™ CX28224/5/9 Data Sheet Default ...
Page 141
... These bits hold the Transmit Header values for Octet 1 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). GFC/VPI bits (for UNI they are GFC bits, for NNI they are VPI bits) VPI bits Mindspeed Technologies ™ Registers - 7 ...
Page 142
... HDRFIELD register (0x09). VPI bits VCI bits Description These bits hold the Transmit Header values for Octet 3 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). VCI bits Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 143
... Cell Loss Priority bit Description These bits hold the Transmit Idle Cell Header values for Octet 1 of the outgoing cell. GFC/VPI bits (for UNI they are GFC bits, for NNI the are VPI bits) VPI bits Mindspeed Technologies ™ Registers - 7 43 ...
Page 144
... These bits hold the Transmit Idle Cell Header values for Octet 2 of the outgoing cell. VPI bits VCI bits Description These bits hold the Transmit Idle Cell Header values for Octet 3 of the outgoing cell. VCI bits Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 145
... These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell. VCI bits Payload-type bits Cell Loss Priority bit Description These bits hold the Receive Header values for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 45 ...
Page 146
... RxHdr3[ RxHdr3[ RxHdr3[0] 7-46 Description These bits hold the Receive Header values for Octet 2 of the incoming cell. Description These bits hold the Receive Header values for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 147
... RxMsk1[ RxMsk1[ RxMsk1[ RxMsk1[0] 28229-DSH-001-D Description These bits hold the Receive Header values for Octet 4 of the incoming cell. Description These bits hold the Receive Header Mask for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 47 ...
Page 148
... RxMsk3[ RxMsk3[ RxMsk3[0] 7-48 Description These bits hold the Receive Header Mask for Octet 2 of the incoming cell. Description These bits hold the Receive Header Mask for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 149
... RxIdl1[ RxIdl1[ RxIdl1[0] 28229-DSH-001-D Description These bits hold the Receive Header Mask for Octet 4 of the incoming cell. Description These bits hold the Receive Idle cell header for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 49 ...
Page 150
... RxIdl3[ RxIdl3[0] 7-50 Description These bits hold the Receive Idle cell header for Octet 2 of the incoming cell. Description These bits hold the Receive Idle cell header for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 151
... IdlMsk1[ IdlMsk1[0] 28229-DSH-001-D Description These bits hold the Receive Idle cell header for Octet 4 of the incoming cell. Description These bits hold the Receive Idle cell header mask for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 51 ...
Page 152
... IdlMsk3[0] 7-52 Description These bits hold the Receive Idle cell header mask for Octet 2 of the incoming cell. Description These bits hold the Receive Idle cell header mask for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 153
... When written to a logical 1, this bit enables the Receive FIFO Overflow Interrupt. When written to a logical 1, this bit enables the Cell Sent Interrupt. Reserved for factory test, ignore. Reserved, set to a logical 0. Reserved, set to a logical 0. Mindspeed Technologies ™ Registers - 7 53 ...
Page 154
... When a logical 1 is read, this bit indicates that a Receive FIFO Overflow occurred. When a logical 1 is read, this bit indicates that a cell has been sent. Reserved for factory test, ignore. Reserved, set to a logical 0. Reserved, write to a logical 0. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 155
... When a logical 1 is read, this bit indicates that an Idle Cell has been received. When a logical 1 is read, this bit indicates that a Non-matching Cell has been received. When a logic 1 is read, this bit indicates that a Non-zero GFC has been received. Mindspeed Technologies ™ Registers - ...
Page 156
... When a logical 1 is read, this bit indicates that a cell has been rejected by the cell screening function. When a logical 1 is read, this bit indicates that a cell with a Non-zero GFC field in the header was received. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 157
... Received cell counter bit 0 (LSB). Description Received cell counter bit 15. Received cell counter bit 14. Received cell counter bit 13. Received cell counter bit 12. Received cell counter bit 11. Received cell counter bit 10. Received cell counter bit 9. Received cell counter bit 8. Mindspeed Technologies ™ Registers - 7 57 ...
Page 158
... LOCD Event counter bit 7 (MSB). LOCD Event counter bit 6. LOCD Event counter bit 5. LOCD Event counter bit 4. LOCD Event counter bit 3. LOCD Event counter bit 2. LOCD Event counter bit 1. LOCD Event counter bit 0 (LSB). Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 159
... Transmitted cell counter bit 0 (LSB). Description Transmitted cell counter bit 15. Transmitted cell counter bit 14. Transmitted cell counter bit 13. Transmitted cell counter bit 12. Transmitted cell counter bit 11. Transmitted cell counter bit 10. Transmitted cell counter bit 9. Transmitted cell counter bit 8. Mindspeed Technologies ™ Registers - 7 59 ...
Page 160
... Corrected HEC Error counter bit 6. Corrected HEC Error counter bit 5. Corrected HEC Error counter bit 4. Corrected HEC Error counter bit 3. Corrected HEC Error counter bit 2. Corrected HEC Error counter bit 1. Corrected HEC Error counter bit 0 (LSB). Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 161
... Received cell counter bit 0 (LSB). Description Received cell counter bit 15. Received cell counter bit 14. Received cell counter bit 13. Received cell counter bit 12. Received cell counter bit 11. Received cell counter bit 10. Received cell counter bit 9. Received cell counter bit 8. Mindspeed Technologies ™ Registers - 7 61 ...
Page 162
... Uncorrected HEC Error counter bit 6. Uncorrected HEC Error counter bit 5. Uncorrected HEC Error counter bit 4. Uncorrected HEC Error counter bit 3. Uncorrected HEC Error counter bit 2. Uncorrected HEC Error counter bit 1. Uncorrected HEC Error counter bit 0 (LSB). Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 163
... Non-matching cell counter bit 0 (LSB). Description Non-matching cell counter bit 15 (MSB). Non-matching cell counter bit 14. Non-matching cell counter bit 13. Non-matching cell counter bit 12. Non-matching cell counter bit 11. Non-matching cell counter bit 10. Non-matching cell counter bit 9. Non-matching cell counter bit 8. Mindspeed Technologies ™ Registers - 7 63 ...
Page 164
... The event occurs after the device has counted 8000 periods KHz clock. When set to 0, the OneSecIO pin is configured as an input. The one-second event must be genetared externally, by pulsing the OneSecIO pin for low-high-low. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 165
... When the ATM UTOPIA interface to TC block is enabled, (ATMmux[1:0] = "10"), this bit controls the bus width of the TC ATM-side UTOPIA interface. Reserved, set to zero. Reserved, set to zero. Reserved, set to zero. Description Reserved, set to zero. The value written into these bits will be asserted on the StatOut[1:0] output pins. Mindspeed Technologies ™ Registers - 7 65 ...
Page 166
... When set, this bit enables PortInt[3] to appear on the MicroInt* output. When set, this bit enables PortInt[2] to appear on the MicroInt* output. When set, this bit enables PortInt[1] to appear on the MicroInt* output. When set, this bit enables PortInt[0] to appear on the MicroInt* output. Mindspeed Technologies CX28224/5/9 Data Sheet Description Description ™ ...
Page 167
... Bit Default Name 7–4 pppp PartNum[3:0] 3–0 0001 Version[3:0] 28229-DSH-001-D Description Part number controlled by bondout: IMA2 – 0100 IMA4 – 0101 IMA8/32 – 1001 Version number of the device. 0001—Version -11 0010—Version -12 0011—Version -13 0100—Version -14 Mindspeed Technologies ™ Registers - 7 67 ...
Page 168
... Version Code II 3–0 Version Code III 7-68 Description 0x0 = CX28224, 2 ports 2 IMA groups 0x2 = CX28225, 4 ports 4 IMA groups 0x8 = CX28229, 32 ports 16 IMA groups 1 = Internal memory present 0x4 = CX2822x family major revision level Description 4 bit code: 0x2 = CX2822x-13 and earlier 0x3 = CX2822x-14 ...
Page 169
... This field has different ranges depending on Product type: CX28224: Unused, Set to 0 CX28225: Unused, Set to 0 CX28229: Range: 0–7 Description This bit is the current state of the signal ATMUTxAddr[4]. This bit is the current state of the signal ATMURxAddr[4]. ...
Page 170
... This field contains the least significant bits of the memory test address for the selected memory component. Range: 0x00–0xFF Description This field contains the middle significant bits of the memory test address for the selected memory component. Range: 0x00–0xFF Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 171
... This field contains the most significant bit of the SRAM write counter for the diagnostic link (selected using the field below). This field contains the PHY Cell Bus Address of the port for which a diagnostic measurement performed. Range: 0x00–0x1F Mindspeed Technologies ™ Registers - ...
Page 172
... All others (Range: 0x00–0xFF) Delay Window = 0 (see register 0x415): Value = Cell_count >> 1 Delay Window = 1–3 (see register 0x415): Value = Cell_count Delay Window = 4 (see register 0x415): Value = Cell_count >> 2 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 173
... Unexpected IMA Cell Offset condition of the ICP-INV anomaly was active sometime since the last time this register was read 0 = Unexpected IMA Cell Offset condition was inactive 1 = ICP-MIS anomaly was active sometime since the last time this register was read 0 = ICP-MIS defect was inactive Mindspeed Technologies ™ Registers - 7 ...
Page 174
... Exclusive OR of address bits from previous IMA core access. The number of bits in the exclusive OR operation is 10. Description An 8 bit register that can be written and read by the processor. The register is not used within the IMA Block. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 175
... Set the Clock Divisor for an IMA group Reserved. Set to 0. Reserved. Set to 0. For Multiplexer Type = 0, Multiplexer Type = 1, and Multiplexer Type = 3: CX28224: 0–1: IMA Group 1–2 CX28225: 0–3: IMA Group 1–4 CX28229: 0–0xF: IMA Group 1–16 For Multiplexer Type = 2: 0–1: Tx_TRL[0]–Tx_TRL[1] output Mindspeed Technologies ™ ...
Page 176
... Use IMA_SysClk/24 or DSL generator output as source (see register 0x416) 0x21: Use IMA_RefClk as source For Multiplexer Type 2 0x00–0x1F: Select timing from a Receive Port (see register 0x416) CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 0x20: Use IMA_SysClk/24 0x21: Use IMA_RefClk as source 0x22: Use 8 kHz as source For Multiplexer Type 3 Reserved ...
Page 177
... The Gamma Value is the number of consecutive valid ICP cells needed for the link to enter the IMA Sync state. 28229-DSH-001-D Description Reserved. Set α α β β β β β γ γ γ γ γ Mindspeed Technologies ™ Registers - 7 77 ...
Page 178
... Reserved. Set Set Delay Threshold for an IMA group 1 = Set Delay Window for an IMA group Reserved. Set to 0. Reserved. Set to 0. CX28224: 0–1: IMA Group 1–2 CX28225: 0–3: IMA Group 1–4 CX28229: 0–0xF: IMA Group 1–16 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 179
... Mindspeed Technologies ™ Registers - ...
Page 180
... Reserved. Set to 0. For Control Type = Receive IMA Group 1 = Transmit IMA Group CX28224: 0–1: IMA Group 1–2 CX28225: 0–3: IMA Group 1–4 CX28229: 0–0xF: IMA Group 1–16 For Control Type = 6, 7 CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Mindspeed Technologies ™ ...
Page 181
... IMA group. The contents of this register are multiplied by 2048kbps in order to obtain the bandwidth. For Control Type = 6 This register contains the 8 lsbs of the payload bandwidth for the specific port of the Rx Timing clock synthesizer. The contents of this register are multiplied by 8kbps in order to obtain the bandwidth. Mindspeed Technologies ™ Registers - 7 81 ...
Page 182
... Description (Continued) For Control Type = 7 Reserved. Set to 0. This register contains the msb of the payload bandwidth for the specific port of the Rx Timing clock synthesizer. The contents of this register are multiplied by 2048kbps in order to obtain the bandwidth. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 183
... Range 0x00–0x1F: Bypass Receive Port CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 Mindspeed Technologies ™ Registers - ...
Page 184
... CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 0x30 All devices: ATM address is not assigned to this device For Translation Type = 1 ...
Page 185
... Range 0x00–0x1F: Bypass Transmit Port CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 Mindspeed Technologies ™ Registers - ...
Page 186
... CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 0x30 All devices: ATM address is not assigned to this device For Translation Type = 1 ...
Page 187
... The read operation will clear the internal state. Reserved. Set to 0. Reserved. Set to 0. This field contains the PHY Cell Bus Address of the SOC being examined CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Mindspeed Technologies ™ Registers ...
Page 188
... CX28224) addresses 0x4D4–0x4D7 addresses 0x4D0–0x4D3 addresses 0x438–0x43F (Not defined for CX28224) addresses 0x430–0x437 (Not defined for CX28224) addresses 0x428–0x42F addresses 0x420–0x427 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
Page 189
... CX28224 and CX28225) addresses 0x538–0x53F (Not defined for CX28224 and CX28225) addresses 0x530–0x537 (Not defined for CX28224 and CX28225) addresses 0x528–0x52F (Not defined for CX28224 and CX28225) addresses 0x520–0x527 (Not defined for CX28224 and CX28225) Mindspeed Technologies ™ ...
Page 190
... CX28224 and CX28225) addresses 0x638–0x63F (Not defined for CX28224 and CX28225) addresses 0x630–0x637 (Not defined for CX28224 and CX28225) addresses 0x628–0x62F (Not defined for CX28224 and CX28225) addresses 0x620–0x627 (Not defined for CX28224 and CX28225) Mindspeed Technologies ™ ...
Page 191
... CX28224 and CX28225) addresses 0x738–0x73F (Not defined for CX28224 and CX28225) addresses 0x730–0x737 (Not defined for CX28224 and CX28225) addresses 0x728–0x72F (Not defined for CX28224 and CX28225) addresses 0x720–0x727 (Not defined for CX28224 and CX28225) Mindspeed Technologies ™ ...
Page 192
... This register contains the value of the Rx Test Pattern field for the transmitted ICP cells. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x420 0x428 0x430 0x438 0x520 0x528 0x530 0x538 0x620 0x628 0x630 0x638 0x720 0x728 0x730 0x738 CX28224 CX28225 Bit Default Name 7–0 0x00 Rx Test Pattern 7-92 n=6 n=7 ...
Page 193
... This register, in conjunction with the IMA_TX_GRPn_FIRST_PHY_ADDR register, controls the operation of the Transmit IMA group. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x421 0x429 0x431 0x439 0x521 0x529 0x531 0x539 0x621 0x629 0x631 0x639 0x721 0x729 0x731 0x739 CX28224 CX28225 Bit Default Name 7 0 Group Enable Timeout Expired 5 — ...
Page 194
... Reserved. Set to 0. Reserved. Set to 0. IMA OAM Label value 1 = IMA v1 IMA v1.0 This field contains the PHY port address of the Transmit link with the lowest LID in the group. CX28224: Range: 0–1 CX28225: Range: 0–3 CX28229: Range: 0–0x1F Mindspeed Technologies ™ CX28224/5/9 Data Sheet n=11 n=12 n=13 ...
Page 195
... This register contains the value of the IMA Group ID field for the transmitted ICP cells. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x423 0x42B 0x433 0x43B 0x523 0x52B 0x533 0x53B 0x623 0x62B 0x633 0x63B 0x723 0x72B 0x733 0x73B CX28224 CX28225 Bit Default Name 7–0 0x00 Tx Group ID 28229-DSH-001-D n=6 n=7 ...
Page 196
... This register contains the value of the Group Status and Control field for the transmitted ICP cells. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x424 0x42C 0x434 0x43C 0x524 0x52C 0x534 0x53C 0x624 0x62C 0x634 0x63C 0x724 0x72C 0x734 0x73C CX28224 CX28225 Bit Default Name 7–4 0x00 Group State 3–2 0 Group Symmetry 1– ...
Page 197
... This register contains the value of the Transmit Timing Information field for the transmitted ICP cells. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x425 0x42D 0x435 0x43D 0x525 0x52D 0x535 0x53D 0x625 0x62D 0x635 0x63D 0x725 0x72D 0x735 0x73D CX28224 CX28225 Bit Default Name ...
Page 198
... This register contains the value of the Tx Test Pattern field for the transmitted ICP cells. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x427 0x42F 0x437 0x43F 0x527 0x52F 0x537 0x53F 0x627 0x62F 0x637 0x63F 0x727 0x72F 0x737 0x73F CX28224 CX28225 Bit Default Name 7–0 0x0 Tx Test Pattern 7-98 n=6 n=7 ...
Page 199
... Transmit links within the group. The register is read only. Status clears upon read. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x441 0x443 0x445 0x447 0x541 0x543 0x545 0x547 0x641 0x643 0x645 0x647 0x741 0x743 0x745 0x747 CX28224 CX28225 Bit Default Name 7-0 0 Transmit Cell Count MSBs 28229-DSH-001-D n=6 n=7 ...
Page 200
... Receive links within the group. The register is read only. Status clears upon read. Group 1–16 Address n=1 n=2 n=3 n=4 n=5 0x451 0x453 0x455 0x457 0x551 0x553 0x555 0x557 0x651 0x653 0x655 0x657 0x751 0x753 0x755 0x757 CX28224 CX28225 Bit Default Name 7-0 0 Receive Cell Count MSBs 7-100 n=6 n=7 ...