CH7304A-T Chrontel, CH7304A-T Datasheet
CH7304A-T
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CH7304A-T Summary of contents
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... Chrontel CH7304 Single LVDS Transmitter Features • Single LVDS transmitter • Supports pixel rate up to 100M pixels/sec • Supports up to SXGA resolution (1280 x 1024) • LVDS low jitter PLL • LVDS 18-bit output • 2D dither engine • Panel protection and power down sequencing • ...
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... CHRONTEL 1.0 Pin Assignment__________________________________________________________________________ 3 1.1 Pin Diagram __________________________________________________________________________ 3 1.2 Pin Description ________________________________________________________________________ 4 2.0 Functional Description ____________________________________________________________________ 6 2.1 Input Data Formats _____________________________________________________________________ 6 2.2 LVDS-Out ___________________________________________________________________________ 9 2.3 Power Down _________________________________________________________________________ 12 3.0 Register Control ________________________________________________________________________ 13 3.1 Control Registers Index ________________________________________________________________ 13 3.2 Control Registers Description____________________________________________________________ 14 3.3 Control Registers Description____________________________________________________________ 15 3.4 Recommended Settings_________________________________________________________________ 25 4.0 Electrical Specifications __________________________________________________________________ 26 4.1 Absolute Maximum Ratings _____________________________________________________________ 26 4 ...
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... ENAVDD LVDD LGND LVDD LGND 201-0000-053 Rev. 1.31, 6/14/2006 Chrontel CH7304 Figure 2: 64 Pin LQFP Package (Top View) CH7304 48 VDDV 47 RESET VREF DVDD 41 SPD 40 SPC 39 CONFIG 38 LPLL_VDD 37 LPLL_CAP 36 LPLL_GND 35 ...
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... CHRONTEL 1.2 Pin Description Table 1: Pin Description Pin # # of Pins Type Symbol 1 1 Out ENABLK 2 1 Out ENAVDD 3,4,6,7,9,10 12,13,15,16 20 Out LLC, LLC* 17,23,26,29 4 Out LDC[3:0] 18,24,27,30 4 Out LDC[3:0 VSWING 33 1 Out Analog LPLL_CAP 39 1 In/Out CONFIG SPC 41 1 In/Out ...
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... CHRONTEL Table 1: Pin Description (continued) Pin # # of Pins Type Symbol 50-55, 58- D[11:0] 56 XCLK, XCLK* 42 Power DVDD 35 Power DGND 48 1 Power VDDV 5,11,22,28 4 Power LVDD 8,14,19,25,31 5 Power LGND 38 1 Power LPLL_VDD 36 1 Power LPLL_GND 201-0000-053 Rev. 1.31, 6/14/2006 Description Data[11] through Data[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller ...
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... CHRONTEL 2.0 Functional Description 2.1 Input Data Formats 2.1.1 Overview Two distinct methods of transferring data to the CH7304 are described. They are: • Multiplexed data, clock input at 1X the pixel rate • Multiplexed data, clock input at 2X the pixel rate For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7304 is latched with both edges of the clock (also referred to as dual edge transfer mode or DDR) ...
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... CHRONTEL 2.1.4 Data De-skew Feature The de-skew feature allows adjustment of the input setup and hold time. The input data D[11:0] can be latched slightly before or after the latching edge of XCLK depending on the amount of the de-skew. Note that the XCLK is not changed, only the time at which the data is latched relative to XCLK. The de-skew is controlled using the XCMD[3:0] bits located in Register 1Dh ...
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... CHRONTEL Table 2: Multiplexed Input Data Formats (IDF = 0, 1) IDF = Format = Pixel # P0a Bus Data D[11] G0[3] D[10] G0[2] D[9] G0[1] D[8] G0[0] D[7] B0[7] D[6] B0[6] D[5] B0[5] D[4] B0[4] D[3] B0[3] D[2] B0[2] D[1] B0[1] D[0] B0[0] Table 3: Multiplexed Input Data Formats (IDF = 2, 3) IDF = Format = Pixel # P0a Bus Data D[11] G0[4] D[10] G0[3] D[9] G0[2] D[8] B0[7] D[7] B0[6] D[6] B0[5] D[5] B0[4] D[4] B0[3] Table 4: Multiplexed Input Data Formats (IDF = 4) IDF = Format = Pixel # P0a Bus Data D[7] Cb0[7] D[6] Cb0[6] ...
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... CHRONTEL 2.2 LVDS-Out 2.2.1 Single LVDS Channel Signal Mapping Table 5: Signal Mapping for Single LVDS Channel LDC[0](1) LDC[0](2) LDC[0](3) LDC[0](4) LDC[0](5) LDC[0](6) LDC[0](7) LDC[1](1) LDC[1](2) LDC[1](3) LDC[1](4) LDC[1](5) LDC[1](6) LDC[1](7) LDC[2](1) LDC[2](2) LDC[2](3) LDC[2](4) LDC[2](5) LDC[2](6) LDC[2](7) LDC[3](1) LDC[3](2) LDC[3](3) LDC[3](4) LDC[3](5) LDC[3](6) ...
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... CHRONTEL 2.2.2 Dithering The CH7304 has a dither engine that can convert the 24-bit pixel data to 18-bit pixel data for better image quality on 18- bit panels. Maximum pixel rate supported is 100M Pixels / sec. 2.2.3 Power Sequencing The CH7304 conforms to SPWG’s requirements on power sequencing. The timing specification shown in Figure superset of the requirements dictated by the SPWG specification ...
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... CHRONTEL LVDS PLL FIFO HSYNC SYNC DETECT VSYNC LSYNCEN XCLK Detect XCLK FOSC (from oscillator) Figure 6: Detection Circuits for Panel Protection The power up sequence can occur only if (a) XCLK is not missing, (b) there are no missing HSYNC and VSYNC, (c) the PLL CLOCK is stable, and (d) PANEN is set to 1. The power down sequence happens if any of those conditions fails. ...
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... Emission Reduction Clock LVDS data path can support a +- 2.5% emission reduction clock to reduce EMI emission. The frequency and amplitude of the emission reduction triangle waveform can be programmed via the serial port. For further details, please contact Chrontel Applications Group. 2.3 Power Down The CH7304 can be powered down via software control to achieve very low standby current. For a complete description of each individual bit please refer to the appropriate register description in Registers 63h and 76h ...
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... CHRONTEL 3.0 Register Control The CH7304 is controlled via a serial port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device should retain all register values during power down modes ...
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... CHRONTEL LPLF[2:0] LVDS PLL Loop Filter Resistor Value LPLF[4:3] LVDS PLL Loop Filter Capacitor Value LPLOCK LVDS PLL Lock – read only register LPPD[4:0] LVDS PLL phase detector trim LPPDN LVDS PLL Power Down LPPRB LVDS PLL Reset LPPSD[1:0] LVDS PLL post scale divider controls ...
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... CHRONTEL 3.3 Control Registers Description Clock Detect Defeat BIT SYMBOL: Reserved Reserved Reserved Reserved Reserved TYPE: R/W R/W DEFAULT CLKDETD (bit 2) of Register CDD controls the XCLK detection circuit. When CLKDETD is ‘1’ the XCLK detection circuit is turned off, when CLKDETD is 0 the XCLK detection is on. ...
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... CHRONTEL Table 8: Delay applied to XCLK before latching input data XCMD3 XCMD2 XCMD1 Input Data Format Register BIT SYMBOL: IBS Reserved Reserved Reserved Reserved TYPE: ...
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... CHRONTEL Color Space Control BIT SYMBOL: Reserved Reserved Reserved Reserved Reserved Reserved Reserved TYPE: R/W R/W DEFAULT RGB (bit 0) of Register CSC enables the YCrCb to RGB color space conversion for IDF4. This bit must be set enable YCrCb to RGB conversion. RGB = 0 => ...
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... CHRONTEL Version ID Register BIT SYMBOL: VID7 VID6 TYPE DEFAULT Register VID is a read only register containing the version ID number of the CH7304 family. Product Number CH7304 Device ID Register BIT SYMBOL: DID7 DID6 TYPE DEFAULT Register DID is a read only register containing the device ID number of the CH7304 the state of the CONFIG pin, pin39 (bit 5 and bit 0 of register 4Bh will update accordingly) ...
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... CHRONTEL LVDS Encoding Register BIT SYMBOL: Reserved Reserved TYPE: R/W R/W DEFAULT LDI (bit 0) of register LVDSE controls OpenLDI specification selection. A ‘1’ corresponds to OpenLDI, and a ‘0’ corresponds to SPWG. LEOSWP (bit 1) of Register LVDSE provides the added flexibility to swap odd/even samples output on the LVDS link. ...
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... CHRONTEL BKLEN (bit 5) of the LPMC register enables the panel backlight. BKLEN = 0 => Disable Backlight = 1 => Enable Backlight SYNCST(bit 6) of the LPMC register is the Hsync and Vsync stability status bit. Refer to Section 2.2.4. SYNCST = 0 => Hsync or Vsync are not stable = 1 => Hsync and Vsync are stable ...
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... CHRONTEL TPBLD[6:0] (bits 6-0) of Register PST3 define the Back Light Disable time (T3), the required time after disabling the back light before the valid LVDS Clock and Data become tri-stated or disabled. Refer to Figure 5 and Table 6 in Section 2.2.3. The range 2ms to 256ms in increments of 2ms. ...
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... CHRONTEL LPFBD[3:0] (bits 3-0) of Register LPFBDC define the LVDS PLL Feed-Back Divider Control. The recommended settings are shown in Table 15 in Section 0. LPFFD[1:0] (bits 5:4) of Register LPFBDC define the LVDS PLL Feed-Forward Divider Control. The recommended settings are shown in Table 15 in Section 0. LVDS PLL VCO Control Register ...
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... CHRONTEL LVDS Output Driver Amplitude control BIT SYMBOL: LODP LODPE TYPE: R/W R/W DEFAULT LODA[2:0] (bits 2-0) of Register LODA controls the Output Driver Amplitude. See Table 12. Table 12: LVDS Output Driver Amplitude LODA2 LODA1 LODPE (bit 6) of Register LODA controls LVDS Output Driver Pre-Emphasis for both LDC[7:4] and LDC[3:0] by simultaneous Pull-up and Pull-down diode currents ...
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... CHRONTEL LVDS Power Down BIT SYMBOL: FRSTB LPLF2 TYPE: R/W R/W DEFAULT LODPDB[1:0] (bits 1-0) of Register LPD control the LVDS Output Power Down per the following table: Table 13: LVDS Output Power Down LODPDB0 LDC[3:0] , LLC & LLC* path 0 Power Down 1 Power On Note: Outputs are tri-stated in power down mode unless LODP (Register 74h, bit 7) is ‘ ...
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... CHRONTEL LVDS Control BIT SYMBOL: LPCP3 LPLF4 TYPE: R/W R/W DEFAULT LPPD[4:0] (bits 4-0) of Register LVCTL define the LVDS PLL Phase Detector Control. The recommended settings are shown in Table 15 in Section 0. LPLF[4:3] (bits 6-5) of Register LVCTL control the LVDS PLL Loop Filter Capacitor. The recommended settings are shown in Table 15 in Section 0 ...
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... CHRONTEL 4.0 Electrical Specifications 4.1 Absolute Maximum Ratings Symbol Description All power supplies relative to GND Input voltage of all digital pins T Analog output short circuit duration SC T Ambient operating temperature AMB T Storage temperature STOR T Junction temperature J T Vapor phase soldering (5 second ) VPS Vapor phase soldering (11 second ) ...
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... CHRONTEL 4.4 Digital Inputs / Outputs Symbol Description V SPD (serial port data) Output SDOL Low Voltage V Serial Port (SPC, SPD) Input SPIH High Voltage V Serial Port (SPC, SPD) Input SPIL Low Voltage V Hysteresis of Inputs HYS V D[11:0] Input High Voltage DATAIH V D[11:0] Input Low Voltage DATAIL ...
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... CHRONTEL 4.6 LVDS Output Specifications The LVDS specifications meet the requirements of ANSI/EIA/TIA-644. Refer to Figure 7 for definitions of parameters. Symbol Description Steady State Differential | Output Magnitude for logic 1 Steady State Differential | Output Magnitude for logic 0 Steady State Magnitude Difference between Logic 1 ...
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... CHRONTEL 4.7 Timing Information 4.7.1 LVDS Output Timing + swing t ui Table 16: AC Timing for LVDS Outputs Symbol Parameter Steady State Differential Output Magnitude | Voltage Difference between the two Steady State Values of Output SWING Unit time interval t Ui Rise time Fall time ...
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... CHRONTEL 4.7.2 LVDS Input Timing: Clock - Slave, Sync - Slave Mode V XCLK XCLK D[11: Figure 8: Timing for Clock - Slave, Sync - Slave Mode Table 17: Timing for Clock Symbol Parameter Setup Time: D[11:0 and DE to XCLK, XCLK* ...
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... CHRONTEL 5.0 Package Dimensions Table of Dimensions No. of Leads Milli- MIN 12 10 meters MAX 201-0000-053 Rev. 1.31, 6/14/2006 SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 Figure 9: 64 Pin LQFP Package CH7304 LEA D CO- PLANARITY H .004 “ 0.45 0.09 0° ...
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... CHRONTEL 6.0 Revision History Rev. # Date Section 1.0 4/8/03 All 1.1 5/15/03 Figure 1 4.3 6/23/03 1.2 2/3/04 4.6, 4.7.1 Register 4Bh All All Figure 1 Back Page 1.3 11/09/04 Back Page 1.31 6/14/06 Back Page 32 Description First official release, Revision 1.0 Deleted AS pin from Figure 1 Added supply current limits Added Table of Contents Added section 4.6 and 4.7.1. Corrected description of DID. ...
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... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part Number CH7304A-T CH7304A-T-TR CH7304A-TF CH7304A-TF-TR ©2006 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 201-0000-053 Rev. 1.31, 6/14/2006 Disclaimer ...