SED1330FBB ETC-unknow, SED1330FBB Datasheet
SED1330FBB
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SED1330FBB Summary of contents
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This part is replaced by SED1335. Some pin differences between SED1330 and SED1335 exist. Please check SED1335 data sheet. S-MOS Systems, Inc., will continue to support existing designs which use SED1330. DESCRIPTION The SED1330 is a CMOS low-power dot matrix ...
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SED1330 BLOCK DIAGRAM Video RAM VRAM Interface Cursor Display Address Address Controller Controller PINOUT SED1330F 60 D1 Index External CG ROM ...
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PIN DESCRIPTIONS Pin No. Pin Name SED1330F SED1330F SEL1 • • ...
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SED1330 • DC ELECTRICAL CHARACTERISTICS Parameter Operating voltage Register data retention voltage High level input voltage T Low level input voltage T High level output voltage L Low level output voltage High level input voltage C Low level input voltage ...
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AC CHARACTERISTICS System Bus READ/WRITE Timing I (8080) A0 AW8 WR, RD D0~D7 (WRITE) D0~D7 (READ) Signal Parameter Address hold time A0, CS Address setup time System cycle time WR, RD Control pulse width Data setup time ...
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SED1330 System Bus READ/WRITE Timing II (6800) E R/W A0, CS D0~D7 (WRITE) D0~D7 (READ) Signal Parameter System cycle time A0, CS, R/W Address setup time Address hold time Data setup time Data hold time Output disable ...
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Display Memory READ Timing t C EXT VCE VA0~VA15 t ASC VR/W t RCS VD0~VD7 Signal Parameter EXT 0 Clock cycle VCE high-level pulse width VCE VCE low-level pulse width Read cycle time VA0 to VA15 VCE ...
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SED1330 Display Memory WRITE Timing EXT O VCE VA0~VA15 VR/W VD0~VD7 Signal Parameter EXT 0 Clock cycle VCE HIGH-level pulse width VCE VCE LOW-level pulse width Write cycle time VCE address hold time (fall) VCE address setup time (fall) VA0 ...
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LCD Control Timing ROW YSCL WF YSCL ROW64 LP XSCL XD0~XD3 XECL XSCL t DS XD0~XD3 XECL t WXE WF(B) YD YSCL 1 frame period 1 line period ROW1 ...
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SED1330 Signal Parameter EXT 0 Clock cycle Rising time Falling time Shift clock cycle time XSCL XSCL clock pulse width X-data hold time XD0 to XD3 X-data setup time Latch data setup time LP LP signal pulse width XECL setup ...
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Oscillator Timing OSP CLO YDIS Power ON EXT 0O Signal Parameter Time to stable CLO output after power-ON CLO Time to stable CLO after sleep OFF External clock rise time External clock fall time EXT 0 External ...
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SED1330 EXAMPLE OF APPLICATION Chip A7 Selector IORQ RESET RESET VL1 VL2 VL3 VL4 Vreg VL5 8.0MHz CS7 CS6 VA13 CS0 ...
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CHARACTER CODE TABLE (BUILT-IN CHARACTER GENERATOR) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal Note: means all ...
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