sed1330 ETC-unknow, sed1330 Datasheet
sed1330
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sed1330 Summary of contents
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... SED1335 data sheet. S-MOS Systems, Inc., will continue to support existing designs which use SED1330. DESCRIPTION The SED1330 is a CMOS low-power dot matrix liquid crystal graphic display controller. The device stores in external RAM display data sent by an 8-bit microcomputer, and generates all the signals required by the LCD drivers ...
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... VA14 VA12 BA 30 VA13 VA13 VA12 29 VA11 NC VA14 VA10 VA9 VA15 VD0 VA8 VD1 VA7 20 VA6 VD2 NC 126 LCD LCD Controller Layered CG ROM Display Controller OSC 45 31 XD3 SED1330F Index SEL1 1 15 ...
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... Frame signal O Scan data shift clock for Y driver O Scan data output O Power down signal when display OFF Ratings V –0 –0 +0 300 D T – opr T –60 to 150 stg T 260 C, 10s (at lead) sol 127 SED1330 (V = 0V) SS Unit — ...
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... SED1330 • DC ELECTRICAL CHARACTERISTICS Parameter Operating voltage Register data retention voltage High level input voltage T Low level input voltage T High level output voltage L Low level output voltage High level input voltage C Low level input voltage M O High level output voltage S Low level output voltage ...
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... CYC DS8 t DH8 t t ACC8 OH8 Rating Symbol Unit Min Max t 10 — ns AH8 t 30 — ns AW8 t *1 — ns CYC t 220 — 120 — ns DS8 t 10 — ns DH8 t — 120 ns ACC8 OH8 129 SED1330 Remark CL = 100 pF + 1TTL ...
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... SED1330 System Bus READ/WRITE Timing II (6800) E R/W A0, CS D0~D7 (WRITE) D0~D7 (READ) Signal Parameter System cycle time A0, CS, R/W Address setup time Address hold time Data setup time Data hold time Output disable time Access time E Enable pulse width *1. t means a cycle of (CS.E) not E alone. ...
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... ASC – 40 — AHC – 45 — RCS – 35 — RCH C t — *2 ACV t — *3 CEA t 0 — OH2 t 0 — CE3 131 SED1330 RCH Remark 100 pF + 1TTL ...
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... SED1330 Display Memory WRITE Timing EXT O VCE VA0~VA15 VR/W VD0~VD7 Signal Parameter EXT 0 Clock cycle VCE HIGH-level pulse width VCE VCE LOW-level pulse width Write cycle time VCE address hold time (fall) VCE address setup time (fall) VA0 to VA15 VCE address hold time (rise) ...
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... LCD Control Timing ROW YSCL WF YSCL ROW64 LP XSCL XD0~XD3 XECL XSCL t DS XD0~XD3 XECL t WXE WF(B) YD YSCL 1 frame period 1 line period ROW1 DHY t WY 133 SED1330 ROW2 ...
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... SED1330 Signal Parameter EXT 0 Clock cycle Rising time Falling time Shift clock cycle time XSCL XSCL clock pulse width X-data hold time XD0 to XD3 X-data setup time Latch data setup time LP LP signal pulse width XECL setup time XECL data hold time ...
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... FCL OSS Sleep period t t RCL FCL Rating Symbol Unit Min Max t — OSP t — OSS t — RCL t — FCL 100 — 135 SED1330 Remark RES = ...
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... SED1330 EXAMPLE OF APPLICATION Chip A7 Selector IORQ RESET RESET VL1 VL2 VL3 VL4 Vreg VL5 8.0MHz CS7 CS6 VA13 CS0 VA15 VR/W CS VA0 to VA12 A0 to A12 WE D0 CS1 SRM2064 to (RAM1) CS2 RES ...
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... CHARACTER CODE TABLE (BUILT-IN CHARACTER GENERATOR) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal Note: means all dots matrix are on 137 SED1330 ...
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