U6264ASA ZMD, U6264ASA Datasheet

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U6264ASA

Manufacturer Part Number
U6264ASA
Description
Manufacturer
ZMD
Datasheet

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Part Number
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Part Number:
U6264ASA
Manufacturer:
ZMD
Quantity:
6 217
November 01, 2001
Features
F
F
F
F
F
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F
F
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F
F
F
F
Pin Configuration
DQ0
DQ1
DQ2
VSS
A12
n.c.
8192 x 8 bit static CMOS RAM
70 ns Access Time
Common data inputs and outputs
Three-state outputs
Typ. operating supply current:
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: SOP28 (300 mil)
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-40 to 125 C
30 mA
Top View
SOP
SOP28 (330 mil)
28
27
26
25
24
23
22
21
20
19
18
15
17
16
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Description
The U6264ASA07 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Write
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
- Standby
- Data Retention
1
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Automotive 8K x 8 SRAM
Signal Description
Address Inputs
Data In/Outputs
Chip Enable 1
Chip Enable 2
Output Enable
Read/Write Enable
Power Supply Voltage
Ground
not connected
available. The full CMOS data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at I
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by E2 =
L, the standby current (TTL) drops
to 150 A typ.
to
U6264ASA07
achieve
low
O
= 0 mA)
power

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U6264ASA Summary of contents

Page 1

... DQ4 14 VSS 15 DQ3 Top View November 01, 2001 Automotive SRAM Description The U6264ASA07 is a static RAM manufactured using a CMOS pro- cess technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge L), or the falling edge ...

Page 2

... U6264ASA07 Block Diagram A11 A12 A10 Address Change Detector E2 E1 Truth Table Operating Mode Standby/not selected Internal Read Read Write * Characteristics All voltages are referenced (ground). SS All characteristics are valid in the power supply voltage range and in the operating temperature range specified. ...

Page 3

... V CC(DR) CC(DR CC( 5.5 V OHZ 5 5.5 V OLZ U6264ASA07 Min. Max. 4.5 5.5 2.0 - -0.3 0.8 2.2 V +0.3 CC Min. Max 2 Unit Unit mA mA ...

Page 4

... U6264ASA07 Switching Characteristics Time to Output in Low-Z Cycle Time Write Cycle Time Read Cycle Time Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid Pulse Widths Write Pulse Width Chip Enable to End of Write Setup Times Address Setup Time ...

Page 5

... the capacitance is 5 pF. Conditions Symbol MHz U6264A S 07 Operating Temperature Range A = -40 to 125 °C 5 U6264ASA07 5 V 960 510 Min. Max. Unit Internal Code Access Time ...

Page 6

... U6264ASA07 Read Cycle 1 (during Read cycle Output Read Cycle 2 (during Read cycle Output Write Cycle 1 (W-controlled Input DQ i Output Addresses Valid t a(A) Previous Data Valid t v( Addresses Valid ...

Page 7

... The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. November 01, 2001 t cW Addresses Valid t t su(A) w(E) t su(E) t su(W) t su(D) Input Data Valid t dis(W) t t(QX) High Addresses Valid t su( su(A) w(E) t su(W) t su(D) Input Data Valid t dis(W) t t(QX H-level 7 U6264ASA07 t h(A) t h(D) t h(A) t h(D) High-Z ...

Page 8

... ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. November 01, 2001 Grenzstraße 28 D-01109 Dresden Phone: +49 351 8822 306 Zentrum Mikroelektronik Dresden AG Fax: +49 351 8822 337 Email: sales@zmd.de U6264ASA07 D-01101 Dresden Germany http://www.zmd.de ...

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