U6264AS1A07 ZMD [Zentrum Mikroelektronik Dresden AG], U6264AS1A07 Datasheet

U6264AS1A07

Manufacturer Part Number

U6264AS1A07

Description

Automotive 8K x 8 SRAM

Manufacturer

ZMD [Zentrum Mikroelektronik Dresden AG]

Datasheet

1.U6264AS1A07.pdf (8 pages)

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Features

December 12, 1997

Pin Configuration

8192 x 8 bit static CMOS RAM

70 ns Access Time

Common data inputs and outputs

Three-state outputs

Typ. operating supply current:

TTL/CMOS-compatible

Automatic reduction of power

dissipation in long Read or Write

cycles

Power supply voltage 5 V

Operating temperature ranges

Quality assessment according to

CECC 90000, CECC 90100 and

CECC 90111

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity > 100 mA

Packages: SOP28 (300 mil)

DQ1

DQ2

DQ0

VSS

A12

n.c.

-40 to 125 C

30 mA

Top View

SOP28 (330 mil)

SOP

DQ3

VCC

W (WE)

E2 (CE2)

A11

G (OE)

A10

E1 (CE1)

DQ7

DQ6

DQ5

DQ4

Description

The U6264ASA07 is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read

- Write

The memory array is based on a

6-transistor cell.

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active.

During the active state (E1 = L and

E2 = H), each address change

leads to a new Read or Write cycle.

In a Read cycle, the data outputs

are activated by the falling edge of

G, afterwards the data word read

will be available at the outputs

DQ0 - DQ7. After the address

- Standby

- Data Retention

Pin Description

Signal Name

A0 - A12

DQ0 - DQ7

VCC

VSS

n.c.

Automotive 8K x 8 SRAM

Signal Description

Address Inputs

Data In/Outputs

Chip Enable 1

Chip Enable 2

Output Enable

Read/Write Enable

Power Supply Voltage

Ground

not connected

change, the data outputs go High-Z

until the new read information is

available. The full CMOS data out-

puts have no preferred state. If the

memory is driven by CMOS levels

in the active state, and if there is no

change of the address, data input

and control signals W or G, the ope-

rating current (at I

to the value of the operating current

in the Standby mode. The Read

cycle is finished by the falling edge

of E2 or W, or by the rising edge of

E1, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E2, all

inputs consist of NOR gates, so that

no pull-up/pull-down resistors are

required. This gate circuit allows to

achieve low power standby require-

ments by activation with TTL-levels

too.

If the circuit is inactivated by E2 = L,

the standby current (TTL) drops to

150 A typ.

U6264ASA07

= 0 mA) drops

Related parts for U6264AS1A07

U6264AS1A07 Summary of contents

Page 1

Features F 8192 x 8 bit static CMOS RAM Access Time F Common data inputs and outputs F Three-state outputs F Typ. operating supply current TTL/CMOS-compatible F Automatic reduction of power dissipation in long ...

Page 2

U6264ASA07 Block Diagram A11 A12 A10 E2 E1 Truth Table Operating Mode E1 * Standby/not selected H Internal Read L Read L Write Characteristics All ...

Page 3

Recommended Operating Conditions Power Supply Voltage Data Retention Voltage Input Low Voltage* Input High Voltage * - Pulse Width 10 ns Electrical Characteristics Supply Current - Operating Mode Supply Current - Standby Mode (TTL level) Output High Voltage ...

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U6264AS1A07 datasheet download

U6264AS1A07 ZMD [Zentrum Mikroelektronik Dresden AG], U6264AS1A07 Datasheet

U6264AS1A07

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U6264AS1A07 Summary of contents

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