HD6433278F HITACHI, HD6433278F Datasheet
HD6433278F
Related parts for HD6433278F
HD6433278F Summary of contents
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... OMC942723054 HITACHI SINGLE-CHIP MICROCOMPUTER HD6473298, HD6433298, HD6413298 HD6473278, HD6433278, HD6413278 H8/329 SERIES H8/329 H8/328 HD6433288 H8/327 H8/326 HD6433268 HARDWARE MANUAL ...
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... Time) version, and a ROMless version, providing a quick and flexible response to conditions from ramp-up through full-scale volume producion, even for applications with frequently-changing specifications. This manual describes the hardware of the H8/329 Series. Refer to the H8/300 Series Programming Manual for a detailed description of the instruction set. Notes: * ZTAT is a registered trademark of Hitachi, Ltd. Preface ...
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Section 1. Overview ............................................................................................................... 1.1 Overview............................................................................................................................... 1.2 Block Diagram...................................................................................................................... 1.3 Pin Assignments and Functions............................................................................................ 1.3.1 Pin Arrangement...................................................................................................... 1.3.2 Pin Functions ........................................................................................................... Section 2. MCU Operating Modes and Address Space 2.1 Overview............................................................................................................................... 15 2.1.1 Mode Selection ........................................................................................................ 15 2.1.2 Mode and ...
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Block Data Transfer Instruction .............................................................................. 50 3.6 CPU States ............................................................................................................................ 51 3.6.1 Program Execution State ......................................................................................... 52 3.6.2 Exception-Handling State........................................................................................ 52 3.6.3 Power-Down State ................................................................................................... 53 3.7 Access Timing and Bus Cycle .............................................................................................. 53 3.7.1 Access to On-Chip Memory ...
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Block Diagram......................................................................................................... 113 6.1.3 Input and Output Pins .............................................................................................. 115 6.1.4 Register Configuration ............................................................................................ 115 6.2 Register Descriptions............................................................................................................ 116 6.2.1 Free-Running Counter (FRC)—H'FF92.................................................................. 116 6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94....................... 117 6.2.3 Input Capture Registers ...
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External Reset of TCNT .......................................................................................... 155 7.3.4 Setting of TCSR Overflow Flag (OVF) .................................................................. 156 7.4 Interrupts............................................................................................................................... 157 7.5 Sample Application............................................................................................................... 157 7.6 Application Notes ................................................................................................................. 158 Section 8. Serial Communication Interface 8.1 Overview............................................................................................................................... 163 8.1.1 Features.................................................................................................................... 163 8.1.2 ...
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A/D Control Register (ADCR)—H'FFEA............................................................... 215 9.3 Operation .............................................................................................................................. 215 9.3.1 Single Mode (SCAN = 0) ........................................................................................ 216 9.3.2 Scan Mode (SCAN = 1) .......................................................................................... 219 9.3.3 Input Sampling Time and A/D Conversion Time.................................................... 222 9.3.4 External Trigger Input Timing................................................................................. ...
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Sample Application of Software Standby Mode ..................................................... 243 12.4.4 Application Note ..................................................................................................... 244 12.5 Hardware Standby Mode ...................................................................................................... 245 12.5.1 Transition to Hardware Standby Mode.................................................................... 245 12.5.2 Recovery from Hardware Standby Mode................................................................ 245 12.5.3 Timing Relationships............................................................................................... 246 Section 13. ...
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Appendix C. Pin States C.1 Pin States in Each Mode ....................................................................................................... 317 Appendix D. Timing of Transition to and Recovery from Hardware Standby Mode Appendix E. Package Dimensions ......................................................................................................... 317 ................................................................................................ 319 .................................................................................... 320 vii ...
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... The entire H8/329 Series is available with masked ROM. The H8/329 and H8/327 are also available in ZTAT™ versions* that can be programmed at the user site, and in ROMless versions. Notes: * ZTAT is a registered trademark of Hitachi, Ltd. Table 1-1 lists the features of the H8/329 Series. ...
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Table 1-1. Features Item Specification CPU Two-way general register configuration • Eight 16-bit registers, or • Sixteen 8-bit registers High-speed operation • Maximum clock rate: 10MHz • Add/subtract: • Multiply/divide: Streamlined, concise instruction set • Instruction length ...
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Table 1-1. Features (cont.) Item Specification A/D converter • 8-bit resolution • Eight channels: single or scan mode (selectable) • Start of A/D conversion can be externally triggered • Sample-and-hold function I/O ports • 43 input/output lines (16 of which ...
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... HD6473298F HD6473298CP HD6433298P HD6433298F HD6433298CP HD6413298P HD6413298F HD6413298CP H8/328 HD6433288P HD6433288F HD6433288CP H8/327 HD6473278C HD6473278P HD6473278F HD6473278CP HD6433278P HD6433278F HD6433278CP HD6413278P HD6413278F HD6413278CP H8/326 HD6433268P HD6433268F HD6433268CP 3-V version Package HD6473298VC 64-pin windowed shrink DIP (DC-64S) HD6473298VP 64-pin shrink DIP (DP-64S) HD6473298VF ...
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Block Diagram Figure 1-1 shows a block diagram of the H8/329 Series. Clock pulse gener- ator ...
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Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement of the FP-64A package. Figure 1-4 shows the pin arrangement of the CP-68 package. ...
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P5 /TxD /RxD /SCK 3 2 RES 4 NMI STBY ...
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P5 /TxD /RxD /SCK 12 2 RES 13 NMI STBY XTAL 19 EXTAL ...
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Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the DC-64S, DP-64S, FP-64A, and CP-68 packages in each operating mode. Table 1-2. Pin Assignments in Each Operating Mode (1) Pin ...
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Table 1-2. Pin Assignments in Each Operating Mode (2) Pin No. DC-64S DP-64S FP-64A CP- — — ...
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Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3. Pin Functions (1) DC-64S Type Symbol DP-64S FP-64A CP-68 Power Clock XTAL 17 EXTAL 18 ...
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Table 1-3. Pin Functions (2) DC-64S Type Symbol DP-64S FP-64A CP-68 Data bus WAIT Bus 8 control NMI Interrupt 13 ...
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Table 1-3. Pin Functions (3) DC-64S Type Symbol DP-64S FP-64A CP-68 Serial com- TxD 9 munication interface RxD 10 SCK 11 16-bit free- FTOA, 32, running FTOB 37 timer FTCI 31 FTIA ...
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Table 1-3. Pin Functions (4) DC-64S Type Symbol DP-64S FP-64A CP-68 General purpose I ...
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Section 2. MCU Operating Modes and Address Space 2.1 Overview 2.1.1 Mode Selection The H8/329 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD The ROMless versions ...
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Mode and System Control Registers (MDCR and SYSCR) Table 2-2 lists the registers related to the operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins ...
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip ...
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Mode Control Register (MDCR)—H'FFC5 Bit 7 — Initial value 1 Read/Write — Note: * Initialized according to MD The mode control register (MDCR eight-bit register that indicates the operating mode of the chip. Bits 7 to 5—Reserved: ...
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Address Space Maps Figures 2-1 to 2-4 show memory maps of the H8/329, H8/328, H8/327, and H8/326 in modes 1, 2, and 3. Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector Table H'0047 H'0048 External Address Space H'FB7F ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector Table H'0047 H'0048 External Address Space H'FB7F H'FB80 On-Chip RAM * byte H'FF7F H'FF80 External Address Space H'FF87 H'FF88 On-Chip Register Field H'FFFF Notes not access these ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector Table H'0047 H'0048 External Address Space H'FB7F H'FB80 *1, *2 Reserved H'FD7F H'FD80 On-Chip RAM *2 , 512 Bytes H'FF7F H'FF80 External Address Space H'FF87 H'FF88 On-Chip Register Field H'FFFF Notes: ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector Table H'0047 H'0048 External Address Space H'FB7F H'FB80 *1, *2 Reserved H'FE7F H'FE80 *2 On-Chip RAM , 256 Bytes H'FF7F H'FF80 External Address Space H'FF87 H'FF88 On-Chip Register Field H'FFFF Notes: ...
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Overview The H8/329 Series has the H8/300 CPU: a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high- speed operation. 3.1.1 Features The main features ...
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Register Configuration Figure 3-1 shows the register structure of the CPU. There are two groups of registers: the general registers and control registers. 7 R0H R1H R2H R3H R4H R5H R6H R7H 15 CCR 3.2.1 General Registers All the ...
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Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Each instruction ...
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Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an instruction. Bit 2—Zero Flag (Z): This flag is set to “1” to indicate a zero result and cleared to “0” to indicate ...
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Addressing Modes 3.3.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 3-1. Addressing Modes No. Addressing mode (1) Register direct (2) Register indirect (3) Register indirect with displacement ...
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MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. • Register Indirect with Pre-Decrement—@–Rn The @–Rn mode is used with ...
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How to Calculate Where the Execution Starts Table 3-2 shows how to calculate the Effective Address (EA: Effective Address) for each addressing mode. In the operation instruction, 1) register direct, as well as 6) immediate (for each instruction, ADD.B, ...
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Addressing mode and No. instruction format 1 Register direct regm regn 2 Register indirect, @ reg 3 Register indirect with displacement, @(d:16, Rn ...
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Table 3-2. Effective Address Calculation (2) Addressing mode and No. instruction format 5 Absolute address @aa abs @aa: abs 6 Immediate #xx IMM #xx: IMM 7 PC-relative @(d:8, ...
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Table 3-2. Effective Address Calculation (3) Addressing mode and No. instruction format 8 Memory indirect, @@aa abs Notation reg: General register op: Operation code disp: Displacement IMM: Immediate data abs: Absolute address Effective address calculation 0 ...
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Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit ..., 7) in ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 3-3. Data type 1-Bit data 1-Bit data Byte data Byte data Word data 4-Bit BCD data 4-Bit BCD ...
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Memory Data Formats Figure 3-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as “0.” ...
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Instruction Set Table 3-3 lists the H8/300 instruction set. Table 3-3. Instruction Classification Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Notes: *1 PUSH Rn is equivalent to MOV.W Rn, @–SP. ...
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Operation Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand SP Stack pointer PC Program counter CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of ...
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Data Transfer Instructions Table 3-4 describes the data transfer instructions. Figure 3-5 shows their object code formats. Table 3-4. Data Transfer Instructions Instruction Size* B/W MOV B MOVTPE B MOVFPE W PUSH W POP Note: * Size: operand size ...
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disp abs #imm. Op abs. Op Op: Operation field Register field disp.: Displacement abs.: Absolute address #imm.: Immediate data Figure ...
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Arithmetic Operations Table 3-5 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations” for their object codes. Table 3-5. Arithmetic Instructions Instruction Size* B/W ADD SUB B ADDX SUBX B INC DEC W ADDS SUBS B ...
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Logic Operations Table 3-6 describes the four instructions that perform logic operations. See figure 3-6 in section 3.5.4, “Shift Operations,” for their object codes. Table 3-6. Logic Operation Instructions Instruction Size* B AND XOR B NOT ...
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Op: Operation field Register field #imm.: Immediate data Figure 3-6. Arithmetic, Logic, and Shift Instruction Codes ...
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Bit Manipulations Table 3-8 describes the bit-manipulation instructions. Figure 3-7 shows their object code formats. Table 3-8. Bit-Manipulation Instructions (1) Instruction Size* B BSET B BCLR B BNOT B BTST B BAND BIAND B BOR BIOR B BXOR Note: ...
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Table 3-8. Bit-Manipulation Instructions (2) Instruction Size* B BIXOR B BLD BILD B BST BIST Note: * Size: operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modify- write instructions. They read a ...
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Before Execution of BCLR Instruction P4 7 Input/output Input Pin state Low DDR Execution of BCLR Instruction BCLR #0, @P4DDR After Execution of BCLR Instruction P4 7 Input/output Output Output Output Output Output Output Output Input Pin ...
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Op: Operation field Register field abs.: Absolute address #imm.: Immediate data Figure ...
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Branching Instructions Table 3-9 describes the branching instructions. Figure 3-8 shows their object code formats. Table 3-9. Branching Instructions Instruction Size — Bcc — JMP — JSR — BSR — RTS Function Branches to the specified address if condition ...
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Op: Operation field cc: Condition field Register field disp.: Displacement abs.: Absolute address Figure 3-8. Branching Instruction Codes 8 7 disp abs. abs. ...
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System Control Instructions Table 3-10 describes the system control instructions. Figure 3-9 shows their object code formats. Table 3-10. System Control Instructions Instruction Size — RTE — SLEEP B LDC B STC B ANDC B ORC B XORC — ...
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Op Op: Operation field Register field #imm.: Immediate data Figure 3-9. System Control Instruction Codes 3.5.8 Block Data Transfer Instruction Table 3-11 describes the EEPMOV instruction. Figure 3-10 shows its object code format. Table 3-11. Block ...
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Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified ...
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Exception handling request Exception - handling state RES = 1 Reset state Notes transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode transition from any ...
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Power-Down State The power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU halts, but CPU ...
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Internal address bus Internal Read signal Internal data bus (read) Internal Write signal Internal data bus (write) Figure 3-13. On-Chip Memory Access Cycle Ø Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 3-14. ...
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Access to On-Chip Register Field and External Devices The on-chip register field (I/O ports, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: T accessed per cycle, via an 8-bit data ...
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Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 3-16. Pin States during On-Chip Register Field Access Cycle Ø Address bus AS RD WR: High Data bus Figure 3-17 (a). External Device Access Timing ...
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T1 state Ø Address bus AS RD: High WR Data bus Figure 3-17 (b). External Device Access Timing (Write) Write cycle T2 state T3 state Address Write data 57 ...
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Section 4. Exception Handling 4.1 Overview The H8/329 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1 indicates their priority and the timing of their hardware exception-handling sequences. Table 4-1. Hardware Exception-Handling Sequences and Priority Type ...
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The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit in the condition code register (CCR) is set to “1.” (2) The CPU loads the program counter with the ...
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RES Ø bits) (1),(3) Reset vector address: (1)=H'0000, (3)=H'0001 (2),(4) Starting address of program (contents of reset vector): (2)=upper byte, (4)=lower byte (5),(7) Starting address of program: ...
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Disabling of Interrupts after Reset After a reset interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program ...
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Table 4-2. Interrupts Interrupt source NMI IRQ 0 IRQ 1 IRQ 2 Reserved 16-Bit free- ICIA (Input capture A) running timer ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare ...
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Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), and IRQ enable register (IER). Table 4-3. Registers Read by Interrupt Controller Name System control register IRQ sense control register IRQ enable register ...
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Bits 0 to 2—IRQ to IRQ 0 IRQ to IRQ are level-sensed or sensed on the falling edge Bits IRQ SC to IRQ SC Description interrupt is generated when IRQ inputs ...
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If execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. Set the I bit to “1” in the CCR, masking interrupts. Note that ...
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Internal Interrupts Eighteen internal interrupts can be requested by the on-chip supporting modules. Each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. All internal interrupts are masked ...
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The IRQ interrupts and interrupts from the on-chip supporting modules all have corresponding enable bits. When the enable bit is cleared to “0,” the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These interrupts ...
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Program execution Interrupt requested? Yes No IRQ ? 0 Yes IRQ 1 Yes Latch vector No. Save PC Save CCR Reset I 1 Read vector address Branch to software interrupt-handling routine Figure 4-4. Hardware Interrupt-Handling Sequence 69 No Yes NMI? ...
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SP-4 SP-3 SP-2 SP-1 SP(R7) Stack area Before interrupt is accepted PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first instruction executed after return. 2. Registers must be saved ...
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Interrupt accepted Interrupt priority decision. Wait for end of instruction. Interrupt request signal Ø Internal address (1) bus Internal Read signal Internal Write signal Internal 16-bit (2) data bus (1) Instruction prefetch address (Pushed on stack. Instruction is executed on ...
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Interrupt Response Time Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since the H8/329 Series accesses its on-chip memory 16 bits at ...
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Figure 4-7 shows an example in which the OCIAE bit is cleared to “0.” Ø Internal address bus Internal write signal OCIAE OCFA OCIA interrupt signal Figure 4-7. Contention between Interrupt and Disabling Instruction The above contention does not occur ...
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SP BSR instruction H'FECF set Upper byte of program counter Lower byte of program counter General register Stack pointer Figure 4-8. Example of Damage Caused by Setting ...
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Overview The H8/329 Series has seven parallel I/O ports, including: • Five 8-bit input/output ports—ports and 6 • One 8-bit input port—port 7 • One 3-bit input/output port—port 5 Ports 1, 2, and 3 have ...
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Table 5-1. Port Functions Port Description Port 1 • 8-bit input-output P1 port • Can drive LEDs • Input pull-ups Port 2 • 8-bit input-output P2 port • Can drive LEDs • Input pull-ups Port 3 • 8-bit input-output P3 ...
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Port 1 Port 8-bit input/output port that also provides the low bits of the address bus. The function of port 1 depends on the MCU mode as indicated in table 5-2. Table 5-2. Functions of Port ...
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P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an output pin if the corresponding bit in P1DDR is set to “1,” and as an input pin if the bit ...
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Reset: A reset clears P1DDR, P1DR, and P1PCR to all “0,” placing all pins in the input state with the pull-up transistors off. In mode 1, when the chip comes out of reset, P1DDR is set to all “1.” Hardware ...
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P1 n 5.3 Port 2 Port 8-bit input/output port that also provides the high bits of the address bus. The function of port 2 depends on the MCU mode as indicated in table 5-5. Table 5-5. Functions ...
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Pins of port 2 can drive a single TTL load and a 90pF capacitive load when they are used as output pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input pins, they ...
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Port 2 Input Pull-Up Control Register (P2PCR)—H'FFAD Bit 7 P2 PCR P2 7 Initial value 0 Read/Write R/W P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port bit in P2DDR is cleared ...
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Table 5-7 indicates the states of the input pull-up transistors in each operating mode. Table 5-7. States of Input Pull-Up Transistors (Port 2) Mode Reset Hardware standby 1 Off Off 2 Off Off 3 Off Off Notes: Off: The input ...
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Port 3 Port 8-bit input/output port that also provides the external data bus. The function of port 3 depends on the MCU mode as indicated in table 5-8. Table 5-8. Functions of Port 3 Mode 1 ...
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Port 3 Data Register (P3DR)—H'FFB6 Bit Initial value 0 Read/Write R/W P3DR is an 8-bit register containing the data for pins P3 output pins it reads the value in the P3DR latch, but for input pins, it ...
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Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears P3DDR, P3DR, and P3PCR to all “0.” All pins are placed in the high-impedance state with the pull-up transistors off. Software Standby Mode: In the ...
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P3 n Figure 5-3. Port 3 Schematic Diagram Mode 3 RP3P Mode 3 External address write Mode 3 Mode WP3P: WP3D: WP3: RP3P : RP3 Reset PCR ...
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Port 4 Port 8-bit input/output port that also provides pins for interrupt input (IRQ trigger input, system clock (Ø) output, and bus control signals (in the expanded modes). Pins have different functions in ...
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Port 4 Data Direction Register (P4DDR)—H'FFB5 Bit 7 P4 DDR P4 7 Modes 1 and 2 Initial value 0 Read/Write W Mode 3 Initial value 0 Read/Write W P4DDR is an 8-bit register that selects the direction of each pin ...
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In mode 3 (single-chip mode), these pins can be used for general-purpose input or output. Pin modes 1 and 2, this pin is used for system clock (Ø) output mode 3, this pin is used ...
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Software Standby Mode: All pins remain in their previous state. For RD, WR, AS, and Ø this means the High output state. Figures 5-4 to 5-8 show schematic diagrams of port WP4D: Write Port 4 DDR WP4: ...
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P4 n WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port Figure 5-5. Port 4 Schematic Diagram (Pins P4 Reset DDR n C WP4D Reset ...
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Hardware standby Mode Mode WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port Figure 5-6. Port 4 Schematic Diagram (Pins P4 Mode ...
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P4 6 WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 Note: Set-priority * Figure 5-7. Port 4 Schematic Diagram (Pin P4 Mode 1, 2 Hardware standby RP9 94 Reset DDR ...
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Mode WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 Figure 5-8. Port 4 Schematic Diagram (Pin P4 Reset DDR 7 C WP4D Reset ...
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Port 5 Port 3-bit input/output port that also provides input and output pins for the serial communi- cation interface (SCI). The pin functions depend on control bits in the serial control register (SCR). Pins not used ...
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Port 5 Data Register (P5DR)—H'FFBA Bit 7 — Initial value 1 Read/Write — P5DR is an 8-bit register containing the data for pins P5 output pins (P5DDR = “1”) it reads the value in the P5DR latch, but for input ...
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P5 0 WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port 5 Figure 5-9. Port 5 Schematic Diagram (Pin P5 Reset DDR 0 C WP5D Reset ...
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P5 1 WP5D: WP5: RP5: Figure 5-10. Port 5 Schematic Diagram (Pin P5 Reset Q P5 DDR 1 C WP5D Reset WP5 RP5 Write Port 5 DDR Write Port 5 Read Port 5 H8/329 U.M. ...
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P5 2 WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port 5 Figure 5-11. Port 5 Schematic Diagram (Pin P5 Reset DDR 2 C WP5D Reset ...
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Port 6 Port 8-bit input/output port that also provides input and output pins for the 16-bit free- running timer and 8-bit timers. The pin functions depend on control bits in the control registers of the timers. ...
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Port 6 Data Register (P6DR)—H'FFBB Bit Initial value 0 Read/Write R/W P6DR is an 8-bit register containing the data for pins P6 output pins (P6DDR = “1”) it reads the value in the P6DR latch, but for ...
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Pin P6 : This pin can be used for general-purpose input or output, input of the FTID input capture 5 signal to the 16-bit free-running timer, or input of an external clock signal to 8-bit timer 1. FTID input operates ...
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P6 0 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-12. Port 6 Schematic Diagram (Pin P6 Reset DDR 0 C WP6D Reset ...
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P6 1 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-13. Port 6 Schematic Diagram (Pin P6 Reset DDR 1 C WP6D Reset ...
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P6 2 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-14. Port 6 Schematic Diagram (Pin P6 Reset DDR 2 C WP6D Reset ...
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P6 n WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port Figure 5-15. Port 6 Schematic Diagram (Pins P6 Reset DDR n C WP6D Reset ...
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P6 4 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-16. Port 6 Schematic Diagram (Pin P6 Reset DDR 4 C WP6D Reset ...
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P6 6 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-17. Port 6 Schematic Diagram (Pin P6 Reset DDR 6 C WP6D Reset ...
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P6 7 WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-18. Port 6 Schematic Diagram (Pin P6 Reset DDR 7 C WP6D Reset ...
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Port 7 Port 8-bit input port that also provides the analog input pins for the A/D converter module. The pin functions are the same in both the expanded and single-chip modes. Table 5-17 lists the pin ...
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Section 6. 16-Bit Free-Running Timer 6.1 Overview The H8/329 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free- running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two ...
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Block Diagram Figure 6-1 shows a block diagram of the free-running timer. External clock source FTCI Clock select FTOA FTOB Control logic FTIA FTIB FTIC FTID FRC: Free-Running Counter (16 bits) OCRA, B: Output Compare Register A, B (16 ...
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Input and Output Pins Table 6-1 lists the input and output pins of the free-running timer module. Table 6-1. Input and Output Pins of Free-Running Timer Module Name Abbreviation Counter clock input FTCI Output compare A FTOA Output compare ...
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Table 6-2. Register Configuration (cont.) Name Input capture register B (High) Input capture register B (Low) Input capture register C (High) Input capture register C (Low) Input capture register D (High) Input capture register D (Low) 6.2 Register Descriptions 6.2.1 ...
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Output Compare Registers A and B (OCRA and OCRB)—H'FF94 Bit Initial value Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Write OCRA and ...
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Note: * The FRC contents are transferred to the input capture register regardless of the value of the input capture flag (ICFA/B/C/D). Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in ...
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Table 6-3. Buffered Input Capture Edge Selection (Example) IEDGA IEDGC Input Capture Edge 0 0 Captured on falling edge of input capture A (FTIA Captured on both rising and falling edges of input capture A (FTIA ...
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The input capture registers are initialized to H'0000 at a reset and in the standby modes. Note: When input capture is detected, the FRC value is transferred to the input capture register even if the input capture flag is already ...
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Bit 5 ICICE Description 0 Input capture interrupt request C (ICIC) is disabled. 1 Input capture interrupt request C (ICIC) is enabled. Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt D (ICID) ...
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Bit 1 OVIE Description 0 Timer overflow interrupt request (FOVI) is disabled. 1 Timer overflow interrupt request (FOVI) is enabled. Bit 0—Reserved: This bit cannot be modified and is always read as “1.” 6.2.5 Timer Control/Status Register (TCSR)—H'FF91 Bit 7 ...
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Bit 6—Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture B event. If BUFEB = “0,” ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = “1,” ICFB ...
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Bit 4 ICFD Description 0 To clear ICFD, the CPU must read ICFD after it has been set to “1,” then write a “0” in this bit. 1 This bit is set to 1 when an FTID input signal is ...
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Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match). Bit 0 CCLRA Description 0 The FRC is not cleared. 1 The FRC is cleared at compare-match ...
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Bit 5—Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on the selected edge of the input capture C signal (FTIC). Bit 5 IEDGC Description 0 Input capture C events are recognized on the ...
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Bit 1 Bit 0 CKS1 CKS0 Description 0 0 Ø/2 Internal clock source 0 1 Ø/8 Internal clock source 1 0 Ø/32 Internal clock source 1 1 External clock source (rising edge) 6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97 Bit ...
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Bit 2—Output Enable B (OEB): This bit enables or disables output of the output compare B signal (FTOB). Bit 2 OEB Description 0 Output compare B output is disabled. 1 Output compare B output is enabled. Bit 1—Output Level A ...
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Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in ...
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Upper byte read CPU reads data H'AA (2) Lower byte read CPU reads data H'55 Figure 6-4 (b). Read Access to FRC (when FRC Contains H'AA55) 6.4 Operation 6.4.1 FRC Incrementation Timing The FRC increments on a pulse generated ...
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Internal clock FRC clock pulse FRC N – 1 Figure 6-5. Increment Timing for Internal Clock Source External Clock: If external clock input is selected, the FRC increments on the rising edge of the FTCI clock signal. Figure 6-6 ...
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Output Compare Timing (1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are set to “1” internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. ...
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Output Timing: When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 6-9 shows the timing of this operation for ...
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Input at FTI pin Internal input capture signal Figure 6-11. Input Capture Timing (Usual Case) If the upper byte of ICRx is being read when the input capture signal arrives, the internal input capture signal is delayed by one ...
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Figure 6-14 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), ...
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Timing of Input Capture Flag (ICF) Setting: The input capture flag ICFx ( set to “1” by the internal input capture signal. Figure 6-15 shows the timing of this operation. Ø Internal input ...
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Interrupts The free-running timer can request seven types of interrupts: input capture (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding enable and ...
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Application Notes Application programmers should note that the following types of contention can occur in the free- running timers. (1) Contention between FRC Write and Clear internal counter clear signal is generated during the T state of ...
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Contention between FRC Write and Increment FRC increment pulse is generated during the T state of a write cycle to the lower byte of the free-running counter, the write takes 3 priority and the FRC is not ...
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Contention between OCR Write and Compare-Match compare-match occurs during the T state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the 3 compare-match signal is inhibited. Figure 6-20 ...
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Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, ...
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Table 6-5. Effect of Changing Internal Clock Sources (cont.) No. Description High Low: CKS1 and CKS0 are 3 rewritten while old clock source is High and new clock source is Low. High High: CKS1 and CKS0 are 4 rewritten while ...
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Overview The H8/329 Series includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to ...
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Internal External clock sources clock source TMCI Clock select TMO TMRI Control logic Interrupt signals TCR: Timer Control Register (8 bits) TCSR: Timer Control Status Register (8 bits) TCORA: Time Constant Register A (8 bits) TCORB: Time Constant Register B ...
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Register Configuration Table 7-2 lists the registers of the 8-bit timer module. Each channel has an independent set of registers. Table 7-2. 8-Bit Timer Registers Name Timer control register Timer control/status register Timer constant register A Timer constant register ...
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The timer counters are initialized to H' reset and in the standby modes. Bit 7 Initial value 1 Read/Write R/W Bit 7 CMIEB CMIEA Initial value 0 Read/Write R R/W R/W R/W ...
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Bit 7 CMIEB Description 0 Compare-match interrupt request B (CMIB) is disabled. 1 Compare-match interrupt request B (CMIB) is enabled. 7.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1) TCORA and TCORB ...
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Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the timer counter. Six internal clock sources, derived by ...
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Bit 7 CMFB Initial value 0 Read/Write R/(W)* R/(W)* R/(W)* The TCRs are initialized to H' reset and in the standby modes. For timing diagrams, see section 7.3, “Operation.” Bit ...
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Bit 6—Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer control/status register (TCSR) is set to “1.” Bit 5 OVF Description 0 To clear OVF, the ...
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Serial/Timer Control Register (STCR)—H'FFC3 Bit 7 — Initial value 1 Read/Write — The STCR is an 8-bit readable/writable register that controls the serial communication interface and selects internal clock sources for the timer counters. The STCR is initialized to ...
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Timer Control/Status Register (TCSR)—H'FFC9 (TMR0), H'FFD1 (TMR1) Note: * Software can write a “0” in bits clear the flags, but cannot write a “1” in these bits. The TCSR is an 8-bit readable and partially ...
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External clock source TCNT clock pulse TCNT N – 1 Bit 5—Timer Overflow Flag (OVF): This status flag is set to “1” when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software. It ...
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If compare-match A and B occur simultaneously, any conflict is resolved as explained in item (4) in section 7.6, “Application Notes.” Ø TCNT TCOR Internal compare-match signal CMF After a reset, the timer output is “0” until the first compare-match ...
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Operation 7.3.1 TCNT Incrementation Timing Ø ø Internal compare-match signal TCNT The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Internal clock sources are created from ...
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See figure 7-4. The counter will not increment correctly if the pulse width is shorter than these values. Ø ø TCNT Internal overflow signal OVF H'FF ...
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Figure 7-3. Count Timing for External Clock Input Figure 7-4. Minimum External Clock Pulse Widths (Example) 7.3.2 Compare Match Timing (1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to “1” ...
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Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 7-5 shows the timing of the setting of the compare-match flags. Figure 7-5. Setting ...
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Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR, the timer counter can be cleared when compare-match occurs. Figure 7-7 shows the timing of this operation. Figure 7-7. Timing of Compare-Match ...
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Setting of TCSR Overflow Flag (OVF) The overflow flag (OVF) is set to “1” when the timer count overflows (changes from H'FF to H'00). Figure 7-9 shows the timing of this operation. Ø Internal address bus Internal write signal ...
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Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable bits are set in the TCR and TCSR. ...
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In the TCSR, bits OS3 to OS0 are set to “0110,” causing the output to change to “1” on No. Description *1 High Low : Clock select bits are 3 rewritten while old clock source is High and new ...
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Section 8. Serial Communication Interface 8.1 Overview The H8/329 Series includes a serial communication interface (SCI) for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. 8.1.1 Features The features of the on-chip ...
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Block Diagram Figure 8-1 shows a block diagram of the serial communication interface. RDR RxD RSR TxD SCK RSR: Receive Shift Register (8 bits) RDR: Receive Data Register (8 bits) TSR: Transmit Shift Register (8 bits) TDR: Transmit Data ...
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Input and Output Pins Table 8-1 lists the input and output pins used by the SCI module. Table 8-1. SCI Input/Output Pins Name Serial clock Receive data Transmit data 8.1.4 Register Configuration Table 8-2 lists the SCI registers. These ...
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Register Descriptions 8.2.1 Receive Shift Register (RSR) Bit 7 Read/Write — The RSR receives incoming data bits. When one data character has been received transferred to the receive data register (RDR). The CPU cannot read or write ...
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Transmit Data Register (TDR)—H'FFDB Bit 7 Initial value 1 Read/Write R/W The TDR is an 8-bit readable/writable register that holds the next character to be transmitted. When the TSR becomes empty, the character written in the TDR is transferred ...
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Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode ignored in synchronous mode. The character length is always eight bits in synchronous mode. Bit 6 CHR Description 0 8 bits per character ...
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Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits ignored in the synchronous mode. Bit 3 STOP Description 0 One stop bit Transmit: one stop bit is added. Receive: one stop bit is checked ...
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Serial Control Register (SCR)—H'FFDA Bit 7 TIE Initial value 0 Read/Write R/W The SCR is an 8-bit readable/writable register that enables or disables various SCI functions initialized to H' reset and in the standby modes. ...
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Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TxD pin is automatically used for output. When the transmit function is disabled, the TxD pin can be used as a ...
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Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data are received in a multiprocessor format, this bit enables or disables the receive-end interrupt (RxI) and receive-error interrupt (ERI) until data with the multiprocessor bit set to “1” are received. It also ...
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Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set to “1.” Bit 2 TEIE Description 0 The TSR-empty interrupt request (TEI) ...
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Serial Status Register (SSR)—H'FFDC Bit 7 TDRE Initial value 1 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Software can write a “0” to clear the flags, but cannot write a “1” in these bits. The SSR is an ...
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Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5 ORER Description 0 To clear ORER, the CPU must read ORER after it has been set to “1,” then write a “0” in this bit. 1 ...
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Bit 2—Transmit End (TEND): This bit indicates that transmission of a character has ended and the serial communication interface has stopped transmitting because there is no valid data in the TDR. The TEND bit is also set to “1” when ...
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Bit Rate Register (BRR)—H'FFD9 Bit 7 Initial value 1 Read/Write R/W The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the baud rate output by the baud rate generator. The ...
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Table 8-3. Examples of BRR Settings in Asynchronous Mode (2) 4.9152 Bit Error rate n N (%) 110 1 174 –0.26 150 1 127 0 300 0 255 0 600 0 127 0 1200 2400 0 31 ...
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Table 8-3. Examples of BRR Settings in Asynchronous Mode (4) 14.7456 Bit Error rate n N (%) 110 2 130 –0.07 150 300 1 191 0 600 1200 0 191 0 2400 0 95 ...
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Table 8-4. Examples of BRR Settings in Synchronous Mode Bit 2 rate 100 — — — 250 1 249 2 500 1 124 249 1 2. 10k ...
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Serial/Timer Control Register (STCR)—H'FFC3 Bit 7 — Initial value 1 Read/Write — The STCR is an 8-bit readable/writable register that controls the operating mode of the serial communication interface and selects input clock sources for the 8-bit timer counters ...
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Operation 8.3.1 Overview The SCI supports serial data transfer in two modes. In asynchronous mode each character is synchronized individually. In synchronous mode communication is synchronized with a clock signal. The selection of asynchronous or synchronous mode and the ...
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Table 8-5. Communication Formats Used by SCI SMR settings Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR — — — — Table ...
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Asynchronous Mode In asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double ...
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Table 8-7. Data Formats in Asynchronous Mode SMR Bits CHR PE MP STOP ...
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D0 D1 Figure 8-3. Phase Relationship between Clock Output and Transmit Data (3) Transmitting and Receiving Data • SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to “0” in the serial control register ...
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Initialization Clear TE and RE bits to “0” in SCR 1 Select communication format in SMR 2 Set value in BRR 3 Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to “0” bit interval ...
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Transmitting Serial Data: Follow the procedure below for transmitting serial data. 1 Initialize Start transmitting 2 Read TDRE bit in SSR No TDRE = “1”? Yes Write transmit data in TDR If using multiprocessor format, select MPBT value in ...
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In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data ...
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Figure 8-6 shows an example of SCI transmit operation in asynchronous mode. Start bit “1” “0” D0 TDRE TEND TXI TXI interrupt handler request writes data in TDR and clears TDRE to “0” Figure 8-6. Example of SCI Transmit Operation ...
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Receiving Serial Data: Follow the procedure below for receiving serial data. 1 Initialize Start receiving 2 Read RDRF bit in SSR No RDRF = “1”? Yes Read receive data from RDR, and clear RDRF bit to “0” in SSR ...
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In receiving, the SCI operates as follows. 1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit. 2. Receive data are shifted into RSR in order from LSB to MSB. 3. The parity ...
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Figure 8-8 shows an example of SCI receive operation in asynchronous mode. Table 8-8. Receive Error Conditions and SCI Operation Receive error Abbreviation Overrun error ORER Framing error FER Parity error PER Start bit “1” “0” D0 RDRF FER Figure ...