MT28F640J3RG-115 Micron Semiconductor Products, MT28F640J3RG-115 Datasheet
MT28F640J3RG-115
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MT28F640J3RG-115 Summary of contents
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... TSOP Type I • 64-ball (standard) FBGA (1.00mm pitch) • 64-ball (lead-free) FBGA (1.00mm pitch) Manufacturer’s Identification Code (ManID) • Micron (0x2Ch) • Intel (0x89h) MT28F640J3RG-115ET 1 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Mark Part Number Example: ©2000 Micron Technology, Inc. ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Power-Up/Down Protection ...
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List of Figures Figure 1: 56-Pin TSOP Type ...
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List of Tables Table 1: Pin/Ball Descriptions ...
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General Description The MT28F128J3 is a nonvolatile, electrically block- erasable (Flash), programmable memory containing 134,217,728 bits organized as 16,777,218 bytes (8 bits) or 8,388,608 words (16 bits). This 128Mb device is organized as one hundred twenty-eight 128KB erase blocks. The ...
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Figure 3: Pin and Ball Assignment Diagrams 56-Pin TSOP Type I A22 1 CE1 2 A21 3 A20 4 A19 5 A18 6 A17 7 A16 A15 10 A14 11 A13 12 A12 13 CE0 14 ...
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Part Numbering Information Micron’s Flash devices are available with several different combinations of features (see Figure 4). Micron Technology Flash Family 28F = Dual-Supply Density/Organization XXX = x8/x16 selectable (XXX = 320, 640, 128) Voltage/Block Organization J3 = Smart 3 ...
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I/O Control Logic A[MAX:0] CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN DENSITY A (MAX) n 128Mb A23 127 64Mb A22 63 32Mb A21 31 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN ...
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Table 1: Pin/Ball Descriptions 56-PIN TSOP 64-BALL FBGA NUMBERS NUMBERS B4, B8 32, 28, 27, 26, G2, A1, B1, C1, 25, 24, 23, 22, D1, D2, A2, C2, 20, 19, ...
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Memory Architecture The MT28F128J3, MT28F640J3, and MT28F320J3 memory array architecture is divided into one hun- dred twenty-eight, sixty-four, or thirty-two 128KB blocks, respectively (see Figure 6). The internal archi- tecture allows greater flexibility when updating data because individual code portions ...
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The command execution logic (CEL) is reset to the read array mode and the status register is set to 80h. During block erase, program, or lock bit configura- tion, RP# LOW aborts the operation. ...
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Bus Operation All bus cycles to and from the Flash memory must conform to the standard microprocessor bus cycles. The local CPU reads and writes Flash memory in-system. Table 3: Bus Operations CE0, CE1, MODE RP# V Read Array IH ...
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Command Definitions When the Vpen voltage is < Vpenlk, only READ operations from the status register, query, identifier codes, or blocks are enabled. Placing Vpenh on Vpen enables BLOCK ERASE, PROGRAM, and LOCK BIT Table 4: Micron Q-Flash Memory Command ...
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NOTE: 1. Commands other than those shown in Table 4 on page 14 are reserved for future device implementations and should not be used. 2. The SCS is also referred to as the extended command set. 3. Bus operations are ...
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READ ARRAY Command The device defaults to read array mode upon initial device power-up and after exiting reset/power-down mode. The read configuration register defaults to asynchronous read page mode. Until another com- mand is written, the READ ARRAY command also ...
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Query Structure Overview The QUERY command makes the Flash component display the CFI query structure or data base. The struc- ture subsections and address locations are outlined in Table 7. Table 6: Example: Query Structure Output of x16- and x8-Capable ...
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CFI Query Identification String The CFI query identification string verifies whether the component supports the CFI specification. Addi- tionally, it indicates the specification version and sup- ported vendor-specified command set(s). Table 8: Block Status Register OFFSET LENGTH DESCRIPTION 1 Block ...
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System Interface Information Table 10 provides useful information about opti- mizing system interface software. Table 10: System Interface Information OFFSET LENGTH DESCRIPTION 1Bh 1 V logic supply minimum program/erase voltage CC Bits 0–3 BCD 100mV Bits 4–7 BCD volts 1Ch ...
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Device Geometry Definition Tables 11 and 12 provide important details about the device geometry. Table 11: Device Geometry Definitions OFFSET LENGTH 27h 1 “n” such that device size= 2 28h 2 Flash device interface: x8 async, x16 async, x8/x16 async; ...
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Primary Vendor-Specific Extended- Query Table Table 13 includes information about optional Flash features and commands and other similar information. Table 13: Primary Vendor-Specific Extended-Query 1 OFFSET DESCRIPTION P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS) (P+0)h Primary extended query table ...
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Table 14: Protection Register Information 1 OFFSET DESCRIPTION P = 31h (Optional Flash Features and Commands) (P+E)h Number of protection register fields in JEDEC ID space. “00h” indicates that 256 protection bytes are available. (P+F)h Protection Field 1: Protection Description ...
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READ IDENTIFIER CODES Command Writing the READ IDENTIFIER CODES command initiates the IDENTIFIER CODE operation. Following the writing of the command, READ cycles from addresses shown in Figure 7 on page 12 retrieve the manufacturer, device, and block lock configuration ...
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Table 17: Status Register Definitions ISMS ESS 7 6 HIGH-Z WHEN BUSY? STATUS REGISTER BITS No SR7 = WRITE STATE MACHINE STATUS (ISMS Ready 0 = Busy Yes SR6 = ERASE SUSPEND STATUS (ESS Block Erase ...
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CLEAR STATUS REGISTER Command The ISM sets the status register bits SR5, SR4, SR3, and SR1 to “1s.” These bits, which indicate various fail- ure conditions, can only be reset by the CLEAR STA- TUS REGISTER command. Allowing system software ...
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WRITE-to-BUFFER Command The write-to-buffer command sequence is initiated to program the Flash device via the write buffer. A buffer can be loaded with a variable number of bytes the buffer size, before writing to the Flash device. First, ...
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BYTE/WORD PROGRAM Commands A two-cycle command sequence executes a byte/ word program setup. This program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of ...
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Table 19: Configuration Coding Definitions DQ7 DQ6 DQ1–DQ0 = STS Configuration Codes 00 = Default, RY/BY# level mode (device ready) indication 01 = Pulse on Erase Complete 10 = Pulse on Program Complete 11 = Pulse on Erase or Program ...
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To initialize block lock bit contents to known values, a repeat of CLEAR BLOCK LOCK BITS is required. PROTECTION REGISTER PROGRAM Command The 3V Q-Flash memory includes a 128-bit protec- tion register to increase ...
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Table 20: Word-Wide Protection Register Addressing WORD USE LOCK Both 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Table 21: Byte-Wide Protection Register Addressing BYTE USE A8 LOCK Both 1 0 Factory ...
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Figure 9: WRITE-to-BUFFER Flowchart Start Set Timeout Issue No WRITE-to-BUFFER Command E8h, Block Address Read Extended Status Register WRITE-to- 0 XSR7 = BUFFER Timeout? 1 Write Word or Byte Count N, Block Address Write Buffer Data, Start Address X = ...
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Figure 10: BYTE/WORD PROGRAM Flowchart Start Write 40h, Address Write Data and Address Read Status Register 0 SR7 = 1 Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (see above) 1 Voltage ...
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Figure 11: PROGRAM SUSPEND/RESUME Flowchart Start Write B0h Read Status Register 0 SR7 = 1 0 SR2 = 1 Write FFh Read Data Array 1 No Done Reading Yes Write D0h Programming Resumed 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN ...
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Figure 12: BLOCK ERASE Flowchart Start Issue Single BLOCK ERASE Command 20h, Block Address Write Confirm D0h Block Address Read Status Register No SR7 = Suspend Erase 1 Full Status Check if Desired Erase Flash Block(s) Complete 09005aef80b5a323 MT28F640J3.fm – ...
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Figure 13: BLOCK ERASE SUSPEND/ RESUME Flowchart Start Write B0h Read Status Register 0 SR7 = 1 0 SR6 = 1 Read Read or Program Program? Read Array Program No Data Loop Done? Yes Write D0h BLOCK ERASE Resumed 09005aef80b5a323 ...
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Figure 14: SET BLOCK LOCK BITS Flowchart Start Write 60h, Block Address Write 01h, Block Address Read Status Register 0 SR7 = 1 Full Status Check if Desired SET BLOCK LOCK BITs Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Figure 15: CLEAR BLOCK LOCK BITS Flowchart Start Write 60h Write D0h Read Status Register 0 SR7 = 1 Full Status Check if Desired CLEAR BLOCK LOCK BITS Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (see above) 1 ...
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Figure 16: PROTECTION REGISTER PROGRAMMING Flowchart Start Write C0h (Protection Register Program Setup) Write Protect Register Address/Data Read Status Register No SR7 = 1 Yes Full Status Check if Desired PROGRAM Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...
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Design Considerations Five-Line Output Control Micron provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections in large memory arrays. This control pro- vides the lowest possible memory power dissipation and ensures that data bus ...
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After block erase, program, or lock bit configura- tion, and after V transitions to V PEN must be placed in read array mode via the READ ARRAY command if subsequent access to the memory array is desired. During V transitions, ...
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Electrical Specificatons Table 22: Absolute Maximum Ratings Note 1 VOLTAGE Temperature under bias expanded Storage Temperature For +2.7V to +3.6V CC Voltage on any pin Short Circuit Output Current NOTE: 1. Stresses greater than those listed in ...
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Table 23: Temperature and Recommended DC Operating Conditions Extended temperature (-40ºC ≤ T ≤ +85ºC) A PARAMATER V Supply Voltage (2.7V–3.6V Supply Voltage (2.7V–3.6V) CC Input and V Load Current PEN (MAX ...
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Table 25: Recommended DC Electrical Characteristics Notes appear on page 44; extended temperature (-40ºC ≤ T DESCRIPTION V Standby Current CC Device is enabled; RP TTL inputs Power-Down Current RP# = GND ±0.2V ...
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Table 25: Recommended DC Electrical Characteristics Notes appear on page 44; extended temperature (-40ºC ≤ T DESCRIPTION V Lockout during PEN PROGRAM, ERASE, and LOCK BIT Operations V during BLOCK ERASE, PEN PROGRAM, or LOCK BIT Operations V Lockout Voltage ...
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Figure 18: Transient Equivalent Test Load Circuit NOTE: C includes jig capacitance. L Table 26: Test Configuration Loading Value TEST CONFIGURATION 2.7V – 3. Table 27: AC Characteristics–Read-Only Operations Notes ...
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Table 27: AC Characteristics–Read-Only Operations Notes extended temperature (-40ºC ≤ T PARAMETER CEx HIGH to CEx LOW Page Address Access Time NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that ...
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Figure 19: Page Mode and Standard Word/Byte READ Operations V IH ADDRESSES V (A22–A3 ADDRESSES V (A2–A0) V Disabled IH 1 CEx V Enabled DQ0–DQ15 ...
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Table 28: AC Characteristics – WRITE Operations Notes extended temperature (-40ºC ≤ T PARAMETER RP# High Recovery to WE# (CEx) Going LOW CEx (WE#) LOW to WE# (CEx) Going LOW Write Pulse Width Data Setup to WE# ...
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Table 29: Block Erase, Program, and Lock Bit Configuration Performance Notes extended temperature (-40ºC ≤ T PARAMETER Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) Byte/Word Program Time (Using WORD/BYTE PROGRAM Command) Block Program ...
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Note Addresses Disabled V CEx (WE#) IL Enabled OE Disabled IH WE# (CEx) V Enabled DQ0–DQ15 STS V OL ...
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Table 30: RESET Specifications Note 1; extended temperature (-40ºC ≤ T PARAMETER RP# Pulse Low Time (If RP# is tied this specification is not applicable) CC RP# High to Reset during Block Erase, Program, or Lock Bit ...
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PIN #1 INDEX +0.03 0.15 -0.02 NOTE: 1. All dimensions in millimeters. 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN Figure 22: 56-Pin TSOP Type 1 20.00 ±0.25 18.40 ±0.08 14.00 ±0.08 SEE DETAIL A 1.20 MAX Micron Technology, Inc., reserves ...
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SEATING PLANE C 0.10 C BALL A8 1.00 TYP 64X ∅0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.40 7.00 3.50 ±0.05 3.50 ±0.05 10.00 ±0.10 NOTE: All dimensions in millimeters. ...
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Revision History Rev. N................................................................................................................................................................................3/05 • Removed all references to 256Mb Q-Flash Rev. M ...............................................................................................................................................................................9/04 • Clarified byte capacitance (page 42) • Updated I 3 currents (page 43) CC Rev. L.................................................................................................................................................................................4/04 • Corrected Maximun Voltage Range on VccQ in Table 22 ...
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Added 4.5V–5.5V parameter for 32Mb and 64Mb devices CC • Updated erase and program timing parameters • Removed Block Erase Status bit Rev. 3.................................................................................................................................................................................6/01 • Updated package drawing and corresponding notes Rev. 2.................................................................................................................................................................................5/01 • Added 128Mb ...