MT46V16M16TG-75 Micron Semiconductor Products, MT46V16M16TG-75 Datasheet
MT46V16M16TG-75
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MT46V16M16TG-75 Summary of contents
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Double Data Rate (DDR) SDRAM MT46V64M4 – 16 Meg banks MT46V32M8 – 8 Meg banks MT46V16M16 – 4 Meg banks Features • +2.5V ±0.2V ...
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... Rev. L 6/06 EN PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) Yes Yes Yes Yes Yes Yes – Yes – – – – -6/-6T -75E Example Part Number: MT46V16M16TG- 75E - Sp. Configuration Package Speed Op. Temp. 64M4 32M8 16M16 Package 400-mil TSOP TG 400-mil TSOP (lead-free 8x14 FBGA ...
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General Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory con- taining 268,435,456 bits internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 256Mb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 2: Functional Block Diagram: 64 Meg x 4 CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH 13 MODE REGISTERS COUNTER ROW- ADDRESS MUX A0-A12, ADDRESS 15 BA0, BA1 REGISTER 2 11 PDF: 09005aef80768abb/Source: 09005aef8076894f ...
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Figure 3: Functional Block Diagram: 32 Meg x 8 CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH 13 COUNTER MODE REGISTERS ROW- ADDRESS MUX A0-A12, ADDRESS 15 BA0, BA1 REGISTER 2 10 PDF: 09005aef80768abb/Source: 09005aef8076894f ...
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Figure 4: Functional Block Diagram: 16 Meg x 16 CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER 13 MODE REGISTERS ROW- ADDRESS MUX A0-A12, ADDRESS 15 BA0, BA1 REGISTER 2 9 PDF: 09005aef80768abb/Source: 09005aef8076894f ...
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Pin/Ball Assignments and Descriptions Table 4: Ball/Pin Descriptions FBGA TSOP Numbers Numbers Symbol G2, G3 45, 46 CK, CK CKE H8 24 CS# H7, G8, G7 23, 22, 21 RAS#, CAS#, WE F7, 3F 20, ...
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Table 4: Ball/Pin Descriptions (Continued) FBGA TSOP Numbers Numbers Symbol A8, B7, C7 DQ0–DQ2 D7, D3, C3, 11, 56, 59, DQ3–DQ5 B3, A2 62, 65 DQ6, DQ7 B1, B9, C1, C9 10, 13, NC D1, ...
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Figure 5: Pin Assignment (Top View) 66-Pin TSOP DQ0 DQ1 ...
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Figure 6: 60-Ball FBGA Ball Assignment (Top View REF REF DQ15 ...
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Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory con- taining 268,435,456 bits. The 256Mb DDR SDRAM is internally configured as a quad- bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed ...
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Register Definition Mode Register The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as ...
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Figure 7: Mode Register Definition BA1 BA0 M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). PDF: 09005aef80768abb/Source: 09005aef8076894f 256MBDDRx4x8x16_2.fm - Rev. L ...
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Table 6: Burst Definition Burst Length Notes: 1. Whenever a boundary of the block is reached within a given sequence above, the follow- ing access wraps within the block. 2. For a burst length of two, A1 ...
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Figure 8: CAS Latency CK# CK COMMAND DQS DQ CK# CK COMMAND DQS DQ CK# CK COMMAND DQS DQ Table 7: CAS Latency (CL) Speed -5B -6/-6T -75E -75Z -75 PDF: 09005aef80768abb/Source: 09005aef8076894f 256MBDDRx4x8x16_2.fm - Rev. L 6/06 EN 256Mb: ...
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Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A12 each set to zero and bits A0–A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER ...
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Figure 9: Extended Mode Register Definition BA1 BA0 A12 E12 E11 E10 – – – Notes: 1. E14 and E13 (BA1 and BA0) must be “0, 1” to select the ...
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Commands Table 8 and Table 9 provide a quick reference of available commands, followed by a description of each command. Two additional truth tables, Table 11 on page 49, and Table 12 on page 51, appear following the Operation section, ...
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DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to ...
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Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. Otherwise, BA0, BA1 are treated as ...
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SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. ...
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Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and ...
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Figure 11: Example: Meeting T0 T1 CK# CK COMMAND ACT NOP A0–A12 Row BA0, BA1 Bank x t RRD PDF: 09005aef80768abb/Source: 09005aef8076894f 256MBDDRx4x8x16_2.fm - Rev RCD ( RRD) MIN When 2 < RCD ( ...
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READs READ bursts are initiated with a READ command, as shown in Figure 12 on page 28. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst ...
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Figure 12: READ Command x4: A0–A9, A11 x8: A0–A9 x16: A0–A8 x8: A11, A12 x16: A9, A11, A12 PDF: 09005aef80768abb/Source: 09005aef8076894f 256MBDDRx4x8x16_2.fm - Rev. L 6/06 EN CK# CK CKE HIGH CS# RAS# CAS# WE# CA x4: A12 EN AP ...
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Figure 13: READ Burst T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ ...
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Figure 14: Consecutive READ Bursts T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n ...
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Figure 15: Nonconsecutive READ Bursts T0 CK# CK COMMAND READ Bank, ADDRESS Col DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ...
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Figure 16: Random READ Accesses T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n ...
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Figure 17: Terminating a READ Burst T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n ...
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Figure 18: READ-to-WRITE T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS CK# CK COMMAND READ Bank a, ADDRESS Col n DQS CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ ...
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Figure 19: READ-to-PRECHARGE T0 CK# CK COMMAND 6 READ Bank a, ADDRESS Col n DQS COMMAND READ Bank a, ADDRESS Col n DQS COMMAND READ Bank a, ADDRESS Col n ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 20. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge ...
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Figure 20: WRITE Command RAS# CAS# WE# x4: A0–A9, A11 x8: A0–A9 x16: A0–A8 x4: A12 x8: A11, A12 x16: A9, A11, A12 BA0, 1 DON’T CARE Data for any WRITE burst may be followed by a subsequent READ command. ...
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Figure 21: WRITE Burst CK# CK COMMAND ADDRESS t DQSS (NOM) DQS DQSS (MIN) DQS DQSS (MAX) DQS DQ DM Notes data-in for column b. 2. Three subsequent elements of ...
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Figure 22: Consecutive WRITE-to-WRITE T0 CK# CK COMMAND WRITE Bank, ADDRESS Col DQSS (NOM) DQSS DQS DQ DM Notes etc., = data-in for column b, etc. 2. Three subsequent elements of data-in are applied ...
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Figure 23: Nonconsecutive WRITE-to-WRITE T0 CK# CK COMMAND WRITE Bank, ADDRESS Col DQSS (NOM) DQSS DQS DQ DM Notes etc., = data-in for column b, etc. 2. Three subsequent elements of data-in are applied ...
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Figure 25: WRITE-to-READ – Uninterrupting T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS ...
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Figure 26: WRITE-to-READ – Interrupting T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS ...
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Figure 27: WRITE to READ – Odd Number of Data, Interrupting T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DI ...
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Figure 28: WRITE-to-PRECHARGE – Uninterrupting T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS ...
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Figure 29: WRITE-to-PRECHARGE – Interrupting T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS ...
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Figure 30: WRITE-to-PRECHARGE – Odd Number of Data – Interrupting T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DI DQ ...
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PRECHARGE The PRECHARGE command, as shown in Figure 31, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subse- quent row access some specified ...
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Exiting power-down requires the device the same voltage and frequency as when it entered power-down. However, power-down duration is limited by the refresh requirements of the device ( While in power-down, CKE LOW and ...
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Table 11: Truth Table – Current State Bank n – Command-to-Bank n Notes: 1–6; notes appear below and on next page. Current State CS# RAS# CAS# Any Idle ...
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Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when banks idle state. • Precharging All: Starts with registration of a PRECHARGE ALL command and ends when met. Once 6. All ...
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Table 12: Truth Table – Current State Bank n – Command-to-Bank m Notes: 1–6; notes appear below and on next page. Current State CS# RAS# CAS Any Idle Row L L ...
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This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled any command to other banks is allowed, as long as that command does not inter- rupt ...
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Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections ...
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Table 15: DC Electrical Characteristics and Operating Conditions (-5B DDR400) 0°C ≤ T ≤ +70° +2.6V ±0.1V Parameter/Condition Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) ...
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Table 16: AC Input Operating Conditions 0°C ≤ T ≤ +70° +2.5V ±0.2V DDR400); notes: 1–5, 14, 16; notes appear on pages 69–74. Parameter/Condition Input High (Logic 1) Voltage Input Low (Logic 0) Voltage ...
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Table 17: Clock Input Operating Conditions 0°C ≤ T ≤ +70° +2.5V ±0.2V DDR400); notes: 1–5, 15, 16, 30; notes appear on pages 69–74. Parameter/Condition Clock Input Midpoint Voltage; CK and CK# Clock Input ...
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Table 18: Capacitance (x4, x8 TSOP) Note: 13; notes appear on pages 69–74. Parameter Delta Input/Output Capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command ...
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Table 20: I Specifications and Conditions (x4, x8; -5B) DD 0°C ≤ T ≤ +70° +2.6V ±0.1V pages 69–74; see also Table 26, “Idd Test Cycle Times,” on page 64. Parameter/condition OPERATING CURRENT: One ...
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Table 21: I Specifications and Conditions (x4, x8; -6/-6T/-75E) DD 0°C ≤ T ≤ +70° +2.5V ±0.2V pages 69–74; see also Table 26, “Idd Test Cycle Times,” on page 64. Parameter/Condition OPERATING CURRENT: One ...
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Table 22: I Specifications and Conditions (x4, x8; -75Z/-75) DD 0°C ≤ T ≤ +70° +2.5V ±0.2V pages 69–74; see also Table 26, “Idd Test Cycle Times,” on page 64. Parameter/Condition OPERATING CURRENT: One ...
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Table 23: I Specifications and Conditions (x16; -5B) DD 0°C ≤ T ≤ +70° +2.6V ±0.1V pages 69–74; see also Table 26, “Idd Test Cycle Times,” on page 64. Parameter/Condition OPERATING CURRENT: One bank; ...
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Table 24: I Specifications and Conditions (x16; -6/-6T/-75E) DD 0°C ≤ T ≤ +70° +2.5V ±0.2V pages 69–74; see also Table 26, “Idd Test Cycle Times,” on page 64. Parameter/Condition OPERATING CURRENT: One bank; ...
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Table 25: I Specifications and Conditions (x16; -75Z/-75) DD 0°C ≤ T ≤ +70° +2.5V ±0.2V Notes: 1–5, 10, 12, 14, 46; notes appear on pages 69–74; see also Table 26, “Idd Test Cycle ...
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Table 26: I Test Cycle Times DD Values reflect number of clock cycles for each test. Speed Clock Cycle I Test Grade Time -75/75Z 7.5ns DD -75E 7.5ns -6/-6T 6ns -5B 5ns I 1 -75 7.5ns DD ...
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Table 27: Electrical Characteristics and Recommended AC Operating Conditions (-5B) Notes: 1–5, 14–17, 33; notes on pages 69–74; 0°C ≤ Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time DQ ...
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Table 28: Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E) Notes: 1–5, 14–17, 33; notes appear on pages 69–74; 0°C ≤ Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time ...
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Table 29: Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75) Notes: 1–5, 14–17, 33; notes appear on pages 69–74; 0°C ≤ Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time ...
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Table 30: Input Slew Rate Derating Values for Addresses and Commands 0°C ≤ T ≤ +70° +2.5V ±0.2V Speed 0.50 V/ns ≤ Slew Rate < 1.0 V/ns -75/-75Z/-75E 0.40 V/ns ≤ Slew Rate < ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs (except for I V Output ...
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Inputs are not recognized as valid until V self-refresh mode, V ing the period before V 17. The output timing reference level, as measured at the timing reference point indi- cated in Note 18. HZ ...
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Figure 35: Derating Data Valid Window ( Examples are for speed grades through -75. 3.8 3.750 3.700 3.6 3.650 3.400 3.350 3.4 3.300 3.2 t —— - 10ns 3.0 t —— 10ns t ...
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The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 36. c. The full variation in driver pull-up ...
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Reduced output drive curves: a. The full variation in driver pull-down current from minimum to maximum pro- cess, temperature, and voltage will lie within the outer bounding lines of the V-I curve of Figure 38. b. The variation in ...
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The voltage levels used are derived from a minimum test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. V overshoot width can not be greater than ...
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Output Drive Characteristics Table 32: Normal Output Drive Characteristics Pull-Down CurrenT (mA) Voltage Nominal Nominal (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 ...
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Table 33: Reduced Output Drive Characteristics Pull-Down CurrenT (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.9 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 ...
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Data Output Timing Diagrams Figure 40: x4, x8 Data Output Timing – DQS DQ (Last data valid (First data no longer valid) DQ ...
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Figure 41: x16 Data Output Timing – LDQS DQ (Last data valid (First data no longer valid (Last data valid) ...
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Figure 42: Data Output Timing – CK (MIN) 2 DQS, or LDQS/UDQS DQ (Last data valid) DQ (First data valid) 3 All DQ values, collectively t Notes: 1. DQSCK is the DQS output window relative ...
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Figure 43: Data Input Timing CK# CK DQS Notes: 1. DSH (MIN) generally occurs during t 2. DSS (MIN) generally occurs during 3. WRITE command issued at T0. 4. For x16, LDQS controls the lower byte and ...
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Initialization To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power Apply V 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at ...
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Figure 44: Initialization Flow Diagram Step Bring CKE High with a NOP command 7 Assert NOP or DESELECT for t RP time 8 9 Assert NOP or DESELECT for t MRD time 10 11 ...
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Timing Diagrams Figure 45: Initialize and Load Mode Registers ( ( ) ) VTD ( ( ) ) REF ) ) T0 CK# ...
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Figure 46: Power-Down Mode T0 CK CKE VALID 2 COMMAND ADDR VALID DQS DQ DM Power-Down Notes: 1. Once initialized this ...
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Figure 47: Auto Refresh Mode CKE COMMAND NOP 2 PRE A0-A9, 1 A11, A12 ALL BANKS 1 A10 ONE BANK Bank(s) ...
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Figure 48: Self Refresh Mode CK CKE COMMAND NOP AR ADDR DQS Enter Self Refresh ...
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Figure 49: Bank Read – Without Auto Precharge CKE NOP 6 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 ...
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Figure 50: Bank Read – With Auto Precharge CKE NOP 5 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 ...
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Figure 51: Bank Write – Without Auto Precharge CKE NOP 6 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 ...
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Figure 52: Bank Write – With Auto Precharge CKE NOP 5 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 ...
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Figure 53: Write – DM Operation CKE NOP 6 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 x4: A12 ...
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Package Drawings Figure 54: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ±0.075 TYP PIN #1 ID Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is ...
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Figure 55: 60-Ball FBGA (8 x 14mm) 0.850 ±0.075 SEATING PLANE C 0.10 C 6.40 60X ∅0.45 0.80 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.40 BALL A9 11.00 5.50 ±0.05 C ...