MT46V32M16TG-5B Micron Semiconductor Products, MT46V32M16TG-5B Datasheet
MT46V32M16TG-5B
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MT46V32M16TG-5B Summary of contents
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Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg Banks MT46V64M8 – 16 Meg Banks MT46V32M16 – 8 Meg Banks Features • +2.5V ±0.2V ...
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Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) Yes -5B – -6 – -6T – -75E – ...
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Table of Contents State Diagram ...
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State Diagram Figure 2: Simplified State Diagram Power applied Note: This diagram represents operations within a single bank only and does not capture concur- rent operations in other banks. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - 512Mb DDR: Rev. L; Core DDR ...
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Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an inter- face designed to transfer two data words per clock cycle at the ...
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Functional Block Diagrams The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a 4-bank DRAM. Figure 3: 128 Meg x 4 Functional Block Diagram CKE CK# CK CONTROL CS# LOGIC ...
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Figure 4: 64 Meg x 8 Functional Block Diagram CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# MODE REGISTERS 15 A0–A12, ADDRESS 15 BA0, BA1 REGISTER Figure 5: 32 Meg x 16 Functional Block Diagram CKE CK# CK CS# ...
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Pin and Ball Assignments and Descriptions Figure 6: 66-Pin TSOP Pin Assignment (Top View DQ0 DQ1 ...
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Figure 7: 60-Ball FBGA Ball Assignment (Top View REF REF DQ14 DQ12 DQ10 DQ8 V REF PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a 512Mb_DDR_x4x8x16_D2.fm - ...
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Table 4: Pin and Ball Descriptions FBGA TSOP Numbers Numbers Symbol K7, L8, L7, 29, 30, 31, A0, A1, A2, M8, M2, L3, 32, 35, 36, A3, A4, A5, L2, K3, K2, 37, 38, 39, A6, A7, A8, J3, K8, ...
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Table 4: Pin and Ball Descriptions (continued) FBGA TSOP Numbers Numbers Symbol E3 51 DQS E7 16 LDQS E3 51 UDQS V F8 B2, D2, C8 15, 55, DD E8, ...
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Package Dimensions Figure 8: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ± .075 TYP PIN #1 ID Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold ...
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Figure 9: 60-Ball FBGA (10mm x 12.5mm) 0.85 ±0.05 SEATING PLANE C 0.10 C .45 60X Ø 0.80 (TYP) SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40. BALL A9 11.00 5.50 ±0.05 3.20 ±0.05 ...
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Electrical Specifications – I Table 6: I Specifications and Conditions (x4, x8 +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 28–33; See also Table 8 ...
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Table 7: I Specifications and Conditions (x16 +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 28–33; See also Table 8 on page 16 A Parameter/Condition ...
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Table 8: I Test Cycle Times DD Values reflect number of clock cycles for each test Speed Clock Cycle I Test Grade Time -75/75Z 7.5ns DD -75E 7.5ns -6/-6T 6ns -5B 5ns I 1 -75 7.5ns DD ...
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Electrical Specifications – DC and AC Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above ...
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Table 11: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) Notes: 1–5, 17 apply to entire table; Notes appear on pages 28–34; V Parameter/Condition Supply voltage I/O supply voltage I/O reference voltage I/O termination voltage (system) Input ...
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Figure 10: Input Voltage Waveform Transmitter Notes Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR ...
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Table 13: Clock Input Operating Conditions 0°C ≤ T ≤ +70° +2.6V ±0.1V Notes: 1–5, 16, 17, 31 apply to entire table; Notes appear on pages 28–34 Parameter/Condition Clock input mid-point voltage: ...
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Table 14: Capacitance (x4, x8 TSOP – 128Mb, 256Mb, 512Mb, 1Gb) Note: 14 applies to entire table; Notes appear on pages 28–34 Parameter Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) Delta input capacitance: Command and address Delta input capacitance: CK, ...
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Table 18: Electrical Characteristics & Recommended AC Operating Conditions (-5B) Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 28–34; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from CK/CK# ...
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Table 18: Electrical Characteristics & Recommended AC Operating Conditions (-5B) (continued) Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 28–34; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup time ...
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Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6, -6T, -75E) Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 28–34; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ ...
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Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6, -6T, -75E) (continued) Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 28–34; AC Characteristics Parameter DQS read postamble ACTIVE bank a to ACTIVE bank b command ...
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Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-75Z, -75) Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 28–34; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-75Z, -75) (continued) Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 28–34; AC Characteristics Parameter PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. Outputs (except for I Output ...
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The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK REF 17. Inputs are not recognized as valid until ...
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CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially). Figure 12: Derating Data Valid Window ( 3.0ns 2.5ns 2.0ns 1.5ns 1.0ns 32. DQ and DM input slew rates must not deviate from DQS ...
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The driver pull-up current variation within nominal limits of voltage and temper- 38e. The full ratio variation of MAX to MIN pull-up and pull-down current should be 38f. The full ratio variation of the nominal pull-up to pull-down current ...
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The driver pull-up current variation, within nominal voltage and temperature 39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should 39f. The full ratio variation of the nominal pull-up to pull-down current should be Figure 15: ...
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RPST end point and but specify when the device output is no longer driving ( t ( RPRE). 45. During initialization, V Alternatively, V provided a minimum of 42Ω of series resistance is used between the V the ...
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Table 23: Normal Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 ...
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Table 24: Reduced Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 ...
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Commands Tables 25 and 26 provide a quick reference of available commands. Two additional Truth Tables—Table 27 on page 37, and Table 28 on page 38— provide current state/next state information. Table 25: Truth Table 1 – Commands CKE is ...
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Table 27: Truth Table 3 – Current State Bank n – Command to Bank n Notes: 1–6 apply to entire table; Notes appear below Current State CS# RAS# CAS Any Idle ...
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Refreshing: Starts with registration of an AUTO REFRESH command and ends when • Accessing mode register: Starts with registration of a LOAD MODE REGISTER command • Precharging all: Starts with registration of a PRECHARGE ALL command and ends when ...
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This table describes alternate bank operation, except where noted (i.e., the current state is for bank n, and the commands shown are those allowed to be issued to bank m, assuming that bank such a state ...
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A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com- mand. Table 30: Truth Table 5 – CKE ...
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ACTIVE (ACT) The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access, like a read or a write, as shown in Figure 17. The value on the BA0, BA1 inputs selects ...
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Figure 18: READ Command CK# CK CKE CS# RAS# CAS# WE# ADDRESS A10 BA0, BA1 Note enable auto precharge; DIS AP = disable auto precharge. WRITE The WRITE command is used to initiate a burst write access ...
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PRECHARGE (PRE) The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks as shown in Figure 20. The value on the BA0, BA1 inputs selects the bank, and the ...
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Operations INITIALIZATION Prior to normal operation, DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures, other than those specified, may result in undefined operation. To ensure device operation, the DRAM must be initialized as described ...
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Figure 21: INITIALIZATION Flow Diagram Step PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A ...
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Figure 22: INITIALIZATION Timing Diagram ( ( ) ) VTD REF ) ) CK ...
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REGISTER DEFINITION Mode Register The mode register is used to define the specific DDR SDRAM mode of operation. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in ...
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Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 23 on page 47. The burst length determines the maximum ...
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CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set (-5B only) ...
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Table 32: CAS Latency Speed 75 ≤ f ≤ 133 -5B 75 ≤ f ≤ 133 -6/-6T 75 ≤ f ≤ 133 -75E 75 ≤ f ≤ 133 -75Z 75 ≤ f ≤ 100 -75 Operating Mode The normal operating ...
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Figure 25: Extended Mode Register Definition Mn Notes the most significant row address bit from Table 2 on page 2. 2. The reduced drive strength option is available only on the x16 version. ...
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Figure 26: Example: Meeting T0 T1 CK# CK COMMAND ACT NOP ADDRESS Row BA0, BA1 Bank x READ During the READ command, the value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, ...
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Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 31 on page 58. The BURST TERMINATE latency is equal to the CL, that is, the BURST TERMINATE command should be issued x ...
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Figure 27: READ Burst CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ Notes data-out from column Three subsequent elements of ...
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Figure 28: Consecutive READ Bursts CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ Notes ( data-out from column n (or column b ...
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Figure 29: Nonconsecutive READ Bursts T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ Notes: 1. ...
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Figure 30: Random READ Accesses CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ Notes ( data-out from column n (or column ...
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Figure 31: Terminating a READ Burst CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ Notes: 1. Page remains open data-out from column ...
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Figure 32: READ-to-WRITE CK# CK COMMAND ADDRESS DQS DQ DM CK# CK COMMAND ADDRESS DQS DQ DM CK# CK COMMAND ADDRESS DQS DQ DM Notes: 1. Page remains open data-out from column ...
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Figure 33: READ-to-PRECHARGE CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ Notes: 1. Provided precharge to be performed at x number of clock cycles after the READ command, where x ...
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Figure 34: Bank READ – Without Auto Precharge CKE NOP ACT COMMAND t IS ADDRESS Row A10 Row t IS BA0, BA1 Bank ...
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Figure 35: x4, x8 Data Output Timing – DQ (first data no longer valid) DQ (first data no longer valid) All DQ and DQS, collectively 6 t Notes the lesser DQSQ is derived at ...
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Figure 36: x16 Data Output Timing – DQ (last data valid (first data no longer valid (last data valid (first data no longer valid) 4 DQ0–DQ7 and LDQS, collectively 6 DQ (last data valid) ...
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Figure 37: Data Output Timing – CK# CK DQS or LDQS/UDQS 3 DQ (last data valid) DQ (first data valid) All DQ values collectively 4 Notes: 1. READ command with issued at T0 DQSCK is ...
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Figure 38 on page 66 shows the nominal case and the extremes of t DQSS for Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and ...
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Figure 38: WRITE Burst COMMAND ADDRESS t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following ...
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Figure 39: Consecutive WRITE-to-WRITE CK# CK COMMAND ADDRESS t DQSS (NOM) DQS DQ DM Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order ...
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Figure 40: Nonconsecutive WRITE-to-WRITE CK# COMMAND ADDRESS t DQSS (NOM) DQS DQ DM Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order following ...
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Figure 42: WRITE-to-READ – Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 43: WRITE-to-READ – Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 44: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 45: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 46: WRITE-to-PRECHARGE – Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 47: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 48: Bank WRITE – Without Auto Precharge CKE NOP 1 COMMAND ACT Row ADDRESS A10 Row BA0, ...
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Figure 49: WRITE – DM Operation CKE COMMAND NOP ACT ADDRESS Row A10 Row BA0, BA1 Bank ...
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Figure 50: Data Input Timing CK# CK DQS DQ DM Notes: 1. WRITE command issued at T0 DSH (MIN) generally occurs during t 3. DSS (MIN) generally occurs during 4. For x16, LDQS controls the lower byte and ...
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Figure 51: Bank READ – with Auto Precharge CKE NOP ACT COMMAND ADDRESS Row A10 Row IS IH BA0, BA1 Bank x DM ...
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Figure 52: Bank WRITE – with Auto Precharge CKE COMMAND NOP ACT ADDRESS Row A10 Row BA0, ...
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Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends Figure 53: Auto Refresh Mode ...
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NOPs for 200 additional clock cycles before applying a READ. Any command other than a READ can be performed reset. NOP or DESELECT commands must be issued during the Figure 54: Self Refresh Mode 1 ...
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POWER-DOWN (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend ...
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Figure 55: Power-Down Mode T0 CK CKE t IS VALID 2 COMMAND t IS ADDRESS VALID DQS DQ DM Notes: 1. Once initialized this command is a PRECHARGE (or if the device is ...