MT58L64L32F Micron Semiconductor Products, MT58L64L32F Datasheet

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MT58L64L32F

Manufacturer Part Number
MT58L64L32F
Description
Manufacturer
Micron Semiconductor Products
Datasheet

Specifications of MT58L64L32F

Case
QFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT58L64L32F-7.5A
Quantity:
29
Part Number:
MT58L64L32FT-8.5
Manufacturer:
NS
Quantity:
9
2Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
• Separate +3.3V or +2.5V isolated output buffer
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
• Three chip enables for simple depth expansion and
• Clock-controlled and registered addresses, data
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Packages
• Operating Temperature Range
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 6/01
supply (V
WRITE
address pipelining
I/Os and control signals
6.8ns/8.0ns/125 MHz
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
3.3V I/O
2.5V I/O
100-pin TQFP
Commercial (0°C to +70°C)
128K x 18
128K x 18
64K x 32
64K x 36
64K x 32
64K x 36
DD
Q)
MT58L64L36FT-8.5
Part Number Example:
MT58L128V18F
MT58L128L18F
MT58L64V32F
MT58L64V36F
MT58L64L32F
MT58L64L36F
MARKING
None
-6.8
-7.5
-8.5
-10
T
DD
)
FLOW-THROUGH SYNCBURST SRAM
1
MT58L128L18F, MT58L64L32F,
MT58L64L36F; MT58L128V18F,
MT58L64V32F, MT58L64V36F
3.3V V
GENERAL DESCRIPTION
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#).
(OE#), snooze enable (ZZ) and clock (CLK). There is also
a burst mode pin (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
**JEDEC-standard MS-026 BHA (LQFP).
The Micron
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
Asynchronous inputs include the output enable
Burst operation can be initiated with either address
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2Mb: 128K x 18, 64K x 32/36
DD
, 3.3V or 2.5V I/O, Flow-Through
®
100-Pin TQFP**
SyncBurst
SRAM family employs
©2000, Micron Technology, Inc.

Related parts for MT58L64L32F

MT58L64L32F Summary of contents

Page 1

... Operating Temperature Range Commercial (0°C to +70°C) Part Number Example: MT58L64L36FT-8.5 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM ™ MT58L128L18F, MT58L64L32F, MT58L64L36F; MT58L128V18F, MT58L64V32F, MT58L64V36F 3. **JEDEC-standard MS-026 BHA (LQFP). GENERAL DESCRIPTION ...

Page 2

ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 16 SA0, SA1, SA MODE ADV# CLK ADSC# ADSP# BYTE “d” ...

Page 3

GENERAL DESCRIPTION (continued) Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins and ...

Page 4

ADV# 83 ADSP# 84 ADSC# 85 OE# 86 BWE# 87 GW# 88 CLK CE2# 92 BWa# 93 BWb CE2 97 CE ...

Page 5

TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32-35, 44-49, 32-35, 44-49, 80-82, 99, 81, 82, 99, 100 100 93 93 BWa BWb# – 95 BWc# – 96 BWd BWE GW# 89 ...

Page 6

TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 85 85 ADSC MODE 64 64 (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72 12, (b) 68, 69, 13, 18, 19, ...

Page 7

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 PARTIAL TRUTH TABLE FOR ...

Page 8

TRUTH TABLE OPERATION ADDRESS CE# CE2# CE2 ZZ Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, ...

Page 9

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V .................................... -0.5V to +4.6V SS Voltage Supply DD Relative to V .................................... -0.5V to +4. ............................................... -0. Storage Temperature (plastic) ............ ...

Page 10

I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note: 1) (0°C ≤ T ≤ +70° DESCRIPTION Device selected; All inputs ≤ V Power Supply Cycle time ≥ Current: Operating V = MAX; Outputs open DD Power Supply Device ...

Page 11

TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) NOTE: 1. This parameter is ...

Page 12

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C ≤ T ≤ +70° +3.3V +0.3V/-0.165V DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock ...

Page 13

I/O AC TEST CONDITIONS Input pulse levels ................. V .................... V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... V Output reference levels ............................ V Output load ............................. See Figures 1 and 2 3.3V I/O ...

Page 14

SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time the ZZ pin ...

Page 15

KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, GW#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# t OEQ t KQLZ Q ...

Page 16

KC CLK ADSS t ADSH ADSP# t ADSS t ADSH ADSC ADDRESS BYTE WRITE signals are ignored when ADSP# is LOW. BWE#, BWa#-BWd# GW# t CES t CEH CE# ...

Page 17

KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# t CES t CEH (NOTE 4) CE# (NOTE 2) ADV# OE# D High-Z Q Q(A1) Q(A2) Back-to-Back READs ...

Page 18

PIN #1 ID 14.00 ±0.10 +0.20 16.00 -0.05 NOTE: 1. All dimensions in millimeters MAX or typical here noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, ...

Page 19

REVISION HISTORY Removed 165-pin FBGA package, Rev. 6/01 .................................................................................................. June/7/01 Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00 Changed FBGA capacitance values, REV 8/00, FINAL ............................................................................. August/7/ TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF I ...

Page 20

KC CLK ADSS t ADSH ADSP# t ADSS t ADSH ADSC ADDRESS BYTE WRITE signals are ignored when ADSP# is LOW. BWE#, BWa#-BWd# GW# t CES t CEH CE# ...

Page 21

KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# t CES t CEH (NOTE 4) CE# (NOTE 2) ADV# OE# D High-Z Q Q(A1) Q(A2) Back-to-Back READs ...

Page 22

BALL A11 165X Ø 0.45 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 5.00 ±0.05 13.00 ±0.10 NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable ...

Page 23

PIN #1 ID 14.00 ±0.10 +0.20 16.00 -0.05 NOTE: 1. All dimensions in millimeters MAX or typical here noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, ...

Page 24

REVISION HISTORY Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00 Changed FBGA capacitance values, REV 8/00, FINAL ............................................................................. August/7/ TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF TYP 4pF from 6pF; MAX. 5pF ...

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