UPD70F3286YGJ-UEN NEC, UPD70F3286YGJ-UEN Datasheet
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UPD70F3286YGJ-UEN
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UPD70F3286YGJ-UEN Summary of contents
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User’s Manual V850ES/SJ2 32-Bit Single-Chip Microcontroller Hardware µPD703264 µPD703264Y µPD703265 µPD703265Y µPD703266 µPD703266Y µPD70F3264 µPD70F3264Y µPD70F3266 µPD70F3266Y µPD703274 µPD703274Y Document No. U16603EJ3V1UD00 (3rd edition) Date Published July 2004 N CP(K) 2003 Printed in Japan µPD703275 µPD703275Y µPD703276 µPD703276Y µPD70F3274 µPD70F3274Y ...
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User’s Manual U16603EJ3V1UD ...
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... Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability Ordering information ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/SJ2 and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/SJ2 ...
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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/SJ2 V850ES Architecture User’s Manual V850ES/SJ2 Hardware User’s Manual Documents related to development tools IE-V850ES-G1 (In-Circuit ...
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CHAPTER 1 INTRODUCTION .................................................................................................................20 1.1 General .....................................................................................................................................20 1.2 Features....................................................................................................................................24 1.3 Application Fields ...................................................................................................................25 1.4 Ordering Information ..............................................................................................................26 1.5 Pin Configuration (Top View) .................................................................................................27 1.6 Function Block Configuration................................................................................................30 1.6.1 Internal block diagram ............................................................................................................... 30 1.6.2 Internal units .............................................................................................................................. 31 CHAPTER 2 ...
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Port 9 .......................................................................................................................................130 4.3.10 Port CD ....................................................................................................................................138 4.3.11 Port CM ...................................................................................................................................139 4.3.12 Port CS ....................................................................................................................................141 4.3.13 Port CT ....................................................................................................................................143 4.3.14 Port DH ....................................................................................................................................145 4.3.15 Port DL ....................................................................................................................................147 4.4 Block Diagrams..................................................................................................................... 150 4.5 Port Register Settings When Alternate Function Is ...
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Overview ................................................................................................................................. 237 6.5.2 Registers ................................................................................................................................. 237 6.5.3 Usage ...................................................................................................................................... 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................242 7.1 Overview.................................................................................................................................242 7.2 Functions ...............................................................................................................................242 7.3 Configuration .........................................................................................................................243 7.4 Registers ................................................................................................................................245 7.5 Operation................................................................................................................................257 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 ...
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Configuration ........................................................................................................................ 439 10.3 Control Registers ................................................................................................................. 441 10.4 Operation............................................................................................................................... 445 10.4.1 Operation as watch timer .........................................................................................................445 10.4.2 Operation as interval timer.......................................................................................................446 10.4.3 Cautions...................................................................................................................................447 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 448 11.1 Functions............................................................................................................................... 448 11.2 Configuration ........................................................................................................................ ...
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Features..................................................................................................................................502 15.3 Configuration .........................................................................................................................503 15.4 Registers ................................................................................................................................505 15.5 Interrupt Request Signals.....................................................................................................512 15.6 Operation................................................................................................................................513 15.6.1 Data format.............................................................................................................................. 513 15.6.2 SBF transmission/reception format.......................................................................................... 515 15.6.3 SBF transmission .................................................................................................................... 517 15.6.4 SBF reception.......................................................................................................................... 518 15.6.5 UART transmission.................................................................................................................. 519 15.6.6 Continuous transmission procedure ...
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I C Bus Mode Functions....................................................................................................... 588 17.5.1 Pin configuration ......................................................................................................................588 2 17 Bus Definitions and Control Methods .......................................................................... 589 17.6.1 Start condition..........................................................................................................................589 17.6.2 Addresses................................................................................................................................590 17.6.3 Transfer direction specification ................................................................................................591 17.6.4 Acknowledge signal (ACK) ......................................................................................................592 17.6.5 Stop ...
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... Multi cast ................................................................................................................................. 719 19.3.5 CAN sleep mode/CAN stop mode function.............................................................................. 720 19.3.6 Error control function ............................................................................................................... 720 19.3.7 Baud rate control function........................................................................................................ 727 19.4 Connection with Target System ..........................................................................................731 19.5 Internal Registers of CAN Controller ..................................................................................732 19.5.1 CAN controller configuration.................................................................................................... 732 19.5.2 Register access type ............................................................................................................... 733 19.5.3 Register bit configuration ......................................................................................................... 767 19 ...
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Transmit history list function ....................................................................................................819 19.10.3 Automatic block transmission (ABT) ........................................................................................821 19.10.4 Transmission abort process.....................................................................................................823 19.10.5 Remote frame transmission .....................................................................................................824 19.11 Power Saving Modes............................................................................................................ 825 19.11.1 CAN sleep mode......................................................................................................................825 19.11.2 CAN stop mode .......................................................................................................................827 19.11.3 Example of using power ...
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Maskable Interrupts ..............................................................................................................907 22.3.1 Operation................................................................................................................................. 907 22.3.2 Restore.................................................................................................................................... 909 22.3.3 Priorities of maskable interrupts .............................................................................................. 910 22.3.4 Interrupt control register (xxICn) .............................................................................................. 914 22.3.5 Interrupt mask registers (IMR0 to IMR4)........................................................................ 918 22.3.6 In-service priority register (ISPR)............................................................................................. ...
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Sub-IDLE Mode ..................................................................................................................... 958 24.8.1 Setting and operation status ....................................................................................................958 24.8.2 Releasing sub-IDLE mode .......................................................................................................958 CHAPTER 25 RESET FUNCTIONS ..................................................................................................... 960 25.1 Overview................................................................................................................................ 960 25.2 Registers to Check Reset Source....................................................................................... 962 25.3 Operation............................................................................................................................... 963 25.3.1 Reset operation via RESET ...
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... Standard self programming flow ............................................................................................ 1012 30.5.4 Flash functions ...................................................................................................................... 1013 30.5.5 Pin processing ....................................................................................................................... 1013 30.5.6 Internal resources used ......................................................................................................... 1014 CHAPTER 31 ON-CHIP DEBUG FUNCTION....................................................................................1015 31.1 Features................................................................................................................................1015 31.2 Connection Circuit Example ..............................................................................................1016 31.3 Interface Signals..................................................................................................................1016 31.4 Register ................................................................................................................................1018 31.5 Operation..............................................................................................................................1020 31.6 ROM Security Function.......................................................................................................1021 31.6.1 Security ID............................................................................................................................. 1021 31.6.2 Setting ................................................................................................................................... 1022 31 ...
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... The V850ES/SJ2 is one of the products in the NEC Electronics V850 Series of single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 General The V850ES/SJ2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter. Some models of the V850ES/SJ2 are provided with IEBus automotive LAN ...
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Function ROM Part Number Type Size µ PD703264 Mask ROM 384 KB µ PD703264Y µ PD70F3264 Flash memory µ PD70F3264Y µ PD703265 Mask ROM 512 KB µ PD703265Y µ PD703266 640 KB µ PD703266Y µ PD70F3266 Flash memory µ PD70F3266Y ...
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Mask ROM version µ PD703264, 703264Y, 703265, 703265Y, 703266, 703266Y, 703274, 703274Y, 703275, 703275Y, 703276, 703276Y, 703284, 703284Y, 703285, 703285Y, 703286, 703286Y, 703287, 703287Y, 703288, 703288Y • Flash memory version µ PD70F3264, 70F3264Y, 70F3266, 70F3266Y, 70F3274, 70F3274Y, 70F3276, 70F3276Y, ...
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Function ROM Part Number Type Size µ PD703260 Mask ROM 256 KB µ PD703260Y µ PD703261 384 KB µ PD703261Y µ PD70F3261 Flash memory µ PD70F3261Y µ PD703262 Mask ROM 512 KB µ PD703262Y µ PD703263 640 KB µ PD703263Y ...
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Features Minimum instruction execution time (operating with main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 × 32 → 64): ...
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DMA controller: 4 channels ROM correction: 4 correction addresses specifiable Clock generator: During main clock or subclock operation 7-level CPU clock (f Clock-through mode/PLL mode selectable Ring-OSC: 200 kHz (TYP.) Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode 144-pin plastic LQFP (fine pitch) (20 ...
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Ordering Information Part Number µ 144-pin plastic LQFP (fine pitch) (20 × 20) Note PD703264GJ-xxx-UEN µ 144-pin plastic LQFP (fine pitch) (20 × 20) Note PD703264YGJ-xxx-UEN µ 144-pin plastic LQFP (fine pitch) (20 × 20) Note PD703265GJ-xxx-UEN µ 144-pin ...
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Pin Configuration (Top View) 144-pin plastic LQFP (fine pitch) (20 × 20) µ Note PD703264GJ-xxx-UEN µ Note PD703264YGJ-xxx-UEN µ Note PD703265GJ-xxx-UEN µ Note PD703265YGJ-xxx-UEN µ Note PD703266GJ-xxx-UEN µ Note PD703266YGJ-xxx-UEN µ Note PD70F3264GJ-UEN µ Note PD70F3264YGJ-UEN µ PD70F3266GJ-UEN µ ...
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... P38/TXDA2/SDA00 35 Note 4 P39/RXDA2/SCL00 36 Notes 1. IC: Directly connect this pin to V FLMD0: Connect these pins to V FLMD1: Flash memory version only 2. Connect the REGC pin DRST, DDI, DDO, DCK, and DMS are valid only in the flash memory version. 4. SCL00 to SCL02 and SDA00 to SDA02 are valid only in the I 5 ...
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... Ground for port SS FLMD0, FLMD1: Flash programming mode HLDAK: Hold acknowledge HLDRQ: Hold request IC: Internally connected IERX0: IEBus receive data IETX0: IEBus transmit data INTP0 to INTP8: External interrupt input KR0 to KR7: Key return NMI: Non-maskable interrupt request P00 to P06: Port 0 ...
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Function Block Configuration 1.6.1 Internal block diagram NMI INTC INTP0 to INTP8 16-bit timer/ TIQ00 to TIQ03 counter Q: TOQ00 to TOQ03 1 ch TIP00 to TIP80, 16-bit timer/ TIP01 to TIP81 counter P: TOP00 to TOP80 ...
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Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either Ring-OSC, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates a non-maskable ...
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CRC function A CRC operation circuit that generates 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data is provided on chip. (21) On-chip debug function An on-chip debug function via an N-wire-type emulator that uses the JTAG ...
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List of Pin Functions The names and functions of the pins of the V850ES/SJ2 are described below. There are four types of pin I/O buffer power supplies: AV these power supplies and the pins is described below. Power Supply ...
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... N-ch open-drain output can be specified in 1-bit units. P53 tolerant. P54 41 P55 42 Notes 1. Incorporates a pull-down resistor. It can be disconnected by clearing the OCDM.OCDM0 bit. 2. Flash memory version only 3. CAN controller (2-channel) version only 4. CAN controller version only 5. IEBus controller version only bus version (Y version) only ...
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Pin Name Pin No. I/O P60 43 I/O Port 6 16-bit I/O port P61 44 Input/output can be specified in 1-bit units. P62 45 N-ch open-drain output can be specified in 1-bit units. P63 tolerant. P64 47 ...
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Pin Name Pin No. I/O P90 61 I/O Port 9 16-bit I/O port P91 62 Input/output can be specified in 1-bit units. P92 63 N-ch open-drain output can be specified in 1-bit units. P93 tolerant. P94 65 ...
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Pin Name Pin No. I/O PCT0 95 I/O Port CT 8-bit I/O port PCT1 96 Input/output can be specified in 1-bit units. PCT2 97 PCT3 98 PCT4 99 PCT5 100 PCT6 101 PCT7 102 PDH0 121 I/O Port DH 8-bit ...
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Non-port pins Pin Name Pin No. I Output Address bus for external memory (when using separate bus N-ch open-drain output selectable tolerant ...
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Pin Name Pin No. I/O ADTRG 18 Input A/D converter external trigger input tolerant ANI0 144 Input Analog voltage input for A/D converter ANI1 143 ANI2 142 ANI3 141 ANI4 140 ANI5 139 ANI6 138 ANI7 137 ANI8 ...
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... FLMD1 110 HLDAK 87 Output Bus hold acknowledge output HLDRQ 88 Input Bus hold request input − Note Internally connected Note 4 IERX0 32 Input IEBus receive data input tolerant Note 4 IEBus transmit data output IETX0 31 Output N-ch open-drain output selectable tolerant INTP0 18 ...
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... NMI 17 Input External interrupt input (non-maskable, analog noise elimination tolerant RD 99 Output Read strobe signal output for external memory − REGC 10 Connection of regulator output stabilization capacitance µ (4.7 F) RESET 14 Input System reset input RTP00 37 Output Real-time output port N-ch open-drain output selectable ...
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Pin Name Pin No. I/O SIB0 22 Input Serial receive data input (CSIB0, CSIB1, CSIB2, CSIB3, CSIB4, CSIB5) SIB1 tolerant SIB2 40 SIB3 71 SIB4 26 SIB5 49 Serial transmit data output (CSIB0, CSIB1, CSIB2, CSIB3, SOB0 ...
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... External wait input WR0 95 Output Write strobe for external memory (lower 8 bits) WR1 96 Write strove for external memory (higher 8 bits Input Connection of resonator for main clock − XT1 15 Input Connection of resonator for subclock − XT2 16 Notes 1. CAN controller (2-channel) version only 2 ...
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Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Bus Control Pin Reset Note 3 AD0 to AD15 Hi A15 A16 to A23 WAIT ...
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... Internally pull-down after reset by RESET pin. 10-D Input: Independently connect to EV resistor. Output: Leave open. 12-D Input: Independently connect to AV resistor. Output: Leave open. 10-D Input: Independently connect to EV resistor. Output: Leave open. Note 1 Note 1 Note 1 User’s Manual U16603EJ3V1UD (1/3) Recommended Connection or EV via a ...
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... Input: Independently connect to EV Output: Leave open. 11-G Input: Independently connect to AV Output: Leave open. 10-D Input: Independently connect to EV Output: Leave open. Note Note 5 Input: Independently connect to BV Output: Leave open. User’s Manual U16603EJ3V1UD (2/3) Recommended Connection or EV via resistor ...
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... Always connect this pin directly to the ground (also in the standby mode). − Always connect this pin to the power supply (also in the standby mode). − Always connect this pin to the ground (also in the standby mode). − Connect memory programming mode. − ...
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CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable EV / Input enable Type 10 Data P-ch ...
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The CPU of the V850ES/SJ2 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time (at 20 MHz operation) Memory space Program (physical address) ...
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CPU Register Set The registers of the V850ES/SJ2 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program ...
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Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data variable ...
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System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. ...
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Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to ...
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NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those ...
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Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this ...
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Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a ...
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Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the ...
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... In the normal mode, make sure that the FLMD0/IC pin goes low when reset is released. In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. Operation When Reset Is Released ...
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Address Space 3.4.1 CPU address space For addressing instruction addresses external memory area, internal ROM area, and internal RAM area in an area linear address space (program space) ...
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Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a ...
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Memory map The areas shown below are reserved in the V850ES/SJ2. Figure 3-2. Data Memory Map (Physical Addresses (80 KB ...
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CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map Use prohibited (program fetch prohibited area ...
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Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (384 KB) 384 KB are allocated to addresses 00000000H to 0005FFFFH in the following versions. Accessing addresses 00060000H to 000FFFFFH ...
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CHAPTER 3 CPU FUNCTION (b) Internal ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the following versions. Accessing addresses 00080000H to 000FFFFFH is prohibited. µ • PD703265, 703265Y, 703275, 703275Y, 703285, 703285Y, 703287, 703287Y Figure ...
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Internal RAM area are reserved as the internal RAM area. (a) Internal RAM (32 KB are allocated to addresses 03FF7000H to 03FFEFFFH in the following versions. Accessing addresses 03FF0000H to 03FF6FFFH is prohibited. ...
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CHAPTER 3 CPU FUNCTION (b) Internal RAM (40 KB are allocated to addresses 03FF5000H to 03FFEFFFH in the following versions. Accessing addresses 03FF0000H to 03FF4FFFH is prohibited. µ • PD703265, 703265Y, 703275, 703275Y, 703285, 703285Y, 703287, 703287Y Figure ...
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On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Physical address space ...
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Programmable peripheral I/O area Cautions 1. The programmable peripheral I/O area exists only in the CAN controller versions. This area cannot be used with products that are not equipped with the CAN controller. 2. Only the programmable peripheral I/O ...
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Recommended use of address space The architecture of the V850ES/SJ2 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ...
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Data space With the V850ES/SJ2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25 26-bit address is sign-extended to 32 bits and ...
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Figure 3-12. Recommended Memory Map Program space ...
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Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DLL register FFFFF005H Port DLH register FFFFF006H Port DH register FFFFF008H Port CS register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF00EH Port CD register ...
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Address Function Register Name FFFFF09CH DMA destination address register 3L FFFFF09EH DMA destination address register 3H FFFFF0C0H DMA transfer count register 0 FFFFF0C2H DMA transfer count register 1 FFFFF0C4H DMA transfer count register 2 FFFFF0C6H DMA transfer count register 3 ...
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Address Function Register Name FFFFF12CH Interrupt control register FFFFF12EH Interrupt control register FFFFF130H Interrupt control register FFFFF132H Interrupt control register FFFFF134H Interrupt control register FFFFF136H Interrupt control register FFFFF138H Interrupt control register FFFFF13AH Interrupt control register FFFFF13CH Interrupt control register ...
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Address Function Register Name FFFFF17EH Interrupt control register FFFFF180H Interrupt control register FFFFF182H Interrupt control register FFFFF184H Interrupt control register FFFFF186H Interrupt control register FFFFF188H Interrupt control register FFFFF18AH Interrupt control register FFFFF18CH Interrupt control register FFFFF18EH Interrupt control register ...
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Address Function Register Name FFFFF210H A/D conversion result register 0 FFFFF211H A/D conversion result register 0H FFFFF212H A/D conversion result register 1 FFFFF213H A/D conversion result register 1H FFFFF214H A/D conversion result register 2 FFFFF215H A/D conversion result register 2H ...
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Address Function Register Name FFFFF324H BRG2 prescaler mode register FFFFF325H BRG2 prescaler compare register FFFFF328H BRG3 prescaler mode register FFFFF329H BRG3 prescaler compare register FFFFF340H IIC division clock select register 0 FFFFF344H IIC division clock select register 1 FFFFF348H IEBus ...
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Address Function Register Name FFFFF420H Port 0 mode register FFFFF422H Port 1 mode register FFFFF426H Port 3 mode register FFFFF426H Port 3 mode register L FFFFF427H Port 3 mode register H FFFFF428H Port 4 mode register FFFFF42AH Port 5 mode ...
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Address Function Register Name FFFFF540H TMQ0 control register 0 FFFFF541H TMQ0 control register 1 FFFFF542H TMQ0 I/O control register 0 FFFFF543H TMQ0 I/O control register 1 FFFFF544H TMQ0 I/O control register 2 FFFFF545H TMQ0 option register FFFFF546H TMQ0 capture/compare register ...
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Address Function Register Name FFFFF5C5H TMP3 option register FFFFF5C6H TMP3 capture/compare register 0 FFFFF5C8H TMP3 capture/compare register 1 FFFFF5CAH TMP3 counter read buffer register FFFFF5D0H TMP4 control register 0 FFFFF5D1H TMP4 control register 1 FFFFF5D2H TMP4 I/O control register 0 ...
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Address Function Register Name FFFFF612H TMP8 I/O control register 0 FFFFF613H TMP8 I/O control register 1 FFFFF614H TMP8 I/O control register 2 FFFFF615H TMP8 option register FFFFF616H TMP8 capture/compare register 0 FFFFF618H TMP8 capture/compare register 1 FFFFF61AH TMP8 counter read ...
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Address Function Register Name FFFFF844H Correction address register 1 FFFFF844H Correction address register 1L FFFFF846H Correction address register 1H FFFFF848H Correction address register 2 FFFFF848H Correction address register 2L FFFFF84AH Correction address register 2H FFFFF84CH Correction address register 3 FFFFF84CH ...
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Address Function Register Name FFFFFA33H UARTA3 option control register 0 FFFFFA34H UARTA3 status register FFFFFA36H UARTA3 receive data register FFFFFA37H UARTA3 transmit data register FFFFFC00H External interrupt falling edge specification register 0 FFFFFC06H External interrupt falling edge specification register 3 ...
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Address Function Register Name FFFFFD22H CSIB2 control register 2 FFFFFD23H CSIB2 status register FFFFFD24H CSIB2 receive data register FFFFFD24H CSIB2 receive data register L FFFFFD26H CSIB2 transmit data register FFFFFD26H CSIB2 transmit data register L FFFFFD30H CSIB3 control register 0 ...
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Address Function Register Name FFFFFD94H IIC clock select register 1 FFFFFD95H IIC function expansion register 1 FFFFFD96H IIC status register 1 FFFFFD9AH IIC flag register 1 FFFFFDA0H IIC shift register 2 FFFFFDA2H IIC control register 2 FFFFFDA3H IIC slave address ...
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Programmable peripheral I/O registers The BPC register is used for programmable peripheral I/O register area selection. (1) Peripheral I/O area select control register (BPC) The BPC register can be read or written in 16-bit units. Reset input clears this ...
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Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. V850ES/SJ2 has the following eight special registers. • Power save control register (PSC) • Clock control register (CKC) • ...
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... Write the setting data to the special register (by using the following instructions). • Store instruction (ST/SST instruction) • Bit manipulation instruction (SET1/CLR1/NOT1 instruction) (<5> to <9> Insert NOP instructions (5 instructions).) <10> Enable DMA operation if necessary. [Example] With PSC register (setting standby mode) ST.B r11, PSMR[r0] <1>CLR1 0, DCHCn[r0] <2>MOV0x02, r10 < ...
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Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first ...
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System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. ...
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... On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary. When using the external bus, set each pin to the alternate-function bus control pin mode by using the port- related registers after setting the above registers ...
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Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus ...
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... CnMDATA6m, CnMDATA7m, CnMDLCm, CnMCONFm, CnMIDLm, CnMIDHm, CnMCTRLm Number of clocks necessary for access = × Notes bus version (Y version only) 2. Digits below the decimal point are rounded up. Caution When the CPU operates on the subclock and main oscillation is stopped, accessing a register for which wait cycles are generated is prohibited ...
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Cautions on using flash memory version The following are the flash memory versions of the V850ES/SJ2. • µ PD70F3264, 70F3264Y, 70F3266, 70F3266Y, 70F3274, 70F3274Y, 70F3276, 70F3276Y, 70F3284, 70F3284Y, 70F3286, 70F3286Y, 70F3288, 70F3288Y 0000007AH is the area reserved by the ...
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Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before ...
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Features I/O ports: 128 • tolerant/N-ch open-drain output switchable: 60 (ports Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/SJ2 features a total of 128 I/O ports consisting of ...
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Port Configuration Item Control register Port n mode register (PMn CD, CM, CS, CT, DH, DL) Port n mode control register (PMCn CM, CS, ...
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Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be ...
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Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, ...
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Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in ...
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Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate function ...
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Port 0 Port 7-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P00 6 TIP61/TOP61 P01 7 TIP60/TOP60 P02 ...
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Registers (a) Port 0 register (P0) After reset: 00H (output latch P06 P0n 0 Outputs 0 1 Outputs 1 (b) Port 0 mode register (PM0) After reset: FFH R/W PM0 1 PM06 PM0n 0 Output mode 1 ...
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CHAPTER 4 PORT FUNCTIONS (c) Port 0 mode control register (PMC0) After reset: 00H R/W Address: FFFFF440H PMC0 0 PMC06 PMC06 0 I/O port 1 INTP3 input PMC05 0 I/O port 1 INTP2 input PMC04 0 I/O port 1 INTP1 ...
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Port 0 function control register (PFC0) After reset: 00H R/W PFC0 0 PFC03 0 INTP0 input 1 ADTRG input PFC01 0 TIP60 input 1 TOP60 output PFC00 0 TIP61 input 1 TOP61 output (e) Port 0 function register (PF0) ...
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Port 1 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P10 3 ANO0 P11 4 ANO1 (1) ...
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Port 3 Port 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P30 25 TXDA0/SOB4 P31 26 RXDA0/INTP7/SIB4 P32 ...
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Registers (a) Port 3 register (P3) After reset: 0000H (output latch (P3H (P3L) P37 P36 P3n 0 Outputs 0 1 Outputs 1 Remarks 1. The P3 register can be read or written in 16-bit ...
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Port 3 mode control register (PMC3) After reset: 0000H 15 PMC3 (PMC3H) 0 (PMC3L) PMC37 PMC39 0 1 PMC38 0 1 110 CHAPTER 4 PORT FUNCTIONS R/W Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H ...
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CHAPTER 4 PORT FUNCTIONS PMC37 Specification of P37 pin operation mode 0 I/O port 1 CRXD0 input/IERX0 input PMC36 Specification of P36 pin operation mode 0 I/O port 1 CTXD0 output/IETX0 output PMC35 Specification of P35 pin operation mode 0 ...
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Port 3 function control register (PFC3) After reset: 0000H 15 PFC3 (PFC3H) 0 (PFC3L) PFC37 Remarks 1. For details of alternate function specification, see 4.3.3 (1) (f) Port 3 alternate function specifications. 2. The PFC3 register can be read ...
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CHAPTER 4 PORT FUNCTIONS (f) Port 3 alternate function specifications PFC39 0 RXDA2 input 1 SCL00 input PFC38 0 TXDA2 output 1 SDA00 I/O PFC37 0 CRXD0 input 1 IERX0 input PFC36 0 CTXD0 output 1 IETX0 output PFC35 0 ...
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PFC31 0 RXDA0 input/INTP7 1 SIB4 input PFC30 0 TXDA0 output 1 SOB4 output Note The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as the RXDA0 pin, disable edge detection for the INTP7 alternate-function pin. ...
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Port 4 Port 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P40 22 SIB0/SDA01 P41 23 SOB0/SCL01 P42 24 SCKB0 2 Note ...
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Registers (a) Port 4 register (P4) After reset: 00H (output latch P4n 0 Outputs 0 1 Outputs 1 (b) Port 4 mode register (PM4) After reset: FFH R/W PM4 1 PM4n 0 Output mode 1 Input mode ...
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CHAPTER 4 PORT FUNCTIONS (d) Port 4 function control register (PFC4) After reset: 00H R/W Address: FFFFF468H PFC4 0 0 PFC41 0 SOB0 output 1 SCL01 I/O PFC40 0 SIB0 input 1 SDA01 I/O (e) Port 4 function register (PF4) ...
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Port 5 Port 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P50 37 TIQ01/KR0/TOQ01/RTP00 P51 38 TIQ02/KR1/TOQ02/RTP01 P52 39 TIQ03/KR2/TOQ03/RTP02/DDI P53 40 ...
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CHAPTER 4 PORT FUNCTIONS (c) Port 5 mode control register (PMC5) After reset: 00H R/W Address: FFFFF44AH PMC5 0 0 PMC55 0 I/O port 1 SCKB2 I/O/KR5 input/RTP05 output PMC54 0 I/O port 1 SOB2 output/KR4 input/RTP04 output PMC53 0 ...
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Port 5 function control expansion register (PFCE5) After reset: 00H R/W PFCE5 0 Remark For details of alternate function specification, see 4.3.5 (1) (f) Port 5 alternate function specifications. (f) Port 5 alternate function specifications PFCE55 PFC55 0 0 ...
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CHAPTER 4 PORT FUNCTIONS PFCE50 PFC50 0 0 Setting prohibited 0 1 TIQ01 input/KR0 1 0 TOQ01 output 1 1 RTP00 output Note The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as the TIQ0m pin, ...
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Port 6 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P60 43 RTP10 P61 44 RTP11 P62 ...
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Registers (a) Port 6 register (P6) After reset: 0000H (output latch (P6H) P615 P614 (P6L) P67 P66 P6n 0 Outputs 0 1 Outputs 1 Remarks 1. The P6 register can be read or written in 16-bit ...
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Port 6 mode control register (PMC6) After reset: 0000H 15 PMC6 (PMC6H) 0 PMC67 (PMC6L) PMC613 0 1 PMC612 0 1 PMC611 0 1 PMC610 0 1 PMC69 0 1 PMC68 0 1 PMC67 0 1 PMC66 0 1 ...
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CHAPTER 4 PORT FUNCTIONS (d) Port 6 function control register H (PFC6H) After reset: 00H R PFC6H 0 0 PFC613 0 TIP81 input 1 TOP81 output PFC612 0 TIP80 input 1 TOP80 output PFC69 0 TIP70 input 1 ...
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Port 7 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-10. Port 7 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name P70 ...
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Registers (a) Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) P7H P715 P714 P77 P76 P7L P7n 0 Outputs 0 1 Outputs 1 Caution Do not read the P7H and P7L registers ...
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Port 8 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 8 includes the following alternate-function pins. Table 4-11. Port 8 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name P80 ...
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CHAPTER 4 PORT FUNCTIONS (c) Port 8 mode control register (PMC8) After reset: 00H R/W Address: FFFFF450H PMC8 0 0 PMC81 0 I/O port 1 TXDA3 output PMC80 0 I/O port 1 RXDA3 input/INTP8 Note The INTP8 and RXDA3 pins ...
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Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-12. Port 9 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name P90 ...
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Registers (a) Port 9 register (P9) After reset: 0000H (output latch (P9H) P915 P914 (P9L) P97 P96 P9n 0 Outputs 0 1 Outputs 1 Remarks 1. The P9 register can be read or written in 16-bit ...
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Port 9 mode control register (PMC9) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 1 PMC99 ...
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CHAPTER 4 PORT FUNCTIONS PMC98 Specification of P98 pin operation mode 0 I/O port 1 A8 output/SOB1 output PMC97 Specification of P97 pin operation mode 0 I/O port 1 A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 Specification of P96 pin operation ...
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Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 register to 0000H. After reset: 0000H 15 ...
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CHAPTER 4 PORT FUNCTIONS (f) Port 9 alternate function specifications PFCE915 PFC915 0 0 A15 output 0 1 INTP6 input 1 0 TIP50 input 1 1 TOP50 output PFCE914 PFC914 0 0 A14 output 0 1 INTP5 input 1 0 ...
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PFCE96 PFC96 PFCE95 PFC95 PFCE94 PFC94 PFCE93 PFC93 ...
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CHAPTER 4 PORT FUNCTIONS (g) Port 9 function register (PF9) After reset: 0000H R PF9 (PF9H) PF915 PF914 (PF9L) PF97 PF96 PF9n Control of normal output or N-ch open-drain output ( 15) 0 Normal output ...
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Port CD Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CD includes the following alternate-function pins. Table 4-13. Port CD Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PCD0 ...
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Port CM Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-14. Port CM Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PCM0 ...
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Port CM mode control register (PMCCM) After reset: 00H R/W PMCCM 0 PMCCM3 0 I/O port 1 HLDRQ input PMCCM2 0 I/O port 1 HLDAK output PMCCM1 0 I/O port 1 CLKOUT output PMCCM0 0 I/O port 1 WAIT ...
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Port CS Port 8-bit port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Table 4-15. Port CS Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PCS0 ...
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Port CS mode control register (PMCCS) After reset: 00H R/W PMCCS 0 PMCCS3 0 I/O port 1 CS3 output PMCCS2 0 I/O port 1 CS2 output PMCCS1 0 I/O port 1 CS1 output PMCCS0 0 I/O port 1 CS0 ...
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Port CT Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-16. Port CT Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PCT0 ...
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Port CT mode control register (PMCCT) After reset: 00H R/W PMCCT 0 PMCCT6 PMCCT6 0 I/O port 1 ASTB output PMCCT4 0 I/O port 1 RD output PMCCT1 0 I/O port 1 WR1 output PMCCT0 0 I/O port 1 ...
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Port DH Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-17. Port DH Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PDH0 ...
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Port DH mode control register (PMCDH) After reset: 00H R/W PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn 0 I/O port 1 Am output (address bus output 23) 146 CHAPTER 4 PORT FUNCTIONS ...
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Port DL Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-18. Port DL Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PDL0 ...
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Registers (a) Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 (PDLL) PDL7 PDLn 0 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 ...
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CHAPTER 4 PORT FUNCTIONS (c) Port DL mode control register (PMCDL) After reset: 0000H R PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 I/O port 1 ADn ...
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Block Diagrams PORT RD 150 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of Type A-1 PMmn Pmn Address Pch A/D input signal Nch User’s Manual U16603EJ3V1UD Pmn ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A PMmn WR PORT Pmn Address RD D/A input signal Figure 4-5. Block Diagram of Type B PMmn WR PORT Pmn Address RD User’s Manual U16603EJ3V1UD ...
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WR PF PFmn WR PM PMmn WR PORT Pmn Address RD Note Hysteresis characteristics are not available in port mode. 152 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type C-1 User’s Manual U16603EJ3V1UD EV DD Pch Pmn Nch ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-1 WR PMC PMCmn WR PM PMmn WR PORT Pmn Address Input signal when RD alternate function is used User’s Manual U16603EJ3V1UD Pmn 153 ...
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WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn RD 154 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D-2 Address User’s Manual U16603EJ3V1UD Pmn ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D-3 WR PMC PMCmn Output enable signal of address/data bus Output buffer off signal WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address Input enable ...
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WR PF PFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. 156 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of ...
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Figure 4-11. Block Diagram of Type E PFmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Note Hysteresis characteristics are not available in port mode. CHAPTER 4 PORT ...
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WR PF PFmn Output enable signal when alternate function is used WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are ...
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Figure 4-13. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis ...
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WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. ...
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Figure 4-15. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD ...
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WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Output signal 1 when alternate function is used Output signal 2 when alternate function is used Note Hysteresis characteristics are not available in ...
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Figure 4-17. Block Diagram of Type G PFmn Output enable signal when alternate function is used WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate ...
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WR PF PFmn Output enable signal when alternate function is used WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal 1 when alternate function is used ...
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Figure 4-19. Block Diagram of Type L PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when Edge detection alternate function is ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used ...
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Figure 4-21. Block Diagram of Type N PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when Edge alternate ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when alternate function is used Notes 1. See 22.6 External Interrupt ...
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Figure 4-23. Block Diagram of Type N PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when Edge alternate ...
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WR PF PFmn Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR ...
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Figure 4-25. Block Diagram of Type U PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address RD Input signal 1 when alternate function is used Input signal 2 when ...
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Figure 4-27. Block Diagram of Type U PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal 1-1 when RD ...
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Figure 4-29. Block Diagram of Type U PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
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WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging WR ...
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Figure 4-31. Block Diagram of Type U PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
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WR PF PFmn WR OCDM0 OCDM0 Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function ...
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Figure 4-33. Block Diagram of Type U- PFmn Output enable signal when alternate WR PFCE function is used PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal ...
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WR PF PFmn Output enable signal when alternate WR PFCE function is used PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR ...
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Figure 4-35. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when RD alternate ...
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Figure 4-37. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
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Figure 4-39. Block Diagram of Type AA PFmn External WR OCDM0 reset signal OCDM0 WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when ...
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Port Register Settings When Alternate Function Is Used Table 4-19 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P00 TIP61 Input P00 = Setting not required TOP61 Output P00 = Setting not required P01 TIP60 Input P01 = Setting not required TOP60 Output P01 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P33 TIP01 Input P33 = Setting not required TOP01 Output P33 = Setting not required Note 1 CTXD1 Output P33 = Setting not required P34 TIP10 Input P34 = ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P50 TIQ01 Input P50 = Setting not required KR0 Input P50 = Setting not required TOQ01 Output P50 = Setting not required RTP00 Output P50 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P54 SOB2 Output P54 = Setting not required KR4 Input P54 = Setting not required RTP04 Output P54 = Setting not required Note DCK Input P54 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P70 ANI0 Input P70 = Setting not required P71 ANI1 Input P71 = Setting not required P72 ANI2 Input P72 = Setting not required P73 ANI3 Input P73 = ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P90 A0 Output P90 = Setting not required KR6 Input P90 = Setting not required TXDA1 Output P90 = Setting not required Note 2 SDA02 I/O P90 = Setting ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P96 A6 Output P96 = Setting not required TIP21 Input P96 = Setting not required TOP21 Output P96 = Setting not required P97 A7 Output P97 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P914 A14 Output P914 = Setting not required INTP5 Input P914 = Setting not required TIP51 Input P914 = Setting not required TOP51 Output P914 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PDH0 A16 Output PDH0 = Setting not required PDH1 A17 Output PDH1 = Setting not required PDH2 A18 Output PDH2 = Setting not required PDH3 A19 Output PDH3 = ...
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Cautions 4.6.1 Cautions on setting port pins (1) In the V850ES/SJ2, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function ...
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... In <2> communication may be affected since the alternate-function SOB0 output is output to the pin. In the CMOS output period of <2> or <3>, unnecessary current may be generated. (b) Cautions on alternate-function mode (input) The input signal to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND output of the PMCn register set value and the pin level ...
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Figure 4-40. Example of Switching from P02 to NMI (Incorrect) PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Remark [Example 2] Switch from external pin (NMI) to general-purpose ...
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Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is ...
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... Cautions on P05/INTP2/DRST pin The P05/INTP2/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a reset by the RESET pin, a pull- down resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0). 4.6.5 Hysteresis characteristics In port mode, the following port pins do not have hysteresis characteristics. ...