PEB2081P Infineon Technologies AG, PEB2081P Datasheet
PEB2081P
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PEB2081P Summary of contents
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ICs for Communications S/T Bus Interface Circuit Extended SBCX PEB 2081 Version 3.4 User’s Manual 11.96 T2081-XV34-M2-7600 ...
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Edition 11.96 This edition was realized using the ‚ software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other ...
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ICs for Communications S/T Bus Interface Circuit Extended SBCX PEB 2081 Version 3.4 User’s Manual 11.96 ...
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PEB 2081 Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in new Version) Version) Current Version: 11.96 ...
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Contents Introduction ...
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Contents (cont’d) 3.2.3.2 Standard I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents (cont’d) 4.1.4 Maintenance Auxiliary Interface (MAI ...
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Contents (cont’d) 4.5 Maintenance Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Figures Figure 1: PEB 2081 SBCX in P-DIP-28 and P-LCC-28-R Packages . . . . . . . . . . . . . . . . . . . . 12 Figure 2: Logic Symbol of the ...
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Table of Figures (cont’d) Figure 34: Definition of the IOM Figure 35: C/I-Channel Use with the ICC (all data values hexadecimal ...
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Table of Figures (cont’d) Figure 72: Receive PLL of the SBCX in TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction The PEB 2081 S/T Bus Interface Circuit Extended (SBCX) implements the four-wire S/T-interface used to link voice/data ISDN terminals, network terminators and PABX trunk lines to a Central Office. The SBCX provides the electrical and functional link between the ...
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S/T Bus Interface Circuit Extended 1 Features Full duplex 2B+D S/T-interface transceiver according to the following specifications: – ITU Recommendation I.430 – ETS 300 012 – ANSI T1.605 192 kbit/s transmission rate Pseudo-ternary coding with 100 % pulse width Activation ...
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Pin Configuration (top view) P-DIP-28 MAI RST 7 MAI 2 8 FSC 9 MAI 1 10 DCL 11 IDP1 12 IDP 0 ...
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Pin Definition and Functions Pin No. Symbol 11 DCL 9 FSC 13 IDP0 12 IDP1 25 SR1 26 SR2 2 SX1 3 SX2 15 MODE 28, 23, 21, 19 MAI (7:4) ...
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Logic Symbol R IOM -2 Interface Maintenance Auxiliary Interface Mode Mode Specific Functions Figure 2 Logic Symbol of the SBCX Semiconductor Group DCL FSC IDP 0 IDP 1 MAI ( 2081 PEB (SBCX) MODE ...
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Functional Block Diagram DPLL Figure 3 Block Diagram of the SBCX Semiconductor Group Transmit R IOM Interface Logic Buffer D-Channel Control Receive Buffer 15 Features FSC DCL IPD 1 IPD 0 ...
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System Integration and Applications The SBCX implements the four-wire S- and T-interfaces used in the ISDN basic access. By programming the corresponding operating mode it may be used at both ends of these interfaces. The operating modes are: ISDN ...
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Operational Modes and System Integration 2.1.1 TE Application In the terminal several IOM-2 compatible devices can be connected to the IOM-2 bus structure (e.g. PEB 2070 ISDN Communications Controller (ICC), PSB 2161 Audio Ringing Codec Filter ® (ARCOFI ), ...
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MHz 11 8 kHz 7.68 MHz 768 kHz PCK µ GND ...
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ISDN Network Termination (NT1) The S-interface is a four-wire interface for connecting ISDN Terminal Equipment (TE) and Terminal Adapter (TA) to the Network Termination (NT). From here a twisted pair interfaces to the exchange. The Network Terminator interfaces the ...
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System Clock 7.68 MHz 16 from U-Interface 17 CEB 0 µF 4 ...
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TE SBCX SBCX 2 km Figure 9 NT-Star Configuration with 8 TEs Connected Point-to-Point Figure 10 NT-Star Configuration with 2 TEs Connected Point-to-Point and 6 TEs Connected via an Extended Passive Bus Semiconductor ...
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PEB 2081 SBCX NT/LT-S PEB 2081 SBCX NT/LT-S Figure 11 NT-Star Configuration Semiconductor Group R IOM -2 Terminal Interface PEB IEC-Q1 CEB ITS03976 22 System Integration 2091 ...
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System 7.68 MHz 16 Clock CEB 0 µ GND ...
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ISDN Network Terminator Using IOM The IOM-2 architecture allows to build a micro controlled NT using additionally the ICC and operating the IEC-Q (or IBC) in the IOM-2 terminal mode. The ICC provides software controlled layer-1 maintenance function such ...
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The S-interface is the standard ISDN subscriber interface, but in a PBX environment also an U-interface (e.g. IBC or IEC-Q) may be used for the connection of a subscriber resulting in an U-interface terminal with an S/T-extension (Intelligent NT). The ...
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System 7.68 MHz 16 Clock 17 CEB ...
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Line Card Application (one D-channel controller per line) The SBCX supports a line card implementation both in an ISDN Subscriber Line Termination LT-S) and in an ISDN Trunk Line Termination (LT-T) using e.g. the PEB 2055 Extended PCM Interface ...
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MHz CEB ...
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Line Card Application (one D-channel controller for eight lines) This configuration is used under the same circumstances as described in section 2.1.3 “NT1 Star Configuration”. Refer to this section for additional information. Figure 18 and figure 19 illustrate the ...
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V 512 kHz 11 8 kHz 7.68 MHz CEB ...
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Private-Branch-Exchange Application (one D-channel controller per line) The SBCX also supports ISDN-PBX configurations in its LT-T (Line Termination-Trunk) mode. By providing internal buffers in this mode, the device is able to compensate phase deviations between the two clock systems ...
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D-channel processing is handled by a separate controller for each line as was the case for line card applications. In order to guarantee correct D-channel access on the S-interface when additional terminals are connected to the same S-bus, an external ...
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R IOM -2 7.68 Clock MHz Generator 33 pF 1536 kHz System 0 Clock 0 µ F GND 0/5 V ...
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Setting Operating Modes Tables 1-2 illustrate which modes are supported by the PEP 2081 version 3.4 and how they can be configured by the user. Table 1 gives an overview of pin signals and the register configuration. For the ...
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Table 1 Modes of Operation (cont’d) Configuration LT-S Point-Point/Bus Register Configuration 0 Bit 0 (Mode) [0] 1) Configuration 0/1 Bit 1 (C/W/P) [0] Configuration 0/1 Bit 5 (FSMM) [0] Configuration 0 Bit 6 (MAIM) [0] SM/CI 0 Bit 0 (MIO) ...
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Table 2 IOM -2 Channel Assignment *) IOM -2 TS2 TS1 Channel No ...
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Clock Generation Clock generation varies with the application. The following diagrams show what timing signals need to be generated for each SBCX mode and how system synchronization is obtained. 2.3.1 TE Mode X3 = 768 FSC = 8 DCL ...
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NT Mode Figure 24 Clocks Generation in NT Mode In NT Mode the SBCX is supplied with synchronous IOM clocks and a synchronous base clock signal. These signals typically are generated by the upstream U-interface device (PEB 2091 or ...
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LT-T Mode XTAL1 FSC LT-S DCL 1 Synchr. XTAL1 FSC LT-S DCL 2 Synchr. XTAL1 FSC LT-S DCL 8 Synchr. Figure 25 Clock Generation in LT-T Mode Semiconductor Group Ref. XIN = 7.68 MHz Clock FSC = 8 kHz ...
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In LT-T mode IOM-clock signals are not issued by the device but need to be generated externally. In order to ensure synchronous timing to the PTT-master clock, a PLL is used for generation of FSC and DCL (supplied to LT-T ...
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LT-S Mode 7.68 MHz LT-S 7.68 MHz LT-S 7.68 MHz LT-S Synchr. Figure 26 Clock Generation in LT-S Mode In LT-S mode the device synchronizes with the internal Transmit PLL (XPLL) the freerunning crystal clock onto the FSC signal. ...
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S/T-Interface Configurations The receiver of the SBCX exceeds the electrical requirements of the S/T-interface. An overview of the different wiring configurations is given in the following figures. The maximum length of a point-to-point configuration depends on the kind of ...
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Application Guide 3.1 SBCX Device Architecture and General Functions The SBCX performs the layer-1 functions of the S/T-interface according to ITU recommendation I.430, ETS 300 012 and T1.605 Basic User Network Interface Specification, respectively. It can be used at ...
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The Common Functions for all Operating Modes are: line transceiver functions for the S/T-interface according to the electrical specifications of ITU I.430 The pseudo-ternary pulse shaping which meets the I.430 pulse templates, is achieved with the integrated transmitter. The integrated ...
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Interfaces Section 3.2 describes the interfaces supplied by the SBCX. Three interfaces are implemented: – IOM-2 Interface – S-Interface – Maintenance Auxiliary Interface ® 3.2.1 IOM -2 Interface The IOM-2 interface is primarily used to interconnect telecommunication ICs. It ...
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Within one FSC period 32 bit to 512 bit are transmitted, corresponding to DCL frequencies from 512 kHz to 8.192 MHz. The SBCX needs no pin strapping to indicate the actual bit rate, because each rising edge of FSC resets ...
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IOM -2 Interface Line Card Frame Structure The SBCX in line card applications (LT-S and LT-T) supports bit rates from 256 kbit/s to 4096 kbit/s corresponding to DCL frequencies from 512 kHz to 8.192 MHz. The typical IOM-2 ...
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IOM -2 Interface Terminal Frame Structure In TE mode the SBCX provides a data clock DCL with a frequency of 1536 kHz consequence the IOM-2 interface provides three channels each with a nominal data rate of ...
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C/I0 in IOM Channel two bits for the 16 kbit/s D-channel C/I: The four command/indication (C/I) bits are used for controlling of the layer-1 functions (activation/deactivation and additional control functions) by ...
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IOM -2 Interface Command / Indicate Channel The Command/Indicate channel (C/I channel) is used to control the operational status of the SBCX and to issue corresponding indications. C/I channel codes serve as the main link between the SBCX ...
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Table 3 C/I Abbreviations Code Description AI Activation Indication AI8 Activation Indication with priority 8 AI10 Activation Indication with priority 10 AIL Activation Indication Loop AR Activation Request AR8 Activation Request with priority 8 AR10 Activation Request with priority 10 ...
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PEB 2070 and C/I-Channel Programming P STCR = 70 CIX0 = 47 CISQ ISTA = 04 CICO = 1 CIR0 = 06 CICO = 0 CIR0 = 04 Figure 35 C/I-Channel Use with the ICC (all data values hexadecimal) The ...
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PEB 2055 and C/I-Channel Programming µP MADR = C 7 MAAR = 08 MACR = 48 SFI 1 = ISTA = 40 CIFIFO = 88 MAAR = 88 MACR = C8 MADR = 7 C Figure 36 C/I-Channel Use with ...
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IOM -2 Interface Monitor Channel The monitor channel represents a second method to access SBCX specific features. Features of the monitor channel are supplementary to the C/I-channel. The SBCX uses the monitor channel for both, local programming and local ...
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ICC and Monitor Channel Programming µP MOCR = 00 STAR MOSR = 00 MOX0 = 1. Byte MOCR = 03 MOCR = 02 MOX0 = 2. Byte MOSR = 02 MOCR = 0A MOSR = 08 MOR ...
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The P starts the transfer procedure after having confirmed the monitor channel being inactive. The first byte of monitor data is loaded into the transmit register. Via the Monitor Control Register MOCR-monitor interrupts are enabled and control of the MX-bit ...
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EPIC and Monitor Channel Programming µP STAR = 05 MFFIFO = 1. Byte MFFIFO = 2. Byte STAR = 04 MFTC 1 MFSAR = XX CMDR = 08 STAR = 12 MFFI ISTA = 70 STAR = ...
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Monitor Procedure “Timeout” (TOD) The SBCX offers an internal reset (monitor procedure “Timeout”) for the monitor routine. This reset function transfers the monitor channel into the idle state (MR and MX set to high) by issuing “EOM” (End of ...
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The structure of a MON-2 message is similar: Table 5 MON-2 Structure MON-2 The following table gives an overview of the S/Q messages available: Table 6 MON-1, MON-2 Functions S1-MON-1 S1-MON-1 S2-MON-2 S2-MON-2 ...
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MON-8 Commands (Internal Register Access) The PEB 2081 V 3.4 contains six internal registers. Access to these registers is only possible via the IOM-2 monitor channel. The following registers are implemented in the SBCX V 3.4: Identification Register Configuration ...
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MON-8 Identification Register The contents of the identification register differs with the SBCX version. PEB 2081 V3.3 and 3.4 is identified with the code 42 Hex Former PEB 2081 versions identify themselves with the following codes: PEB 2081 Identification ...
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LP Loop Transparency. In case analog loop-backs are closed with C/I = ARL or bit SC in the loop-back register, the user may determine with this bit, whether the data is forwarded to the S/T-interface outputs (transparent) or not. The ...
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SC Close complete analog loop-back (2B+D) close to the S/T-interface. Corresponds to C/I = ARL. Transparency is optional. Operational in LT-S and NT mode. IB1 Close the loop-back for B1 channel close to the IOM-2 interface (i.e. loop-back S/T data). ...
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MON-8 SM/CI Register This multifeature register allows access to the C/I channel, sets the MAI interface mode and controls the monitor time-out and S/G bit function. C/I Allows the user to access the C/I channel if the CIH bit ...
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S/T-Interface The S-interface establishes a direct link between terminals and the exchange or NT. It consists of two pairs of copper wires: one for the transmit and one for the receive direction. The PEB 2081 inputs and outputs are ...
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Maintenance Auxiliary Interface (MAI) The SBCX provides eight pins, MAI (7:0), for maintenance aids and general interface purposes. Two major operational modes are supported: MAI Interface: I/O Mode P Mode The I/O mode offers two additional alternatives: I/O Specific ...
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Table 11 I/O Specific MAI Interface LT-S MAI 0 i:NT-STAR MAI 1 i:MPR1 MAI 2 i:MPR2 MAI 3 i:MPR3 MAI 4 o:MPR4 MAI 5 o:MPR5 MAI 6 o:MPR6 MAI 7 o:MPR7 NT-STAR LT-S configurations optionally the NT-STAR ...
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A LOW level at this input (D-channel collision must be programmed via DH bit in IOM channel register) prevents transmission of INFO1 after AR (activation-request) has been received on the C/I channel. An activation initiated by the network side (reception ...
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Standard I/O Mode In standard I/O mode no pins are reserved for special signals. Thus four input and four output lines are available to the user for general purpose interface applications. Do not use this mode however when in ...
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P MAI Mode The interface structure is adapted to the register structure of the IEPC. It consists of three data bits MAI0 … 2, two address bits MAI4,5, read and write signals MAI6 and MAI7 respectively as well as ...
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Read from P Interface (single address): IOM -2 MON-8 Config: MAIM MON-8 MAI: MON-8 MAI: 3. Read from P Interface (complete address scan): The following example assumes that a device capable of decoding addresses is connected to the P ...
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Control Procedures Control procedures describe the commands and messages required to control the PEB 2081 in different modes and situations. This chapter shows the user how to activate and deactivate the device under various circumstances. In order to keep ...
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Activation Initiated by Terminal (TE/LT-T) The following scheme illustrates how a terminal initiates an activation. As described in the previous section the command C/I “AI” needs to be sent at the end if the device is operating in NT ...
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D-Channel Access Control D-channel access control was defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Figure 41 illustrates that collisions are possible on the TIC- and the S-bus. ICC ...
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TIC Bus D-Channel Control in TE The TIC bus was defined to organize D- and C/I channel access when two or more D- and C/I channel controllers can access the same IOM-2 timeslot. Bus access is controlled by five ...
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S-Bus Priority Mechanism for D-Channel The S-bus access procedure specified in ITU I.430 was defined to organize D-channel access with multiple TEs connected to a single S-bus. To implement collision detection the D (channel) and E (echo) bits are ...
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Application 1. Priority Class 8/10 Selection with NT Initiated Activation TE IOM -2 C/I DC (1111b) C/I DI (1111b) C/I RSY (0100b) C/I AR (1000b) C/I AI (1100b) C/I AR8 (1000b) D: transfer HDLC frame C/I AR10 (1001b) D: transfer ...
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S-Bus D-Channel Control in LT-T In LT-T mode the SBCX is primarily considered point-to-point configuration. In these configurations no S-bus D-channel collision can occur, therefore the default setting after resetting the SBCX is transparent (IOM-2 ...
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After D-channel data transmission is completed the controller sets the BAC bit to ONE. SBCX pulls S/G bit to ZERO. SBCX transmits non-inverted echo (E = D). Note: 1. Although the D-channel controller releases the TIC bus for one IOM-2 ...
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R IOM -2 Master Device Exchange (TE Mode 1.536 MHz) Reset External Access A S/G = A/B Figure 42 Data Flow for Collision Resolution Procedure in Intelligent NT The SBCX uses the Echo-bit of the ...
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IOM -2 Interface Channel Switching In order to realize intelligent NT configurations the SBCX provides basic switching functions. These include: Individual channel transfer from IOM-2 channel 1 to IOM-2 channel 0. Individual channel reversion on input and output lines. ...
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The following four examples illustrate typical switching operations. Three of them are programmed in the “IOM-2 Channel” register, example No. 4 makes use of the “Loop-back” register. All register bits related to the channel are set to ...
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Connection U-TE (B1) SBCX B2L = 1 R IOM -2 Reg. 4. Connection TE1 (B1) SBCX IB1 Loopback Reg. Semiconductor Group Exchange, B2 (e.g. TE1) B2 IDP0 B1 IDP1 DU ...
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Maintenance Functions This chapter summarizes all features provided by the SBCX V 3.4 to support system maintenance and system measurements. Two main groups may be distinguished: – maintenance function to close and open test loop-backs. – test modes required ...
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Complete Loop-Backs (No. 2, No. 3, and No. A) Internal Loop-Backs In a complete loop, all three channels (B1, B2 and D) are looped back at the S/T-interface “transparent loop” the data are also sent forward (in ...
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External Loop-Backs In order to enable complete systems diagnostics (including transformers etc possible to close an external loop at the four wire S/T-interface. In that case the signal transmitted onto the line is fed to the receiver. PEB ...
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Single Channel Loop-Backs (No. 4, No. B1/2, No. C) With the S/T-interface being in the activated state single channel loops are possible for the B channels in all directions, i.e. from the S/T-interface to the IOM-2 interface and back ...
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Monitoring of Illegal Code Violations The SBCX V 3.4 offers the option of monitoring the S-bus for illegal code violations. If bit RCVE in the configuration register is set to ONE a Far End Code Violation (FECV) function according ...
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Pulse Mask Measurement Pulse Mask defined in ITU I.430 section 8.5.3 S-interface is terminated with: – 50 (TE and NT equipment) – 400 (TE equipment only) – 5.6 (TE equipment only) B-channel loop is neccessary IB1, IB2 in Loopback ...
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Possible problems: – Impedance measurement with 96 kHz exceeds current limit interface circuitry between transformer and protection circuit (see also S/T-interface recommendation in chapter 4). 3.4.3.6 NT/TE Timing Extraction Jitter Requirement defined by ITU I.430 sections 8.2.2 and 8.3. TE ...
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TE and NT Longitudinal Conversion Loss (LCL) Requirement defined by ITU I.430 in section 8.5.6.1. Measurement conditions: – all possible power feeding conditions. – all possible connections set to ground. – 100 termination across transmit and receive ports. Requirements: ...
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Technical Description Chapter 4, “Technical Description”, is structured similar to chapter 3 in order to facilitate cross- referencing. Chapter 4 is dedicated to technical information only. It describes the interfaces, control procedures, maintenance functions and the analog line port. ...
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Multiframe Marker In NT and LT-S mode the signaling of the multiframe identification on the S-interface is performed automatically by the SBCX. The multiframe generation can be disabled by pin strap (NT pin MAI1 tied to high programming ...
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IOM -2 Dynamic Characteristics In case the period of signals is stated the time reference will all other cases 0.8 V (LOW) and 2.0 V (HIGH) thresholds are used as reference. The following two ...
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Table 12 Timing Characteristics of the IOM -2 Interface TE Mode Parameter Frame sync delay Bit clock delay Data delay Data setup Data hold Data clock high Data clock low Data clock period Semiconductor Group Symbol Limit Values min. typ. ...
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Timing Characteristics IOM -2 Interface LT-S and LT-T Mode IOM lost Channels (...B*-Channel) FSC ( ) DCL ( ) t DS IPD IPD ( Figure 50 Timing of the IOM ® ...
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Table 13 Timing Characteristics of the IOM -2 Interface NT / LT-S and LT-T Mode Parameter Data clock high Data clock low Frame sync hold Frame sync setup Frame sync high 1) Frame sync low Data delay to clock Data ...
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Timing Characteristics CEB (NT / LT-S) The form and the AC characteristics of the CEB input/output (pin and LT-S mode) are given in the following figures for the case of two S/T-interfaces having a minimum loop ...
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The influence of more SBCXs connected to the CEB line is illustrated in the following figure. Two stations one with minimal frame delay (station A), the second with maximum frame delay (station B) determine the echo bit to be sent ...
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Command/Indicate Channel Structure 4 bit wide, located at bit positions 27-30 in each time-slot. Verification Double last-look criterion. A new command or indication will be recognized as valid after it has been detected in two successive IOM frames. Codes ...
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Table 15 C/I Codes Code LT RES TM1 TM2 – – ...
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Monitor Channel Modes Automode and non-auto mode are available. These affect MON-1 and MON-2 messages only and will be described in the sections dealing with these monitor categories. Structure The structure of the monitor channel is 8 bit wide, ...
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Handshake Procedure The monitor channel is full duplex and operates on a pseudo-asynchronous basis, i.e. while data transfer on the bus takes place synchronized to frame synchronization, the flow of monitor data is controlled by the MR and MX ...
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Standard Transmission Procedure 1. The first byte of monitor data is placed by the external controller (e.g. ICC, EPIC) on the IDP1 line of the SBCX and MX is activated (LOW; frame No 1). 2. The SBCX reads the data ...
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Error Treatment and Transmission Abortion In case the SBCX does not detect identical monitor messages in two successive frames, transmission is not aborted. Instead the SBCX will wait until two identical bytes are received in succession. Transmission is aborted only ...
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MON-1, MON-2 Commands (S/Q Channel Access) Function: MON-1 and MON-2 commands provide access to the SBCX internal S/Q registers. MON1 controls the S In order to synchronize onto multiframing pulses (TE, LT-T modes) and issue monitor- messages (NT, LT-S ...
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Non-Auto Mode In non-auto mode only MON-1 functions to access the S messages (for S channel access) are ignored non-auto mode monitor messages are only released after new data has been received. In this mode traffic on the ...
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MON-8 Commands (Register Access) Function: MON-8 commands provide access to the SBCX internal registers. MON-8 commands allow to configure the SBCX. With the exception of the identification register (read only) all registers have read/write capability. In case a write ...
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MON-8 Identification Register – (Read, Address: 0 Format: 0 Initial Value Older SBCX Versions identify themself with the following IDs: Versions Versions: B1 and 2 MON-8 Configuration Register – ...
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Table 16 (cont’d) FSMM NT/LT-S mode: 0: normal operation 1: Finite state machine interchanged (LT-S MAIM MAI pins mode: 0: I/O-specific or standard I/O MAI interface 1: P interface mode for MAI interface MFD Multi-frame disable (write): 0: All multi-frame ...
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MON-8 IOM-2 Channel Register - (Read/Write, Address: 3 Format: B1L Initial value Table 18 Bit-name Description B1L B1 channel location 1) 0: normal 1: B1 channel in IOM-2 channel 0 B2L B2 channel location 0: normal 1) 1: ...
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MON-8 SM/CI Register – (Read/Write, Address: 4 Format: CI3 Initial value: CI Table 19 Bit-name Description CI (3:0) CI channel When CIH-bit is set to one the commands are input in the monitor channel CI (3:0) The indication ...
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MON-8 MAI Pin Register - (Read/Write, Address: 5 Format: MPR7 Initial value Bit-name Description MPR (7:0) access to MAI(7:0) pins if MAI interface is set to standard I/O or I/O specific function mode. In case the P interface ...
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S/T-Interface Transmission over the S/T-interface is performed at a rate of 192 kbit/s. Pseudo-ternary coding with 100 % pulse width is used (see following section). 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing ...
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Figure 56 S/T -Interface Line Code (without code violation) A standard S/T frame consists of 48 bits. In the direction TE two bit offset. For details on the framing rules please refer to ITU ...
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F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – B1 B1-Channel Data Bit – B2 B2-Channel Data Bit – A Activation ...
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S/T-Interface Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer 1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q-channel). The Q bits are defined to be the ...
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In TE and LT-T mode the SBCX identifies the Q-bit position (after multi-frame synchronization has been established) by waiting for the F (F [NT TE] = binary ONE). After successful identification, the Q data will be inserted at the A ...
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Standard I/O Mode Provides four input and four output lines. Interface access via MON-8 MAI pin register. The MAI pins may be written by the following 2-byte sequence via the IOM-2 monitor channel: write command (access to MAI Pin ...
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P MAI Mode In case the P mode is selected (MIO, MAIM bits) the following timing applies for read and write operations. Write Access ... ... D 2 Figure 58 Dynamic ...
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Table 23 Dynamic Characteristics of Data Port Parameter Signal Write Width Low Address Delay A0 … 1 Read/Write Data Delay Write Start D0 … 2 Data Delay Write End Setup Data Read Hold Data Read Read Width Low Interrupt For ...
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Control Procedures Chapter 4.2 illustrates the interactions between two SBCX stations during activation and deactivation. The behaviour of a single SBCX station is described in the state diagrams of chapter 4.3. With a knowledge of the state machine and ...
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Complete Activation Initiated by Exchange (LT-S) The following figure depicts the procedure if activation has been initiated by the exchange side and the exchange SBCX is set to LT-S mode. R IOM - RSY AR AI AR8 ...
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Complete Activation Initiated by Exchange (NT) Figure 61 illustrates the activation procedure when the exchange starts the activation. R IOM -2 TE/LT RSY AR AI AR8 / 10 SBCX Figure 61 Complete Activation Initiated by Exchange (NT) ...
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Complete Activation Initiated by Terminal The following figure illustrates the activation process if started from the terminal side (or LT-T). This illustration only shows the part of the activation which differs from the previously described exchange initiated activation. R ...
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Complete Deactivation A deactivation will always be initiated by the exchange side. R IOM - (AR Figure 63 Deactivation Procedure For the NT case (DCL = 512 kHz) the deactivation procedure is shown in ...
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FSC DCL DU D Figure 64 Deactivation of the IOM -2 Interface in the NT (DCL = 512 kHz) Semiconductor Group 127 ...
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State Machine State machines are the key to understanding the SBCX in different operational modes. They include all information relevant to the user and enable him to understand and predict the behaviour of the SBCX. The informations contained in ...
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The state may be left by either of the following methods: – Leave for the state “F3 power up” after synchronous or asynchronous “TIM” code has been received on IOM. – Leave for state “F5/8 unsynchron” after any kind of ...
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TE/LT-T Modes State Diagram Pend. Act RSY X i4 F5/8 Unsynchron Synchronized Activated ...
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DI ARL ARL Loop A Closed i3 i3 RSY ARL AIL Loop A Activated DI i3 Note state “loop A activated” the internal signal, the external signal is I0. Figure 67 State Diagram of the TE/LT-T ...
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TE/LT-T Modes Transition Criteria The transition criteria used by the SBCX are described in the following sections. They are grouped into: – C/I commands – Pin states – Events related to the S/T-interface 4.3.1.2.1 C/I Commands AR8 Activation Request ...
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Pin States Pin-RES Pin-Reset. Corresponds to a low level at pin RST. At power up, a reset pulse (RST low active) of minimum 1 s should be applied to bring the SBCX to the state “reset”. After that the ...
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C/I Indications Abbreviation Indication DR Deactivate Request RES Reset TM1 Test mode 1 TM2 Test mode 2 SLIP Slip detected (LT-T only) RSY Resynchronization during level detect MAIC MAI change DIS Disconnected PU Power up AR Activate request ARL ...
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States TE/LT-T Mode F3 power down This is the deactivated state of the physical protocol. The received line awake unit is active mode, clocks are disabled. F3 power up This state is dependent of the logical level ...
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F7 slip detected When a slip is detected between the S/T-interface clocking system and the IOM-2 interface clocks (phase wander greater than 50 s, data may be disturbed programmed in the configuration register) the SBCX enters ...
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LT-S Mode State Diagram RST TIM RES Reset i0 * RES DC Any State Notes: 1. ARD stands for AR or ARL 2. NT star: transition from ‘G2 pend. act.’ to ‘G3 activated’ takes place when the first branch ...
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LT-S Mode Transition Criteria The transition criteria used by the SBCX are described in the following sections. They are grouped into: – C/I commands – Pin states – Events on the S/T-interface. 4.3.2.2.1 C/I Commands AR Activation Request. This ...
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Transmitted Signals and Indications in LT-S Mode The following signals and indications are issued on the IOM-2 and S/T-interface. 4.3.2.3.1 C/I Indications Abbreviation Indication (upstream) LT-S mode TIM Timing RSY Resynchronizing MAIC MAI change AR Activate request CVR Far-end-code-violation ...
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States LT-S Mode G1 deactivated The SBCX is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. G2 pending activation As a result of an INFO 0 detected ...
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NT Mode State Diagram RST TIM RES Reset i0 * RES Any State AID RSY ARD G2 Lost Framing S RSY DR RSY RSY G3 Lost Framing Notes: 1. ARD = AR or ARL ...
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NT Mode Transition Criteria The transition criteria used by the SBCX are described in the following sections. They are grouped into: – C/I commands – Pin states – Events or the S/T-interface. 4.3.3.2.1 C/I Commands AR Activation Request. This ...
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Pin States Pin-RES Pin Reset. Please refer to section 4.3.1.2.2 for details. Pin-NT-STAR Device operates in NT-STAR mode. In this mode detection of INFO 3 is not essential for a transfer to “G2 wait for AI”. The transfer will ...
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S/T-Interface Signals I0 INFO 0 I2 INFO 2 I4 INFO 4 It Pseudo ternary pulses at 2-kHz frequency (TM1). Pseudo ternary pulses at 96-kHz frequency (TM2). 4.3.3.4 States NT Mode G1 Deactivated The SBCX is not transmitting. No signal ...
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G4 Pend. Deact. This state is triggered by a deactivation request DR, and is an unstable state. Indication DI (state “G4 wait for DR”) is issued by the SBCX when: either INFO0 is received or an internal timer of 32 ...
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Reset 4.4.1 C/I Command RES Reset of the layer-1 state machine. SBCX is transmitting info 0 and does not react on received infos. RES is an unconditional command. 4.4.2 Hardware Reset RST All SBCX registers are set back to ...
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Maintenance Functions The technical description of maintenance functions follows in the next sections. The sections “Test Modes” and “System Measurement” of chapter 3 have not been included as they contain primarily application information. 4.5.1 Test Loop-Backs 4.5.1.1 Complete Loop-Backs ...
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Single Channel Loop-Backs (No. 4, No. B Function Partial loop-backs may be closed on the IOM-2 or the S/T-interface. Loop-backs No. B No. C (NT1) and No. 4 (terminal and PBX) are closed on IOM-2 and loop-back the data ...
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Clock Generation and Clock Characteristics This section deals with clock generation requirements for slave and master modes and the characteristics of clock signals produced by the SBCX. The following requirements apply to all operational SBCX modes: Clock Requirements Master ...
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Propagation Delay The delay from the IOM-2 to the S/T-interface and vice versa is independent of the direction. Table 26 Parameter Signal delay S IOM Signal delay IOM S The requirements for input jitter and the operation of the implemented ...
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Figure 71 Clock System of the SBCX in NT and LT-S Mode 4.6.1.2 Jitter Requirements According to ITU I.430 the maximum jitter output sequence bit period (260 ns). Two cases need to ...
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LT-T and TE Mode 4.6.2.1 Receive PLL in TE and LT-T Mode The Receive PLL (RPLL) recovers bit timing from the detector’s output signal and provides a synchronous 1536-kHz clock (adaptive timing recovery). Divided by eight this clock is ...
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Elastic Buffers in LT-T Mode 4.7.1 Elastic Buffer In LT-T mode the SBCX provides a buffer designed as a wander-tolerant system. This is required because the SBCX is a slave to both interfaces and the data clocks of the ...
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Table 27 Clock Characteristics TE Mode (cont’d) Pin Parameter X0 and Output: 16 kHz C/W/P- Output: 16 kHz bit = ‘1’ Output: 16 kHz Duty Ratios Table 28 TE Clock Signals (IOM -2 mode) Application DCL TE o:1536 kHz 1:1 ...
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Table 29 Clock Characteristics LT-T Mode Pin Parameter X3 Output: 1536 kHz Output: 1536 kHz Output: 1536 kHz 4.7.2 Recommended Oscillator Circuit In all applications the user has the choice to supply the master clock by crystal ...
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Analog Line Port The analog part of the SBCX consists of two major building blocks: – Receiver – Transmitter In addition external circuitry is required to connect both transmitter and receiver to the S/T-interface. The following three sections describe ...
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Figure 77 Receiver Thresholds The peak detector requires maximum reach the peak value while storing the peak level for at least 250 s (RC > 1 ms). The additional level detector for power up/down control works with ...
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Transmitter Characteristics The transmitter stage consists of two identical current limited voltage sources, one for each polarity of output pulses. The voltage source guarantees the required output voltages on 50 loads whereas the 5.6 load is current limited to ...
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S/T-Interface Circuitry In order to comply to the physical requirements of ITU recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the SBCX needs some additional circuitry. The transmitter of the SBCX is identical ...
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The receiver of the SBCX is symmetrical receive path. Although it is possible to place two single 10 k resistors either between transformer and diode circuit or between chip and diode circuit it is preferable to split the ...
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S/T-Interface Transformer The SBCX is connected to the S/T-interface by the use of a 2:1 transformer for the receiver and the transmitter respectively. The line side of the transformer should be centre tapped for the phantom power supply. The ...
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Line Overload Protection (Transmitter, Receiver) In order to protect the SBCX from over-current pins SX1, SX2 and SR1, SR2 are equipped with internal protection circuits. The following figures indicate what limits may not be exceeded to avoid permanent damage ...
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Transmitter Input Current The destruction limits for negative input signals ( are given in the following figure 0.5 0.05 -10 10 Figure 84 Destruction Limits Transmitter Input Current Semiconductor Group and for positive ...
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Receiver Input Current R The destruction limits ( 300 ) are given in the following figure 0.1 0.01 0.005 -10 10 Figure 85 Destruction Limits Receiver Input Current Semiconductor Group Technical Description - ...
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Electrical Characteristics All characteristics given are valid under the following conditions unless otherwise indicated – ° 5.1 Absolute Maximum Ratings Ambient temperature under bias Storage temperature Voltage on ...
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Power Supply 0. The analog receiver part has a power supply rejection of better than – 100 kHz as shown in the following figure. However, due to the digital ...
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DC Characteristics Pin Parameter All pins Input low voltage except Input high voltage SX1, 2; SR1, 2; Output low voltage XTAL1, 2 IDP1, 0 Output low voltage All pins Output high voltage except SX1, 2; SR1, 2; Input leakage ...
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Power Consumption Parameter 50 chip load inputs bin. ZEROs in B1 and B2 channel No output loads 0 chip load and INFO2 transmitted Note: For power consumption under emergency conditions ...
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Package Outlines P-DIP-28-3 (Plastic Dual In-Line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Semiconductor Group Package Outlines 169 Dimensions in mm ...
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P-LCC-28-1 (Plastic Leaded Chip Carrier Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group Package Outlines 170 Dimensions in mm ...
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Appendix ...
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The appendix comprises three sections: Appendix A contains a collection of Delta- and Errata Sheets published for the SBCX, PEB 2081. These allow the user to identify technical differences between the latest SBCX versions. Appendix B summarizes the requirements of ...
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Appendix A 7.1 Delta and Errata Sheets ...
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S/T Bus Interface Circuit Extended (SBCX) Delta Sheet Differences between PEB 2081 Version 3.4 and Version 3.3 ® 1. Programming the IOM the LT-T mode has no influence on the indication. The indication in the state “activated” is always 1100 ...
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S/T Bus Interface Circuit Extended (SBCX) Errata Sheet for the Version 3.3 1. Activation Indication After programming the IOM-2 Channel Register (address the LT-T Mode, the indication of the state “activated” may be 0100 (RSY) instead of 1100 ...
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S/T Bus Interface Circuit Extended (SBCX) Errata Sheet for the Version 3.4 1. Statemachine Toggling Receiving INFOX LT-T mode the statemachine may toggle betweenstateF5/F8 and state F6 or between state F5/F8 and state F7. While toggling the ...
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Appendix B 7.2 External Components Information ...
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Transformers and Crystals Vendor List Crystals: Frischer Electronic Schleifmühlstraße 2 D-91054 Erlangen, Germany KVG Waibstadter Straße 2-4 D-74924 Neckarbischofsheim 2, Germany Tel.: (…7263) 648-0 NDK 2-21-1 Chome Nishihara Shibuya-Ku Tokyo 151, Japan Tel.: (03)-460-2111 or Cupertino, CA, USA Tel.: (408) ...
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Universal Microelectronics Vacuumschmelze (VAC) Grüner Weg 37 Postfach 2253 D-63412 Hanau 1, Germany Tel.: (…6181) 380 or 186 Wood Avenue South Iselin, NJ OB830, USA Tel.: (908) 603 5905 Valor Steinstraße 68 D-81667 München, Germany Tel.: (…89) 480 2823 Fax.: ...
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List of Transformer Manufacturers and S The following list contains transformers recommended by different manufacturers for use with Siemens S transceivers. 0 Transformers marked with shown positive test results concerning pulse shape and impedance requirements of ETS 300 012. This ...
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Appendix C 7.3 Quick Reference Guide ...
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Modes of Operation Configuration LT-S Point-Point/Bus Pin Mode 1 X0 i:TS0 X1 i:TS1 X2 i:TS2 X3 i/o:CEB MAI0 i:NT-STAR MAI1 i:MPR1 MAI2 i:MPR2 MAI3 i:MPR3 MAI4 o:MPR4 MAI5 o:MPR5 MAI6 o:MPR6 MAI7 o:MPR7 FSC i:8kHz DCL i:512-8192kHz i: input i: ...
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Modes of Operation (cont’d) Configuration LT-S Point-Point/Bus Register Configuration 0 Bit 0 (Mode) [0] 1) Configuration 0/1 Bit 1 (C/W/P) [0] Configuration 0/1 Bit 5 (FSMM) [0] Configuration 0 Bit 6 (MAIM) [0] SM/CI 0 Bit 0 (MIO) [0] SM/CI ...
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MON-8 Configuration Register – (Read/Write, Address: 1 Format: MFD Initial Value Bit-name Description V MODE Pin MODE = DD C/W/P LT-S and NT mode: Configuration 0: point-to-point or extended passive bus configuration (adaptive timing recovery mode ...
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MON-8 Loop-Back Register – (Read/Write, Address: 2 Format: AST Initial value Bit-name Description AST ASynchronous Timing In NT and LT-S mode; only NT state machine 0: LT-S: command TIM in C/I NT: asynchronous wake up 1: LT-S: asynchronous ...
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MON-8 IOM -2-Channel Register - (Read/Write, Address: 3 Format: B1L Initial value Bit-name Description B1L B1 channel location 0: normal channel in IOM-2 channel 0 B2L B2 channel location 1) 0: normal 1: B2 channel ...
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MON-8 SM/CI Register – (Read/Write, Address: 4 Format: CI3 Initial value: CI Bit-name Description CI (3:0) CI channel When CIH-bit is set to one the commands are input in the monitor channel CI (3:0). The indication can always ...
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MON-8 MAI Pin Register - (Read/Write, Address: 5 Format: MPR7 Initial value Bit-name Description MPR (7:0) access to MAI(7:0) pins if MAI interface in standard I/O or I/O specific function mode In case the P interface was selected ...
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TE/LT-T Modes State Diagram Pend. Act RSY X i4 F5/8 Unsynchron Synchronized Activated i3 i4 Slip SLIP X i2 ...
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LT-S Mode State Diagram RST TIM RES Reset i0 * RES DC Any State Notes: 1. ARD stands for AR or ARL 2. NT star: transition from ‘G2 pend. act.’ to ‘G3 activated’ takes place when the first branch of ...
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NT Mode State Diagram RST TIM i0 RES Any State RSY G2 Lost Framing i2 RSY RSY G3 Lost Framing i2 Notes: 1. ARD = AR or ARL 2. AID = AI or AIL 3. Transition takes place as soon ...
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C/I Codes Code LT RES TM1 TM2 – – – ...