UPD78P058YGC-3B9 NEC, UPD78P058YGC-3B9 Datasheet
UPD78P058YGC-3B9
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UPD78P058YGC-3B9 Summary of contents
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Application Note 78K/0 Series 8-bit Single-chip Microcontroller Basic (III) PD78054 subseries PD78064 subseries PD78078 subseries PD78083 subseries PD780018 subseries PD780058 subseries PD780308 subseries PD78058F subseries PD78064B subseries PD78075B subseries PD78098B subseries Document No. U10182EJ2V0AN00 (2nd edition) Date Published October 1997 ...
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[MEMO] ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...
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... Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • ...
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Page Throughout Addition of following products as target products: PD780018, 780018Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY PD78052(A), 78053(A), 78054(A) PD78062(A), 78063(A), 78064(A) PD78081(A), 78082(A), 78P083(A), 78081(A2) PD78058F(A), 78058FY(A) PD78064B(A) Deletion of following ...
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Readers This Application Note is intended for use by engineers who understand the functions of the 78K/0 series and wish to design application programs with the following subseries products: • Subseries Notes 1. Under development Remarks 1. The PD78052(A), 78053(A), ...
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Purpose This Application Note is to deepen your understanding of the basic functions of the 78K/0 series by using program examples. Note that the programs and hardware configuration shown in this document are only examples and not subject to mass ...
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How to Read This Manual Although this Application Note explains the functions of the 78K/0 series products, the functions of some products in each subseries differ from those of the others. Subseries Chapter CHAPTER 1 GENERAL CHAPTER 2 FUNDAMENTALS OF ...
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The (A)-model and standard models differ only in quality grade. The PD78081(A2) differs from standard models and (A)-models in terms of supply voltage and operating temperature range. For details, refer to the individual Data Sheet. In this document, read (A)-models ...
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... Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. • Application Field Related documents Some of the related documents listed below are preliminary versions but not so specified here. ...
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Documents dedicated to product (1) PD78054 subseries Document Name PD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet PD78P054 Data Sheet PD78P058 Data Sheet PD78054, PD78054Y Subseries User’s Manual PD78054 Subseries Special Function Register Table PD78052(A), 78053(A), 78054(A) Data Sheet ...
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PD78078 subseries Document Name PD78076, 78078 Data Sheet PD78P078 Data Sheet PD78078 Subseries User’s Manual PD78078 Subseries Special Function Register Table (6) PD78078Y subseries Document Name PD78076Y, 78078Y Data Sheet PD78P078Y Data Sheet PD78078, 78078Y Subseries User’s Manual PD78078Y ...
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PD780018 subseries Document Name PD780016, 780018 Preliminary Product Information PD78P0018 Preliminary Product Information PD780018, 780018Y Subseries User’s Manual (10) PD780018Y subseries Document Name PD780016Y, 780018Y Preliminary Product Information PD78P0018Y Preliminary Product Information PD780018, 780018Y Subseries User’s Manual (11) PD780058 ...
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PD780308Y subseries Document Name PD780306Y, 780308Y Data Sheet PD78P0308Y Preliminary Product Information PD780308, 780308Y Subseries User’s Manual (15) PD78058F subseries Document Name PD78056F, 78058F Data Sheet PD78P058F Data Sheet PD78058F(A) Data Sheet PD78058F, 78058FY Subseries User’s Manual (16) PD78058FY ...
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PD78070A, 78070AY subseries Document Name PD78070A Data Sheet PD78070AY Data Sheet PD78070A, 78070AY User’s Manual PD78070A PD78070AY (19) PD78075B subseries Document Name PD78074B, 78075B Data Sheet PD78075B, 78075BY Subseries User’s Manual (20) PD78075BY subseries Document Name PD78074BY, 78075BY Data ...
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CHAPTER 1 GENERAL ................................................................................................................... 1.1 Product Development of 78K/0 Series ....................................................................... 1.2 Features of 78K/0 Series .............................................................................................. CHAPTER 2 FUNDAMENTALS OF SOFTWARE .......................................................................... 2.1 Data Transfer .................................................................................................................. 2.2 Data Comparison ........................................................................................................... 2.3 Decimal Addition ........................................................................................................... 2.4 Decimal Subtraction ...................................................................................................... 2.5 ...
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Interface with OSD LSI ( PD6451A) ............................................................................ 8.3 Interface in SBI Mode .................................................................................................... 8.3.1 Application as master CPU ............................................................................................. 8.3.2 Application as slave CPU ................................................................................................ 8.4 Interface in 3-Wire Serial I/O Mode ............................................................................. 8.4.1 Application as master CPU ............................................................................................. ...
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Fig. No. 1-1. Block Diagram of PD78054 Subseries ....................................................................................... 1-2. Block Diagram of PD78054Y Subseries .................................................................................... 1-3. Block Diagram of PD78064 Subseries ....................................................................................... 1-4. Block Diagram of PD78064Y Subseries .................................................................................... 1-5. Block Diagram of PD78078 Subseries ....................................................................................... 1-6. Block Diagram ...
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Fig. No. 3-7. Format of Oscillation Mode Select Register ( PD780018, 780018Y subseries) ............................................................................................... 3-8. Format of Clock Select Register 1 ( PD78098, 78098B subseries) ............................................ 3-9. Format of Clock Select Register 2 ( PD78098, 78098B subseries) ............................................ 3-10. Example ...
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Fig. No. 6-3. Format of Timer Clock Select Register 1 ( PD780018, 780018Y subseries) .............................. 6-4. Format of 8-Bit Timer Mode Control Register .............................................................................. 6-5. Format of 8-Bit Timer Output Control Register ............................................................................ 6-6. Format of Port Mode Register 3 ...
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... Format of Serial Interface Pin Select Register ( PD780058 and 780058Y Subseries) ............... 8-24. Format of Serial Interface Pin Select Register ( PD780308 and 780308Y Subseries) ........................................................................................ 8-25. Pin Configuration of PD6252 ..................................................................................................... 8-26. Example of Connection of PD6252 ............................................................................................ 8-27. Communication Format of PD6252 ............................................................................................ 8-28. Example of Connection between PD6252 and I LIST OF FIGURES (4/6) Title 2 C Bus Mode ................................................... – vi – Page 212 213 215 216 ...
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... Example of Connecting PD6451A ............................................................................................. 8-31. Communication Format of PD6451A ......................................................................................... 8-32. Example of Connection in SBI Mode ........................................................................................... 8-33. Communication Format in SBI Mode ........................................................................................... 8-34. ACK Signal in Case of Time out .................................................................................................. 8-35. Testing Bus Line .......................................................................................................................... 8-36. Example of Connection in 3-Wire Serial I/O Mode ...................................................................... 8-37. Communication Format in 3-Wire Serial I/O Mode ...................................................................... 8-38. Output of Busy Signal .................................................................................................................. 8-39. Communication Block Diagram .................................................................................................... 8-40. Communication Format ................................................................................................................ 8-41. Reception Format ........................................................................................................................ 8-42. ...
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... Example of Static LCD Driving Waveform ................................................................................... 12-11. Display Pattern of 4-Time Division LCD and Electrode Wiring .................................................... 12-12. Connections of 4-Time Division LCD Panel ................................................................................. 12-13. Example of Connecting LCD Drive Power in 4-Time Division Mode (with external divider resistor, V 12-14. Example of 4-Time Division LCD Driving Waveform .................................................................... 13-1. Key Matrix Circuit ......................................................................................................................... LIST OF FIGURES (6/6) ...
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Table. No. 1-1. Functional Outline of PD78054 Subseries ................................................................................. 1-2. Functional Outline of PD78054Y Subseries ............................................................................... 1-3. Functional Outline of PD78064 Subseries ................................................................................. 1-4. Functional Outline of PD78064Y Subseries ............................................................................... 1-5. Functional Outline of PD78078 Subseries ................................................................................. 1-6. Functional Outline ...
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Table. No. 8-7. Pin Function of PD6252 ............................................................................................................. 8-8. PD6252 Commands ................................................................................................................... 8-9. Signals in SBI Mode ..................................................................................................................... 8-10. Relations between Main System Clock and Baud Rate (at f 9-1. A/D Conversion Value and Temperature ..................................................................................... 9-2. Input Voltage and ...
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Product Development of 78K/0 Series The following shows the products organized according to usage. The names in the parallelograms are subseries names. Control PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 100-pin PD780058 80-pin PD78058F 80-pin 80-pin PD78054 PD780034 64-pin 64-pin ...
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The following lists the main functional differences between subseries products. Function ROM Capacity 8-bit 16-bit Watch WDT A/D A/D Subseries Name Control PD78075B 32K-40K 4ch 1ch PD78078 48K-60K PD78070A – PD780058 24K-60K 2ch PD78058F 48K-60K PD78054 16K-60K PD780034 8K-32K PD780024 ...
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Features of 78K/0 Series The 78K/0 series is a collection of 8-bit single-chip microcontrollers ideal for commercial systems. The PD78054 and 78054Y subseries are provided with peripheral hardware functions such as an A/D converter, D/A converter, timer, serial interface, ...
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Figure 1-1. Block Diagram of PD78054 Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-1. Functional Outline of PD78054 Subseries (1/2) Item PD78052 Part Number Internal ROM Mask ROM memory 16K bytes 24K bytes 32K bytes 512 bytes 1024 bytes High-speed RAM 32 bytes Buffer RAM Expansion RAM None Memory space 64K bytes ...
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Table 1-1. Functional Outline of PD78054 Subseries (2/2) Item PD78052 Part Number Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Vectored Maskable Internal: 13, external: 7 interrupt Non-maskable Internal: 1 source ...
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Figure 1-2. Block Diagram of PD78054Y Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SERIAL SO0/SB1/SDA1/P26 INTERFACE 0 SCK0/SCL/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-2. Functional Outline of PD78054Y Subseries (1/2) Item PD78052Y Part Number Internal ROM Mask ROM memory 16K bytes High-speed RAM 512 bytes Buffer RAM 32 bytes Expansion RAM None Memory space 64K bytes General-purpose register 8 bits 8 4 ...
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Table 1-2. Functional Outline of PD78054Y Subseries (2/2) Item PD78052Y Part Number Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Vectored Maskable Internal: 1 interrupt Non-maskable 1 ...
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Figure 1-3. Block Diagram of PD78064 Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI2/R D/P70 X SERIAL ...
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Table 1-3. Functional Outline of PD78064 Subseries Item PD78062 Part Number Internal Mask ROM ROM memory 16K bytes 512 bytes High-speed RAM LCD display RAM 40 4 bits Memory space 64K bytes 8 bits 8 General-purpose register Minimum With main ...
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Figure 1-4. Block Diagram of PD78064Y Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SERIAL SO0/SB1/SDA1/P26 INTERFACE 0 SCK0/SDL/P27 SI2/R D/P70 X SERIAL ...
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Table 1-4. Functional Outline of PD78064Y Subseries Item PD78062Y Part Number Internal ROM Mask ROM memory 16K bytes High-speed RAM 512 bytes LCD display RAM 40 4 bits Memory space 64K bytes General-purpose register 8 bits 8 4 banks Minimum ...
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Figure 1-5. Block Diagram of PD78078 Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER ...
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Table 1-5. Functional Outline of PD78078 Subseries Item PD78076 Part Number Internal ROM Mask ROM memory 48K bytes 1024 bytes High-speed RAM Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space 64K bytes 8 bits 8 4 banks General-purpose ...
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Figure 1-6. Block Diagram of PD78078Y Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER ...
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Table 1-6. Functional Outline of PD78078Y Subseries Item PD78076Y Part Number Internal ROM Mask ROM memory 48K bytes High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space 64K bytes 8 bits 8 General-purpose register Minimum ...
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Figure 1-7. Block Diagram of PD78083 Subseries 8-bit TIMER/ TI5/TO5/P100 EVENT COUNTER 5 5-bit TIMER/ TI6/TO6/P101 EVENT COUNTER 6 WATCHDOG TIMER SI2/RxD/P70 SERIAL SO2/TxD/P71 INTERFACE 2 SCK2/ASCK/P72 ANI0/P10- ANI7/P17 AV DD A/D CONVERTER REF1 INTP1/P01- INTERRUPT INTP3/P03 ...
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Table 1-7. Functional Outline of PD78083 Subseries Item PD78081 Part Number Internal ROM Mask ROM memory 8K bytes High-speed RAM 256 bytes Memory space 64K bytes General-purpose register 8 bits 8 4 banks Minimum instruction 0.4 s/0.8 s/1.6 s/3.2 s/6.4 ...
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Figure 1-8. Block Diagram of PD78098 Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-8. Functional Outline of PD78098 Subseries (1/2) Item PD78094 Part Number Internal ROM Mask ROM memory 32K bytes High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM None Memory space 64K bytes General-purpose register 8 bits 8 Minimum ...
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Table 1-8. Functional Outline of PD78098 Subseries (2/2) Item PD78094 Part Number Buzzer output 977 Hz, 1.95 kHz, 3.9 kHz, 7.8 kHz (with main system clock of 6.0 MHz) Vectored Maskable Internal: 14, external: 7 interrupt Non-maskable Internal: 1 source ...
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Figure 1-9. Block Diagram of PD780018 Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER ...
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Table 1-9. Functional Outline of PD780018 Subseries (1/2) Item PD780016 Part Number Mask ROM Internal ROM memory 48K bytes 1024 bytes High-speed RAM 32 bytes Buffer RAM 1024 bytes Expansion RAM 64K bytes Memory space 8 bits 8 General-purpose register ...
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Table 1-9. Functional Outline of PD780018 Subseries (2/2) Item PD780016 Part Number 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Buzzer output Internal: 12, external: 7 Vectored Maskable Internal: 1 interrupt Non-maskable 1 source Software ...
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Figure 1-10. Block Diagram of PD780018Y Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER ...
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Table 1-10. Functional Outline of PD780018Y Subseries (1/2) Item PD780016Y Part Number ROM Mask ROM Internal memory 48K bytes High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space 64K bytes General-purpose register 8 bits 8 ...
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Table 1-10. Functional Outline of PD78P0018Y Subseries (2/2) Item PD780016Y Part Number 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Buzzer output Internal: 12, external: 7 Vectored Maskable Internal: 1 interrupt Non-maskable 1 source Software ...
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Figure 1-11. Block Diagram of PD780058 Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-11. Functional Outline of PD780058 Subseries (1/2) Item PD780053 Part Number Internal ROM Mask ROM memory 24K bytes 1024 bytes High-speed RAM Buffer RAM 32 bytes Expansion RAM None Memory space 64K bytes 8 bits 8 4 banks General-purpose ...
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Table 1-11. Functional Outline of PD780058 Subseries (2/2) Item PD780053 Part Number Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Vectored Maskable Internal: 1 interrupt Non-maskable 1 ...
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Figure 1-12. Block Diagram of PD780058Y Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SERIAL SO0/SB1/SDA1/P26 INTERFACE 0 SCK0/SCL/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-12. Functional Outline of PD780058Y Subseries (1/2) Item PD780053Y Part Number Internal ROM Mask ROM memory 24K bytes 1024 bytes High-speed RAM Buffer RAM 32 bytes Expansion RAM None Memory space 64K bytes 8 bits 8 4 banks General-purpose ...
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Table 1-12. Functional Outline of PD780058Y Subseries (2/2) Item PD780053Y Part Number 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Buzzer output Internal: 13, external: 7 Vectored Maskable Internal: 1 interrupt Non-maskable 1 ...
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Figure 1-13. Block Diagram of PD780308 Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI2/R D/P70 X SO2/T ...
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Table 1-13. Functional Outline of PD780308 Subseries Item PD780306 Part Number Internal ROM Mask ROM memory 48K bytes 1024 bytes High-speed RAM 1024 bytes Expansion RAM 40 4 bits LCD display RAM 64K bytes Memory space 8 bits 8 4 ...
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Figure 1-14. Block Diagram of PD780308Y Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SERIAL RxD/P114 INTERFACE 0 TxD/P113 SCK0/SDL/P27 SI2/R D/P70 ...
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Table 1-14. Functional Outline of PD780308Y Subseries Item PD780306Y Part Number ROM Mask ROM Internal memory 48K bytes 1024 bytes High-speed RAM 1024 bytes Expansion RAM 40 4 bits LCD display RAM Memory space 64K bytes 8 bits 8 4 ...
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Figure 1-15. Block Diagram of PD78058F Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-15. Functional Outline of PD78058F Subseries (1/2) Item PD78056F Part Number Internal Mask ROM ROM memory 48K bytes 1024 bytes High-speed RAM 32 bytes Buffer RAM None Expansion RAM 64K bytes Memory space 8 bits 8 4 banks General-purpose ...
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Table 1-15. Functional Outline of PD78058F Subseries (2/2) Item Part Number 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Buzzer output Internal: 13, external: 7 Vectored Maskable Internal: 1 interrupt Non-maskable Internal: 1 ...
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Figure 1-16. Block Diagram of PD78058FY Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SERIAL SO0/SB1/SDA1/P26 INTERFACE 0 SCK0/SCL/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-16. Functional Outline of PD78058FY Subseries (1/2) Item PD78056FY Part Number Internal ROM Mask ROM memory 48K bytes 1024 bytes High-speed RAM 32 bytes Buffer RAM Expansion RAM None Memory space 64K bytes General-purpose register 8 bits 8 4 ...
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Table 1-16. Functional Outline of PD78058FY Subseries (2/2) Item PD78056FY Part Number 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Buzzer output Internal: 13, external: 7 Vectored Maskable Internal: 1 interrupt Non-maskable 1 ...
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Figure 1-17. Block Diagram of PD78064B Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI2/R D/P70 X SERIAL ...
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Table 1-17. Functional Outline of PD78064B Subseries Item Part Number ROM Mask ROM Internal memory 32K bytes High-speed RAM 1024 bytes LCD display RAM 40 4 bits Memory space 64K bytes General-purpose register 8 bits 8 4 banks Minimum With ...
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Figure 1-18. Block Diagram of PD78070A TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 ...
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Table 1-18. Functional Outline of PD78070A Part Number Internal ROM None memory High-speed RAM 1024 bytes Buffer RAM 32 bytes Memory space 64K bytes General-purpose register 8 bits 8 4 banks Minimum With main 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 ...
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Figure 1-19. Block Diagram of PD78070AY TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 ...
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Table 1-19. Functional Outline of PD78070AY Part Number Internal ROM None memory 1024 bytes High-speed RAM Buffer RAM 32 bytes Memory space 64K bytes General-purpose register 8 bits 8 4 banks Minimum With main 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 ...
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Figure 1-20. Block Diagram of PD78075B Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER ...
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Table 1-20. Functional Outline of PD78075B8 Subseries Item Part Number ROM Mask ROM Internal memory High-speed RAM 32K bytes Buffer RAM 1024 bytes 32 bytes Expansion RAM Memory space 64K bytes General-purpose register 8 bits 8 4 banks Minimum With ...
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Figure 1-21. Block Diagram of PD78075BY Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 8-bit TIMER/EVENT TI5/TO5/P100 COUNTER 5 8-bit TIMER/EVENT TI6/TO6/P101 COUNTER 6 WATCHDOG TIMER WATCH TIMER ...
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Table 1-21. Functional Outline of PD78075BY Subseries Item Part Number Internal ROM Mask ROM memory 32K bytes 1024 bytes High-speed RAM Buffer RAM 32 bytes Memory space 64K bytes General-purpose register 8 bits 8 4 banks Minimum With main 0.4 ...
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Figure 1-22. Block Diagram of PD78098B Subseries TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SERIAL SCK1/P22 ...
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Table 1-22. Functional Outline of PD78098B Subseries Item PD78095B Part Number ROM Internal Mask ROM memory 40K bytes 1024 bytes High-speed RAM 32 bytes Buffer RAM None Expansion RAM 64K bytes Memory space 8 bits 8 4 banks General-purpose register ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.1 Data Transfer Data is exchanged by using an address specified by the DE and HL registers as the first address. The number of bytes of the data to be exchanged is specified by the ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.2 Data Comparison Data is compared by using an address specified by the DE and HL registers as the first address. The number of bytes of the data to be compared is specified by the ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.3 Decimal Addition The lowest address for decimal addition is specified by the DE and HL registers, and the number of digits specified by BYTNUM is added. The result of the addition is stored to ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE No 60 DADDS CY 0 Sign flag SFLAG 0 DADDS1 A [DE] + [HL Adds augend and addend with CY Adjusts result to decimal and stores in memory ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE DSUBS Makes subtrahend positive Sign flag SFLAG 0 Minuend < 0 Yes Makes subtrahend positive Sign flag SFLAG 1 DSUBS1 DSUBS2 A [DE] – [HL] – CY Subtracts subtrahend from minuend ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE (2) Registers used AX, BC, DE, HL (3) Program list ;****************************************************************** ; ; Input parameter ; HL register: addend first address ; DE register: augend first address ; Output parameter ; HL register: Operation result ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE ;============================================================= ; ***** 10 Decimal addition ***** ;============================================================= DADDS: CLR1 CY CLR1 SFLAG DADDS1: MOV A,[DE] ADDC A,[HL] ADJBA MOV [HL],A INCW HL INCW DE DBNZ B,$DADDS1 MOV A,[DE] ADDC A,[HL] DADDS2: BNC $DADDS3 SET1 ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE ;================================================================ ; ***** 10 Decimal subtraction ***** ;================================================================ DSUBS: PUSH HL CLR1 SFLAG MOV A,[HL+BYTNUM–1] CLR1 A.7 MOV [HL+BYTNUM–1],A XCHW AX,DE XCHW AX,HL XCHW AX,DE MOV A,[HL+BYTNUM–1] BF A.7,$DSUBS1 CLR1 A.7 MOV [HL+BYTNUM–1],A SET1 SFLAG ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE MOV [HL],A INCW HL DBNZ C,$DSUBS4 MOV1 CY,SFLAG NOT1 CY MOV1 SFLAG,CY ;====================================================== ; ***** 0 check of operation result ***** ;====================================================== DSUBS5: MOV A,B MOV C,A POP HL PUSH HL MOV A,#0 DSUBS6: CMP ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.4 Decimal Subtraction The lowest address for decimal subtraction is specified by the DE and HL registers, and the number of digits specified by BYTNUM is subtracted. The result of the subtraction is stored to ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE (3) Program list ;****************************************************************** ; ; Input parameter ; HL register: subtrahend first address ; DE register: minuend first address ; Output parameter ; HL register: Operation result first address ; ;****************************************************************** PUBLIC BYTNUM PUBLIC ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.5 Binary-to-Decimal Conversion Binary data of 16 bits in data memory is converted into 5-digit decimal data and stored in data memory. Binary data of 16 bits is divided by decimal 10 by the number ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE (2) Program list PUBLIC B_DCONV DATDEC EQU 10 DSEG SADDRP REGA REGB COLNUM EQU 4 B_DCONV: MOVW AX,REGA MOV B,#COLNUM MOVW HL,#REGB B_D1: MOV C,#DATDEC DIVUW C XCH A,C MOV [HL],A ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.6 Bit Manipulation Instruction A 1 bit of a flag in the data memory is ANDed with the bit 4 of port 6, and the result is ANDed with the bit 5 of port 6 ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.7 Binary Multiplication (16 bits Data in a multiplicand area (HIKAKE; 16 bits) and multiplier area (KAKE; 16 bits) are multiplied, and the result is stored in an operation result storage area (KOTAE). Multiplicand area ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE <Contents used> Set the data in the multiplicand (HIKAKE) and multiplier (KAKE) areas, and call subroutine S_KAKERU. EXTRN S_KAKERU EXTRN HIKAKE,KAKE,KOTAE MAIN: · · HIKAKE=WORKA (A) HIKAKE+1=WORKA+1 (A) KAKE=WORKB (A) KAKE+1=WORKB+1 (A) CALL !S_KAKERU HL=#KOTAE ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE (1) Input/output condition • Input parameter HIKAKE : Store the multiplicand data in this area. KAKE : Store the multiplier data in this area. • Output parameter KOTAE : Store the result of the operation ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE (4) Program list $PC(054) ; PUBLIC HIKAKE,S_KAKERU,KAKE,KOTAE ; ;************************************************ ; RAM definition ;************************************************ DSEG SADDR HIKAKE KAKE WORK1 KOTAE ;************************************************ ; Multiplication ;************************************************ CSEG S_KAKERU: WORK1=KAKE+1 ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.8 Binary Division (32 bits 16 bits) Data in a dividend area (HIWARU; 32 bits) is divided by data in a divisor area (WARUM; 16 bits), and the result is stored in an operation result ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE <Usage> Set data in the dividend area (HIWARU) and divisor area (WARUM), and call subroutine S_WARU. EXTRN S_WARU EXTRN HIWARU,WARUM,KOTAE EXBIT F_ERR MAIN: · · HIWARU=WORKA (A) HIWARU+1=WORKA+1 (A) WARUM=WORKB (A) WARUM+1=WORKB+1 (A) CALL !S_WARU ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE (1) Input/output conditions • Input parameter HIWARU: Store the dividend data in this area. WARUM : Store the divisor data in this area. • Output parameter KOTAE : Store the result of the calculation in ...
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CHAPTER 2 FUNDAMENTALS OF SOFTWARE (4) Program list $PC(054) ; PUBLIC S_WARU,HIWARU,WARUM,F_ERR EXTRN KOTAE ; ;************************************************ ; RAM definition ;************************************************ DSEG SADDR HIWARU WARUM AMARI BSEG F_ERR DBIT ;************************************************ ; Division ;************************************************ CSEG S_WARU: ...
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... CPU clock is actually changed therefore not apparent for a while after the contents of the PCC have been rewritten, whether the processor operates on the new or old clock. To stop the main system clock or execute the STOP instruction, therefore, the wait time shown in Table 3-1 is necessary. Caution IECL1 and IECL2 are provided to the PD78098, 78098B subseries only. ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Table 3-1. Maximum Time Required for Changing CPU Clock Set Value before Change MCS CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-1. Format of Processor Clock Control Register ( PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol PCC ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-2. Format of Processor Clock Control Register ( PD78083 subseries) Symbol PCC PCC2 PCC1 PCC0 ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-3. Format of Processor Clock Control Register ( PD78098, 78098B subseries) Symbol PCC MCC FRC CLS CSS 0 R/W CSS PCC2 PCC1 PCC0 ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-4. Format of Processor Clock Control Register ( PD780018, 780018Y subseries) Symbol PCC MCC FRC CLS CSS R/W CSS PCC2 PCC1 PCC0 ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-5. Format of Oscillation Mode Select Register ( PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-7. Format of Oscillation Mode Select Register ( PD780018, 780018Y subseries) Symbol OSMS Cautions 1. When an instruction that writes a value ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION The fastest instruction is executed in two CPU clocks. Therefore, the relation between the CPU clock (f minimum instruction execution time is as shown in Tables 3-2 and 3-3. Table 3-2. Relation between ...
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Table 3-3. CPU Clock (f Selects CPU clock (f ) CPU CSS PCC2 PCC1 PCC0 MCS 0 IECL20 0 IECL10 (0. ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION 3.1 Changing PCC Immediately after RESET When the RESET signal is asserted, the slowest mode (processor clock control register: PCC = 04H, oscillation mode select register: OSMS = 00H) of the main system ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION (1) SPD chart Sets watch timer to 3.91 ms WHILE: No watch timer interrupt request ( ! TMIF3) Clears TMIF3 Sets PCC in fastest mode (2) Program list ;************************************** ;* Sets wait time ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION 3.2 Selecting Power ON/OFF The 78K/0 series can operate in an ultra low current consumption mode by using the processor clock control register (PCC) and selecting the subsystem clock. By providing a backup ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-12. Example of Changing System Clock on Power Failure ( PD78054 subseries) 6.0 (V) V pin voltage 4.5 (V) DD 2.0 (V) ON Commercial power source OFF H P01/INTP1 pin L Interrupt ...
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CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION (1) SPD chart INTP1 IF: power off (P01 = low level) THEN Sets CPU clock in slowest mode User processing ELSE Sets CPU clock in fastest mode User processing (2) Program list VEP0 ...
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[MEMO] 94 ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER The watchdog timer of the 78K/0 series has two modes: watchdog timer mode in which a hang-up of the microcontroller is detected, and interval timer mode. The watchdog timer is set by using timer ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-1. Format of Timer Clock Select Register 2 ( PD78054 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-2. Format of Timer Clock Select Register 2 ( PD78083 subseries) Symbol TCL2 TCL27 TCL26 TCL25 0 TCL22 TCL21 TCL20 ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-3. Format of Timer Clock Select Register 2 ( PD78098, 78098B subseries) Symbol TCL2 TCL27 TCL26 TCL25 TCL24 0 TCL22 TCL21 TCL20 ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-4. Format of Timer Clock Select Register 2 ( PD780018, 780018Y subseries) Symbol TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-5. Format of Watchdog Timer Mode Register Symbol WDTM RUN 0 0 WDTM4 WDTM3 Notes 1. Once WDTM3 and WDTM4 have been set to 1, they cannot be ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER 4.1 Setting Watchdog Timer Mode Reset processing or non-maskable interrupt processing is performed after the watchdog timer has detected a hang- up. You can select which processing performed by the watchdog ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER (2) Program list ;************************************* ;* Sets watchdog timer ;************************************* OSMS=#00000001B TCL2=#00000100B WDTM=#10011000B ; User processing 1 SET1 RUN ; User processing 2 SET1 RUN ; User processing 3 SET1 RUN 102 ; Does not ...
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CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER 4.2 Setting Interval Timer Mode When the interval timer mode is used, the interval time is set by the timer clock select register 2 (TCL2) (interval time = 0.488 ms to 125 ms, at ...
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[MEMO] 104 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER The 16-bit timer/event counter of the 78K/0 series has the following six functions: • Interval timer • PWM output • Pulse width measurement • External event counter • Square wave output • One-shot ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-1. Format of Timer Clock Select Register 0 ( PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Remarks main system clock frequency ( main system clock oscillation frequency subsystem clock oscillation frequency XT 4. TI00 : input pin of ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-2. Format of Timer Clock Select Register 0 ( PD78098, 78098B subseries) Symbol TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL03 TCL02 TCL01 TCL00 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-3. Format of Timer Clock Select Register 0 ( PD780018, 780018Y subseries) Symbol TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL03 TCL02 TCL01 TCL00 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-4. Format of 16-Bit Timer Mode Control Register Symbol TMC0 TMC03 TMC02 OVF0 0 Overflow does not occur 1 Overflow occurs TMC03 TMC02 TMC01 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Remarks 1. TO0 : output pin of 16-bit timer/event counter 2. TI00 : input pin of 16-bit timer/event counter 3. TM0 : 16-bit timer register 4. CR00 : compare register 00 5. CR01 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-6. Format of 16-Bit Timer Output Control Register Symbol TOC0 0 OSPT OSPE TOC04 LVS0 Cautions 1. Be sure to stop the timer operation before setting TOC0 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-7. Format of Port Mode Register 3 Symbol PM3 PM37 PM36 PM35 PM34 PM33 PM32 Figure 5-8. Format of External Interrupt Mode Register 0 Symbol 7 6 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-9. Format of Sampling Clock Select Register ( PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-10. Format of Sampling Clock Select Register ( PD78098, 78098B subseries) Symbol SCS Caution the clock supplied to ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.1 Setting of Interval Timer To set the 16-bit timer/event counter as an interval timer, first set the timer clock select register 0 (TCL0) and the 16-bit timer mode control register (TMC0). The ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (b) Interval <1> Setting of TMC0 Selects a mode in which the timer is cleared and started on coincidence between TM0 and CR00. <2> Setting of TCL0 2 Select the ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.2 PWM Output When using the 16-bit timer/event counter in the PWM output mode, set the PWM mode by the 16-bit timer mode control register (TMC0) and enables the output of the 16-bit ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <Initial setting> • OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit • Setting of 16-bit timer/event counter CRC0 = #00000000B ; Selects CR00 as compare register TMC0 = ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC PWM,PWMOUT PWM_DAT DSEG SADDR PWMOUT ;************************************ ;* PWM output (16 steps) ;************************************ P0_SEG CSEG PWM: A=PWMOUT A<<=1 A<<=1 A<<=1 A<<=1 A|=#0FH X=#0FCH CR00=AX RET 120 ; PWM ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.3 Remote Controller Signal Reception This section introduces two examples of programs that receives signals from a remote controller by using the 16- bit timer/event counter. • The counter is cleared each time ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-13. Remote Controller Signal Transmitter IC Output Signal 67.5 ms 108 4.5 ms Custom Code 8 bits 13.5 ms Leader Code First time 9 ms Second time and onward ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.3.1 Remote controller signal reception by counter clearing Table 5-1 shows the valid pulse width for receiving a remote controller signal in the program example shown in this section, and <1> through <6> ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <2> Leader code (high) The pulse width while the leader code is high is measured by using the falling-edge interrupt request INTP0 and the count value of the timer. <3> Custom/data code The ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <RAM used> Name RPTCT Repeat code valid time counter RMENDCT No-input time counter after data input SELMOD Mode selection LD_CT Leader signal detection counter RMDATA Valid data storage area WORKP Input signal storage ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use PUBLIC CSTM EXTRN RMDATA,RPTCT EXTBIT RPT,RMDTSET,IPDTFG CSTM EQU 9DH OSMS=#00000001B CRC0=#00000100B CR00=#6290 TCL0=#00100000B TMC0=#00001100B SCS=#00000011B CLR1 PPR0 CLR1 RPT CLR1 IPDTFG CLR1 RMDTSET CLR1 TMMK0 EI DT_TEST: if_bit(RMDTSET) CLR1 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (3) SPD chart INTTM00 Selects register bank 1 Enables master interrupt IF: input signal exists (IPDTFG) THEN IF: valid data exists (RMDTOK) THEN THEN ELSE ELSE THEN ELSE Counts leader low time S_LOWCT ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER INTP0 Selects register bank 0 Waits for 100 s WAIT CASE: SELMOD OF: 1 Leader low measuring mode LEAD_L OF: 2 Leader high measuring mode LEAD_H OF: 3 Custom code/data loading mode CDCODE ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER CDCODE IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Reads timer CR_READ IF: 0.5 ms < input data THEN IF: input data THEN ELSE Stores CY ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ENDCHK IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN CR_READ Reads capture register Stops 16-bit timer operation Starts timer S_M0SET Selects leader low detection mode Disables ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC RPT,IPDTFG,RMDTOK,RMDTSET PUBLIC RMENDCT,RPTCT,SELMOD,LD_CT,RMDATA EXTRN CSTM RM_DAT DSEG SADDR RPTCT RMENDCT: DS SELMOD LD_CT RMDATA RM_DATP DSEG SADDRP WORKP BSEG ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER S_LOWCT: if(SELMOD==#0) if_bit(!P0.0) LD_CT–– if(LD_CT==#0) SELMOD=#1 TMC0=#00000000B CR00=#32767 TMC0=#00001100B INTM0=#00000100B CLR1 PIF0 CLR1 PMK0 LD_CT=#5 endif else LD_CT=#5 endif else CALL !S_MOSET LD_CT=#5 endif RET $EJECT ;*********************************************************** ;* Remote controller signal edge detection ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;**************************************** ;* Leader low detection ;**************************************** LEAD_L: if_bit(P0.0) CALL !WAIT if_bit(P0.0) CALL !CR_READ if(AX>=#3354) if(AX<#18035) SELMOD=#2 INTM0=#00000000B else CALL !S_MOSET endif else CALL !S_MOSET endif endif endif RET $EJECT ;**************************************** ;* Leader high ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;****************************** ;* Custom/data code loading ;****************************** CDCODE: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CALL !CR_READ if(AX>=#1257–190/2) if(AX<#9646–190/2) if(AX>=#6710–190/2) SET1 else CLR1 endif HL=#WORKP+3 C=#4 WKSHFT: A=[HL] RORC [HL]=A HL–– DBNZ if_bit(CY) if(WORKP+0==#CSTM) (A) else 134 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER endif endif else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ;************************************ ;* Repeat code detection ;************************************ REPCD: if_bit(P0.0) CALL !WAIT if_bit(P0.0) if_bit(RMDTOK) CALL !CR_READ if(AX<=#3354–190/2) SET1 RPT CLR1 RMDTOK ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;**************************************** ;* Abnormal data detection ;**************************************** ENDCHK: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CLR1 IPDTFG CLR1 RPT CALL !S_M0SET endif endif RET ;**************************************** ;* Waits for 100 s ;**************************************** WAIT: B=#(838–14–12–8)/12 WAITCT: DBNZ B,$WAITCT RET ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.3.2 Remote controller signal reception by PWM output and free running mode Table 5-2 shows the valid pulse width when a remote controller signal is received by this program. <1> through <6> below ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <6> Time out during pulse width measurement The OVF0 of the 16-bit timer/event counter is tested during pulse width measurement detected two times, time out is assumed and the data ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <Flag used> Name IPDTFG Presence/absence of valid data RMDTOK Presence/absence of valid input signal RMDTSET Presence/absence of input signal RPT Judgment whether repeat valid period elapsed TO_FLG Occurrence of timer overflow OVSENS Detection ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use PUBLIC CSTM EXTRN RMDATA,RPTCT,PWM,PWMOUT,TIM_PRO EXTBIT RPT,RMDTSET,IPDTFG,TO_FLG,OVSENS CSTM EQU 9DH OSMS=#00000001B CRC0=#00000100B TOC0=#00000011B TCL0=#00100000B TMC0=#00000010B INTM0=#00000000B SCS=#00000011B CLR1 PPR0 CLR1 RPT CLR1 IPDTFG CLR1 RMDTSET CLR1 PMK0 EI DT_TEST: if_bit(OVSENS) ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (3) SPD chart TIM_PRO IF: input signal exists THEN IF: valid data exists THEN IF: repeat code invalid time THEN Checks timer overflow TO_CHK ELSE IF: No input exists after input of data ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER RM_STA IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN LEAD_L IF: P00 = HIGH THEN Waits for 100 s WAIT IF: P00 = HIGH THEN THEN ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER CDCODE IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Reads timer CR_READ IF: 0.5 ms < input data THEN THEN ELSE THEN ELSE Sets leader low ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ENDCHK IF: P00 = LOW THEN THEN PW_CT IF: OVF occurs after edge detection processing THEN THEN Loads capture register value Subtracts capture register value from previous value IF: borrow occurs as result ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC TIM_PRO,RPT,IPDTFG,RMDTOK,RMDTSET PUBLIC RMENDCT,RPTCT,SELMOD,LD_CT,RMDATA PUBLIC TO_FLG,OVSENS EXTRN CSTM RM_DAT DSEG SADDR RPTCT RMENDCT:DS 1 SELMOD LD_CT RMDATA TO_CNT RM_DATP DSEG ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER TO_CHK: if(SELMOD==#0) CLR1 TO_FLG else TO_CNT++ if(TO_CNT==#2) CALL !S_M0SET endif endif RET $EJECT ;*********************************************************** ;* Remote controller signal edge detection processing ;*********************************************************** P0_SEG CSEG INTP0: SEL RB0 CALL !WAIT switch(SELMOD) case 0: CALL ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;**************************************** ;* Leader low detection ;**************************************** LEAD_L: if_bit(P0.0) CALL !WAIT if_bit(P0.0) CALL !PW_CT if_bit(!CY) TO_CNT=#0 if(AX>=#12582) if(AX<#41942) SELMOD=#2 INTM0=#00000000B else CALL endif else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;****************************** ;* Custom/data code loading ;****************************** CDCODE: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CALL !PW_CT if_bit(!CY) TO_CNT=#0 if(AX>=#2096) if(AX<#10485) if(AX>=#7549) else endif HL=#WORKP+3 C=#4 WKSHFT: A=[HL] RORC [HL]=A HL–– DBNZ if_bit(CY) else endif endif else ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER CALL endif else CALL !S_M0SET endif endif endif RET $EJECT ;************************************ ;* Repeat code detection ;************************************ REPCD: if_bit(P0.0) CALL !WAIT if_bit(P0.0) if_bit(RMDTOK) CALL !PW_CT if_bit(!CY) TO_CNT=#0 if(AX<=#4193) SET1 CLR1 CLR1 CALL else CALL ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;********************************************* ;* Abnormal data detection ;********************************************* ENDCHK: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CLR1 IPDTFG CLR1 RPT CALL !S_M0SET endif endif RET ;********************************************* ;* Calculation of capture register value ;********************************************* PW_CT: if_bit(OVF0) if(CR01<#10000–33) (AX) CLR1 ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;********************************************** ;* Waits for 100 s ;********************************************** WAIT: B=#(838–14–12–8)/12 WAITCT: DBNZ B,$WAITCT RET ;********************************************** ;* Sets start edge detection mode ;********************************************** S_M0SET: TO_CNT=#0 SELMOD=#0 INTM0=#00000000B RET ;********************************************** ;* Setting of abnormal data detection ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.4 One-Shot Pulse Output The 16-bit timer/event counter has a function which outputs a one-shot pulse in synchronization with a software trigger and external trigger (INTP0/TI00/P00 pin input). When using the one-shot pulse ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-16. Timing of One-Shot Pulse Output Operation by Software Trigger Count clock TM0 count value 0000 TO0/P30 pin output CR01 set value CR00 set value OSPT INTTM01 INTTM00 F_TRG Remark F_TRG: flag ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (1) Description of package <Public declaration symbol> SOP_INIT: One-shot pulse output initial setting subroutine <Register used> None <RAM used> None <Nesting level> 1 level 2 bytes <Hardware used> • 16-bit timer/event counter <Initial ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use Because bit 6 (OSPT) of the 16-bit timer output control register (TOC0) is not set again while the pulse is output in the example of this package, the F_TRG ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC SOP_INIT OPINIT CSEG SOP_INIT: TMC0=#00000000B TCL0=#01000000B CRC0=#00000000B CR00=#11550–1 CR01=#10500–1 TOC0=#00110111B TMC0=#00001100B RET END 5.5 PPG Output When using the 16-bit timer/event counter in the PPG (Programmable Pulse Generator) mode, ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (1) Description of package <Public declaration symbol> • Subroutine name SPG_INIT : PPG output initial setting subroutine • Data definition reference name of SPG_INIT routine PDAT : First address of data value for ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <Nesting level> 1 level 3 bytes <Hardware used> • 16-bit timer/event counter <Initial setting> • OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit • CLR1 P3.0 ; Clears ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use EXTRN SPG_INIT EXTRN SAIKURUP.PARUSUP EXTRN SAIKURU,PARUSU EXTRN PDAT,SDAT ; SMIN EQU 02H PMIN EQU 01H · · OSMS=#00000001B SAIKURU=#SMIN PARUSU=#PMIN CLR1 P3.0 CLR1 PM3.0 CALL !SPG_INIT EI · · ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (3) SPD chart PPG_INIT Stops timer operation Selects count clock of 16-bit timer register Uses CR00 and CR01 as compare registers Table reference of compare data corresponding to PARUSU area contents and stores ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC SPG_INIT,PDAT,SDAT PUBLIC SAIKURU,PARUSU EXTRN SAIKURUP,PARUSUP ; ;************************************************ ; RAM definition ;************************************************ PPGRAM DSEG SADDR SAIKURU PARUSU ;************************************************ ; PPG output initial setting ;************************************************ PPGINIT ...
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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER PDAT: DW 4201 DW 8403 DW 12605 DW 16807 DW 21009 DW 25211 DW 29413 DW 33615 DW 37817 SDAT: DW 8403 DW 12605 DW 16807 DW 21009 DW 25211 DW 29413 DW ...
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... The 8-bit timer/event counter of the 78K/0 series has three functions: interval timer, external event counter, and square wave output. Two channels of 8-bit timers/event counters are provided and these timers/event counters can be used as a 16-bit timer/event counter when connected in cascade. The 8-bit timers/event counters are set by the following registers: • ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-1. Format of Timer Clock Select Register 1 ( PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Remarks main system clock frequency ( main system clock oscillation frequency X 3. TI1 : input pin of 8-bit timer register 1 4. TI2 : input ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-2. Format of Timer Clock Select Register 1 ( PD78098, 78098B subseries) Symbol TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL13 TCL12 TCL11 TCL10 ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-3. Format of Timer Clock Select Register 1 ( PD780018, 780018Y subseries) Symbol TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL13 TCL12 TCL11 TCL10 ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-4. Format of 8-Bit Timer Mode Control Register Symbol TMC1 Cautions 1. Before changing the operation mode, stop the timer operation. 2. ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-5. Format of 8-Bit Timer Output Control Register Symbol TOC1 LVS2 LVR2 TOC15 TOE2 LVS1 Cautions 1. Before setting TOC1, be sure to stop the timer operation. ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-6. Format of Port Mode Register 3 Symbol PM3 PM37 PM36 PM35 PM34 PM33 PM32 170 Address At reset PM31 PM30 FF23H FFH PM3n ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.1 Setting of Interval Timer When using an 8-bit timer/event counter as an interval timer, set an operation mode by the 8-bit timer mode control register (TMC1) and interval time by the timer ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.1.1 Setting of 8-bit timers In this example, 8-bit timer 2 is used to set two types of interval times: 500 s and 100 ms. (a) To set interval of 500 s <1> ...
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... CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.1.2 Setting of 16-bit timer In this example, 8-bit timers 1 and 2 are connected in cascade as a 16-bit timer to set two types of interval times: 500 ms and 10 s. (a) To set interval of 500 ms <1> Setting of TMC1 Select the 16-bit timer register and 2. <2> Setting of TCL1 ...
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CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.2 Musical Scale Generation This section shows an example of a program that uses the square wave output (P31/TO1 8-bit timer/event counter and generates a musical scale by supplying pulses to ...