HM5216326FP-10 HITACHI, HM5216326FP-10 Datasheet
HM5216326FP-10
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HM5216326FP-10 Summary of contents
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Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5216326 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for graphic applications. ...
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... HM5216326 Series Ordering Information Type No. HM5216326FP-8 HM5216326FP-10 HM5216326FP-12 Pin Arrangement DQ29 DQ30 83 DQ31 DQ0 97 DQ1 DQ2 100 2 Frequency 125 MHz 100 MHz 83 MHz HM5216326FP Series ...
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Pin Description Pin name A0 to A10 DQ0 to DQ31 CS RAS CAS WE DQM0 to DQM3 CLK CKE DSF NC Function Address input Row address Column address Bank select ...
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HM5216326 Series Block Diagram Column address counter Row decoder Memory array Bank 0 1024 row 256 column Input Output buffer DQ0 to DQ31 Column address buffer 32 bit buffer A0 to A10 A0 to A10 Row ...
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Pin Functions CLK (input pin): CLK is the master clock input pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all ...
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HM5216326 Series Simplified State Diagram Write WRITE/ BWRITE SUSPEND WRITE/ BWRITEA SUSPEND POWER APPLIED Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE ...
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Commands Operation Commands Explanation Every operations of HM5216326 are executed by input commands. A command is input, at the rising edge of CLK, by setting the levels on CS, RAS, CAS, WE, A9 (precharge control) and DSF pins, HIGH (V ...
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HM5216326 Series Precharge command [PRE, PALL]: At the CLK rising edge, by setting CS, RAS, WE, DSF are LOW, CAS is HIGH bank can be precharged to idle state LOW: the bank selected by A10 is precharged. A9 ...
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Mode register set command [MRS]: If both banks have been precharged or are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, WE, DSF; LOW an internal register (the mode register; MRS) are set. The data ...
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HM5216326 Series Mode Register Configuration A10 ...
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Bank and row active command [ACTV, ACTVM bank has been precharged idle state. At the CLK rising edge, by setting CS, RAS; LOW, CAS, WE: HIGH a row of the bank is activated. The bank ...
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HM5216326 Series Column address and read command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF; LOW, RAS, WE; HIGH, data is output through DQ pins. ...
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Column Address and Read Command ( Column address and write command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF, WE; ...
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HM5216326 Series Row active — (Column address and write command) ->Row active Row active — (Column address and write command) ->Idle (auto precharge case) Column Address and Write Command ( Burst stop command (BST): At the CLK rising ...
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Burst Stop Command CLK CKE CS RAS CAS WE DSF A0 to A10 HM5216326 Series ...
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HM5216326 Series Auto refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, DSF; LOW, WE; HIGH, the HM5216326 starts auto-refresh (CBR type) operation. Refresh address is internaly generated. No ...
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Self refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, DSF; LOW, WE; HIGH, and if CKE's falling edge is detected, the HM5216326 starts self-refresh operation. Self-refresh operation is ...
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HM5216326 Series No operation command (NOP): At the CLK rising edge, by setting CS; LOW, WE, RAS, CAS; HIGH, [State transition] No transition No Operation Command Ignore command (DESL): At the CLK rising edge, by setting CS; HIGH, any input ...
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Graphic Commands Special mode register set command (SMRS): If each banks is in idle state or activated, at the CLK rising edge, by setting CS, RAS, CAS, WE; LOW, DSF; HIGH, an internal register (the special mode register; SMRS) are ...
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HM5216326 Series Special Mode Register Set Command A7 to A10 Special Mode Register Configuration Note Reserved Bits ...
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Graphic Function Block Diagram When block write command is issued, data I1 stored in the COLOR register is loaded into column block (8 columns) of memory array. For burst and single ...
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HM5216326 Series Column address and block write command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, WE; LOW, RAS, DSF; HIGH, a block write *2 is ...
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Column Address and Block Write Command Column Block Column location Note: 1. a3, ...
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HM5216326 Series DQ Input at the Block Write Cycle and Column Mask Location Column location 1 DQ pin NO. DQ group* A0 DQ0 00 0 DQ1 00 1 DQ2 00 0 DQ3 00 1 DQ4 00 0 DQ5 00 1 ...
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Command Truth Table The HM5216326 recognizes the following commands specified by the CS, RAS, CAS, WE, DSF and address pins. All other combinations than those in the table bellow are illegal. Function Ignore command No operation Burst stop in full ...
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HM5216326 Series DQM Truth Table Function Ith byte write enable/output enable Ith byte write input/output disable Note DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, ...
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Function Truth Table The following tables show how each command works and what command can be executed in the state given. Current state CS RAS CAS WE Precharge ...
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Current state CS RAS CAS WE Read Read with H auto precharge ...
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HM5216326 Series Current state CS RAS CAS WE Write/Bwrite H with auto precharge ...
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Current state CS RAS CAS WE Row activating Refresh(auto H precharge) L ...
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HM5216326 Series Operations of HM5216326 Series Power on sequence: In order to get rid of data contention of I/O bus when power on, the following power on sequence recommended to be performed before any operation. 1. Apply power and start ...
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Burst Length CLK t RCD read Command ACT row Address column BL=1 BL=2 DQout BL=4 BL=8 BL=Full page CAS Latency CLK Command ACT row Address CL out CL= 2 CL= 3 Burst operation (on read or write): One ...
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HM5216326 Series Column Block Column location Column block location Note: a1, a2, a3, a4, a5, a6, a7 Column location Column block location A0 A1 ...
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The Order of Burst Operation Start column location Order in decimal Sequential Start column location ...
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HM5216326 Series Write operation: OPCODE (A10, A9, A8) of the mode register is referred when a write command is executed as well as BL (Burst Length) and BT (Burst Type). CL (CAS Latency) is ignored and CL is fixed to ...
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Write per bit: To use write per bit function, 1. Set mask data in advance, which define DQ paths to be masked, to the MASK register by SMRS command. An interval not less than t necessary. 2. Use ACTVM command ...
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HM5216326 Series Write Per Bit Example DQ input data Block write: Before executing a block write ...
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Block Write Example with Write Per Bit Color data input ...
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HM5216326 Series Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation precharge commands are necessary after each read operation. The command next to this command must be a ...
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Write with auto precharge: In this operation, since precharge is automatically performed after completion of a burst write or a single write operation precharge commands are necessary after the write operation. The command next to this command must ...
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HM5216326 Series Block write with auto-precharge: In this operation, since precharge is automatically performed after completion of a block write operation need to execute precharge command. The following command must be a bank active command (ACTV, ACTVM). In ...
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Full Page Burst Stop Burst stop command during burst read: Burst stop command is used to stop data output during a full- page burst read. This command sets the output buffer to High-Z and stops the full-page burst read. The ...
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HM5216326 Series CAS Latency = 3, Burst Length = Full Page CLK Command DQ out Burst stop command at burst write: For full page burst write cycle, when a burst stop command is issued, the write data at that cycle ...
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DQM Control The DQM i (i= controls the ith byte of DQ data. DQM control operation for read and for write are different in terms of latency. Reading: When data are read, output buffer can be controlled ...
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HM5216326 Series Refresh Auto Refresh: All the banks must be precharged before executing an auto-refresh command. Auto refresh command increments the internal counter every time when it is executed. This command also determines the row to be refreshed. Therefore external ...
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Command Intervals Read Command to Read Command Interval: 1. Operation for a column in the same row: Read command can be issued every cycle. Note that the latest read command has the priority to the preceding read command, that is, ...
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HM5216326 Series Write Command to Write Command Interval: 1. Operation for a column in the same row : Write command can be issued every cycle. Note that the latest write command has the priority to the preceding write command, that ...
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Block Write Command to Write or Block Write Command Interval: 1. Operation for a column in the same row necessary to take no less than t block write and another block write or the following write ...
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HM5216326 Series Read Command to Write or Block Write Command Interval: 1. Operation for a column in the same row: The write or the block write command following the preceding read command can be performed after an interval of no ...
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Write Command to Read Command Interval: 1. Operation for a column in the same row: The read command following the preceding write command can be performed after an interval of no less than 1cycle. Note that the latest read command ...
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HM5216326 Series Block Write Command to Read Command Interval: 1. Operation for a column in the same row : Within the same row necessary to take no less than t between a block write and the following read ...
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Read Command to Precharge Command: The minimum interval between read command and precharge command is one cycle. However, since the output buffer then becomes High-Z after the cycles defined there is a possibility that burst read data ...
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HM5216326 Series READ to PRECHARGE Command Interval (Same Bank): Stop Output Data CAS Latency = 1, Burst Length = 4 CLK Command DQout CAS Latency = 2, Burst Length = 4 CLK Command DQout CAS Latency = 3, Burst Length ...
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Write Command to Precharge Command: The minimum interval between a write command and the following precharge command is 1 cycle. However, if the burst write operation is not finished, input must be masked by means of DQM for the cycle ...
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HM5216326 Series Block Write Command to Precharge Command Interval: The minimum interval between block write command and the following precharge command is t Block Write to Precharge Command Interval (Same Bank) CLK Command Bwrite Register set to register set interval: ...
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Bank Active Command Interval: 1. Operation for the same bank: The interval between two bank-active commands must be no less than t 2. Operation for another bank: The interval between two bank-active commands must be no less than t Bank ...
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HM5216326 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Note (max) = 5.75 V for pulse width IH ...
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DC Characteristics ( Parameter Symbol Min Operating current I CC1 Standby current I CC2 (Bank Disable) Active standby current I CC3 (Bank active) Bur s t oper ati ng c urr ent I (CL ...
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HM5216326 Series Capacitance ( Parameter Input capacitance (Address) Input capacitance (Signals) Output capacitance (DQ) Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM = V to disable Dout ...
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AC Characteristics ( Parameter System clock cycle time ( ( ( CLK high pulse width CLK low pulse width Access time from CLK ( (CL = ...
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HM5216326 Series AC Characteristics ( (cont) Parameter The last data-in to precharge lead time ( ( ( Block write to precharge lead time ( (CL = ...
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Test Conditions Input and output timing reference levels: 1.4 V Input waveform and output load: See following figures 2.8 V input V SS Output +1.4 V 500 DQ CL Test Load (A) 80% 20 LVTTL interface ...
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HM5216326 Series Relationship Between Frequency and Minimum Latency Parameter CL t (ns) CK Last data in to active command (Auto precharge, same bank) Block write to active command (Auto precharge, same bank) Precharge command to high impedance Last data out ...
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Timing Waveforms Read Cycle CLK V IH CKE t t CMS CMH CMS CMH RAS t t CMS CMH CAS t t CMS CMH A10 t ...
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HM5216326 Series Write Cycle CLK V IH CKE t t CMS CMH CMS CMH RAS t t CMS CMH CAS t t CMS CMH A10 t ...
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Mode Register Set Cycle CLK V CKE IH CS RAS CAS WE A10(BS valid code DQM DQ(output) DQ(input Precharge Mode register If needed Set Read Cycle/Write Cycle ...
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HM5216326 Series Read/Single Write Cycle CLK V CKE IH CS RAS CAS WE A10(BS) R:a C DQM DQ (input) DQ (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE ...
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Read/Burst Write Cycle CLK CKE CS RAS CAS WE A10(BS) R:a C DQM DQ (input) DQ (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE A10(BS) R:a C:a ...
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HM5216326 Series Full Page Read/Write Cycle CLK V CKE IH CS RAS CAS WE A10(BS R:a C:a DQM DQ (output) DQ (input) Bank 0 Bank 0 Active Read V CKE IH CS ...
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Self Refresh Cycle CLK CKE CS RAS CAS WE A10(BS A9=1 DQM DQ(input) DQ(output Self refresh entry Precharge command command If needed Clock Suspend Mode CLK CKE CS RAS ...
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HM5216326 Series Power Down Mode CLK CKE CS RAS CAS WE A10(BS A9=1 DQM DQ(input) DQ(output) Precharge command If needed 72 CKE Low t RP Power down entry t CKS R: a High-Z Power down cycle Power ...
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Mask Register Set Cycle 0 1 CLK V CKE IH CS RAS CAS WE DSF A10 DQM Precharge If needed Mask No Mask ...
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HM5216326 Series Color Register Set Cycle 0 1 CLK V CKE IH CS RAS CAS WE DSF A10 DQM Precharge If needed Mask Mask ...
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Write Cycle (with I/O Mask CLK V CKE IH CS RAS CAS WE DSF A10 DQM DQ in Bank 0 Bank 1 ACTVM ACTV ...
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HM5216326 Series Block Write Cycle 0 1 CLK V CKE IH CS RAS CAS WE DSF A10 DQM DQ in Bank 0 ACTVM ...
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... Package Dimensions HM5216326FP Series (FP-100H) 22.00 ± 0.10 20. 100 1 0.32 ± 0.08 0.30 ± 0.06 0.575 0.10 M 0.1 Hitachi Code JEDEC Code EIAJ Code Weight HM5216326 Series Unit: mm 1.00 0.825 0 – 10° 0.50 ± 0.10 FP-100H MO-136 — 0. ...
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... All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. ...
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Revision Record Rev. Date Contents of Modification 0.0 Nov. 20, 1996 Initial issue HM5216326 Series Drawn by Approved by 79 ...