HD6472655VTE HITACHI, HD6472655VTE Datasheet
HD6472655VTE
Related parts for HD6472655VTE
HD6472655VTE Summary of contents
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... H8S/2655, HD6432655, HD6472655, H8S/2653, HD6432653 ADE-602-094A Rev. 2.0 6/4/97 Hitachi, Ltd. MC-Setsu H8S/2655 Series Hardware Manual ...
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... All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. ...
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... Use of the H8S/2655 Series enables compact, high-performance systems to be implemented easily. This manual describes the hardware of the H8S/2655 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Note: * ZTAT is a trademark of Hitachi, Ltd. Preface ...
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Main Revisions and Additions in This Edition Page Section 11,16 1.2 Block Diagram, 1.3 Pin Description 14, 15 Table 1-3 Pin Functions 39 Table 2-2 Combinations of Instructions and Addressing Modes 125 5.6.3 Operation (1) Selection of ...
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Page Section 323 8.3.4 Location of Register Information in Address Space Figure 8-5 Location of Register Information in Address Space 325 8.3.6 Repeat Mode Table 8-6 Register Information in Repeat Mode 326 8.3.7 Block Transfer Mode Table 8-7 Register Information ...
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Page Section 555 12.3.3 Timing of External RESET on TCNT 574 13.3.1 Watchdog Timer Operation Figure13-4 Watchdog Timer Operation 609 Figure 14-2 Data Format in Asynchronous Communication 615 Figure 14-6 Example of Operation in Transmission in Asynchronous Mode 616, 617 ...
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Section 1 Overview ........................................................................................................... 1.1 Overview............................................................................................................................ 1.2 Block Diagram................................................................................................................... 1.3 Pin Description .................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode................................................................ 1.3.3 Pin Functions........................................................................................................ 13 Section 2 CPU ..................................................................................................................... 21 2.1 Overview............................................................................................................................ 21 2.1.1 Features ................................................................................................................ 21 ...
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On-Chip Supporting Module Access Timing....................................................... 67 2.9.4 External Address Space Access Timing............................................................... 68 Section 3 MCU Operating Modes 3.1 Overview............................................................................................................................ 69 3.1.1 Operating Mode Selection.................................................................................... 69 3.1.2 Register Configuration ......................................................................................... 3.2 Register Descriptions......................................................................................................... 71 3.2.1 Mode Control Register (MDCR).......................................................................... ...
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Register Descriptions......................................................................................................... 5.2.1 System Control Register (SYSCR) ...................................................................... 94 5.2.2 Interrupt Control Registers (ICRA to ICRC)............................................ 95 5.2.3 Interrupt Priority Registers (IPRA to IPRK) ............................................ 95 5.2.4 IRQ Enable Register (IER) .................................................................................. 97 ...
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Refresh Timer/Counter (RTCNT) ........................................................................ 150 6.2.9 Refresh Time Constant Register (RTCOR).......................................................... 150 6.3 Overview of Bus Control................................................................................................... 151 6.3.1 Area Partitioning .................................................................................................. 151 6.3.2 Bus Specifications ................................................................................................ 152 6.3.3 Memory Interfaces................................................................................................ 153 6.3.4 Advanced Mode.................................................................................................... 154 6.3.5 Areas in ...
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Burst ROM Interface ......................................................................................................... 202 6.8.1 Overview .............................................................................................................. 202 6.8.2 Basic Timing ........................................................................................................ 202 6.8.3 Wait Control ......................................................................................................... 204 6.9 Idle Cycle........................................................................................................................... 205 6.9.1 Operation .............................................................................................................. 205 6.9.2 Pin States in Idle Cycle ........................................................................................ 207 6.10 Write Data Buffer ...
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Operation ........................................................................................................................... 252 7.5.1 Transfer Modes .................................................................................................... 252 7.5.2 Sequential Mode................................................................................................... 255 7.5.3 Idle Mode.............................................................................................................. 258 7.5.4 Repeat Mode ........................................................................................................ 261 7.5.5 Single Address Mode ........................................................................................... 265 7.5.6 Normal Mode........................................................................................................ 268 7.5.7 Block Transfer Mode............................................................................................ 271 7.5.8 DMAC Activation ...
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Repeat Mode ........................................................................................................ 325 8.3.7 Block Transfer Mode............................................................................................ 326 8.3.8 Chain Transfer...................................................................................................... 328 8.3.9 Operation Timing ................................................................................................. 329 8.3.10 Number of DTC Execution States........................................................................ 330 8.3.11 Procedures for Using DTC ................................................................................... 332 8.3.12 Examples of Use of the DTC................................................................................ ...
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Port B ................................................................................................................................. 389 9.9.1 Overview .............................................................................................................. 389 9.9.2 Register Configuration ......................................................................................... 390 9.9.3 Pin Functions........................................................................................................ 392 9.9.4 MOS Input Pull-Up Function ............................................................................... 394 9.10 Port C ................................................................................................................................. 395 9.10.1 Overview .............................................................................................................. 395 9.10.2 Register Configuration ......................................................................................... 396 9.10.3 ...
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Timer Start Register (TSTR)................................................................................ 459 10.2.9 Timer Synchro Register (TSYR).......................................................................... 460 10.2.10 Module Stop Control Register (MSTPCR) .......................................................... 461 10.3 Interface to Bus Master...................................................................................................... 462 10.3.1 16-Bit Registers.................................................................................................... 462 10.3.2 8-Bit Registers...................................................................................................... 462 10.4 Operation ........................................................................................................................... 464 10.4.1 Overview ...
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Non-Overlapping Pulse Output ............................................................................ 533 11.3.5 Inverted Pulse Output ........................................................................................... 536 11.3.6 Pulse Output Triggered by Input Capture ............................................................ 537 11. 4 Usage Notes ....................................................................................................................... 538 11.4.1 Operation of Pulse Output Pins ............................................................................ 538 11.4.2 Note on Non-Overlapping Output........................................................................ ...
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Register Descriptions......................................................................................................... 568 13.2.1 Timer Counter (TCNT) ........................................................................................ 568 13.2.2 Timer Control/Status Register (TCSR) ................................................................ 568 13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 570 13.2.4 Notes on Register Access ..................................................................................... 572 13.3 Operation ........................................................................................................................... 574 13.3.1 Watchdog Timer Operation.................................................................................. 574 ...
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Section 15 Smart Card Interface 15.1 Overview............................................................................................................................ 643 15.1.1 Features ................................................................................................................ 643 15.1.2 Block Diagram...................................................................................................... 644 15.1.3 Pin Configuration ................................................................................................. 645 15.1.4 Register Configuration ......................................................................................... 646 15.2 Register Descriptions......................................................................................................... 647 15.2.1 Smart Card Mode Register (SCMR) .................................................................... 647 15.2.2 Serial ...
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Starting Conversion by External Input ................................................................. 694 16.4.9 A/D Conversion Time .......................................................................................... 695 16.5 Interrupts............................................................................................................................ 698 16.6 Usage Notes ....................................................................................................................... 699 Section 17 D/A Converter 17.1 Overview............................................................................................................................ 701 17.1.1 Features ................................................................................................................ 701 17.1.2 Block Diagram...................................................................................................... 702 17.1.3 Pin Configuration ...
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Section 20 Clock Pulse Generator .....................................................................727 20.1 Overview............................................................................................................................ 727 20.1.1 Block Diagram...................................................................................................... 727 20.1.2 Register Configuration ......................................................................................... 728 20.2 Register Descriptions......................................................................................................... 729 20.2.1 System Clock Control Register (SCKCR) ........................................................... 729 20.3 Oscillator............................................................................................................................ 730 20.3.1 Connecting a Crystal Resonator ........................................................................... 730 ...
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Bus Timing ........................................................................................................... 763 22.3.4 DMAC Timing ..................................................................................................... 775 22.3.5 Timing of On-Chip Supporting Modules ............................................................. 779 22.4 A/D Conversion Characteristics ........................................................................................ 784 22.5 D/A Conversion Characteristics ........................................................................................ 785 22.6 Usage Notes ....................................................................................................................... 785 Appendix A Instruction Set A.1 ...
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... Overview The H8S/2655 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space ...
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Table 1-1 Overview Item Specification CPU • General-register machine — Sixteen 16-bit general registers (also usable as sixteen 8-bit registers • High-speed operation suitable for realtime control — Maximum clock rate: 20 MHz — High-speed arithmetic operations • Instruction set ...
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Table 1-1 Overview (cont) Item Specification Data transfer — Can be activated by internal interrupt or software controller (DTC) — Multiple transfers or multiple types of transfer possible for one — Transfer possible in repeat mode, block transfer mode, etc. ...
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... Single-chip mode Advanced On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode Model Name Low-Voltage Version 10 2 HD6472655VTE HD6472655VF HD6432655(***)TE HD6432655(***)F HD6432653(***)TE HD6432653(***)F External Data Bus On-Chip Initial Maximum ROM Value Value Disabled ...
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Block Diagram Figure 1-1 shows an internal block diagram of the H8S/2655 Series EXTAL XTAL STBY RES WDTOVF NMI PF / ø Port PF ...
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Pin Description 1.3.1 Pin Arrangement Figures 1-2 and 1-3 show the pin arrangement of the H8S/2655 Series ...
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Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2655 Series in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. TFP-120 FP-128 Mode ...
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Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. TFP-120 FP-128 Mode /IRQ /IRQ /IRQ 6 2 — — ...
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Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. TFP-120 FP-128 Mode /RxD /SCK /SCK ...
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Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. TFP-120 FP-128 Mode 1 RES NMI STBY XTAL 78 86 EXTAL ...
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Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. TFP-120 FP-128 Mode 1 102 112 P4 / 103 113 AV SS 104 114 V SS 105 115 P1 / TIOCB2/ ...
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Pin Functions Table 1-3 outlines the pin functions of the H8S/2655 Series. Table 1-3 Pin Functions Type Symbol Power Clock XTAL EXTAL ø Pin No. TFP-120 FP-128 I/O 1, 33, 5, 39, Input 52, 76, ...
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Table 1-3 Pin Functions (cont) Type Symbol Operating mode control MD 0 RES System control STBY BREQ BREQO BACK 14 Pin No. TFP-120 FP-128 I/O 115 to 125 to Input 113 123 73 81 Input 75 83 ...
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Table 1-3 Pin Functions (cont) Type Symbol Interrupts NMI IRQ to 7 IRQ 0 Address bus Data bus Bus control HWR Pin No. ...
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Table 1-3 Pin Functions (cont) Type Symbol LWR Bus control CAS/ OE WAIT LCAS DREQ DMA controller , 1 DREQ (DMAC) 0 TEND , 1 TEND 0 DACK , 1 DACK 0 16 Pin No. TFP-120 FP-128 I ...
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Table 1-3 Pin Functions (cont) Type Symbol 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Pin No. TFP-120 FP-128 I/O 105, 107, 115, 117, ...
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Table 1-3 Pin Functions (cont) Type Symbol Programmable pulse generator PO 0 (PPG) 8-bit timer TMO , 0 TMO 1 TMCI , 0 TMCI 1 TMRI , 0 TMRI 1 WDTOVF Watchdog timer (WDT) Serial TxD , ...
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Table 1-3 Pin Functions (cont) Type Symbol A/D converter AV CC and D/A converters ref I/O ports ...
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Table 1-3 Pin Functions (cont) Type Symbol I/O ports ...
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Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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High-speed operation — All frequently-used instructions execute in one or two states — Maximum clock rate — 8/16/32-bit register-register add/subtract : 50 ns — 8 8-bit register-register multiply — 16 8-bit register-register divide — 16 16-bit register-register multiply — ...
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Enhanced instructions — Addressing modes of bit-manipulation instructions have been enhanced. — Signed multiply and divide instructions have been added. — A multiply-and-accumulate instruction has been added. — Two-bit shift instructions have been added. — Instructions for saving and ...
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CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum ...
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Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2). The exception vector table differs depending ...
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Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Address Space Figure 2-6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 ...
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Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
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Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ...
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Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB Legend ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most ...
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Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Instruction Set 2.6.1 Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Data transfer MOV POP* LDM, STM MOVFPE, MOVTPE Arithmetic ADD, SUB, CMP, ...
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Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. — @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 @aa:24 @aa:16 @aa:8 @–ERn/@ERn+ @(d:32,ERn) @(d:16,ERn) @ERn Rn #xx 39 ...
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Table 2-2 Combinations of Instructions and Addressing Modes (Cont) Function Instruction Logic AND, OR, BWL BWL operations XOR NOT — BWL — BWL Shift Bit manipulation — B Bcc, BSR — — Branch JMP, JSR — — RTS — — ...
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Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ERn General ...
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Table 2-3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Note: * Size refers to the operand size. B: Byte W: Word L: Longword 42 Size* Function B/W/L (EAs) Rd, Rs Moves data ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Note: * Size refers to the operand size. B: Byte W: Word L: Longword Size* Function ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS MAC CLRMAC LDMAC STMAC Note: * Size refers to the operand size. B: Byte W: Word L: Longword 44 Size* Function B/W Rd ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Size refers to the operand size. B: Byte W: Word L: Longword Size* ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Note: * Size refers to the operand size. B: Byte 46 Size* Function B 1 (<bit-No.> of <EAd>) Sets a ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Note: * Size refers to the operand size. B: Byte Size* Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction Branch Bcc instructions JMP BSR JSR RTS 48 Size* Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Note: * Size refers to the operand size. B: Byte W: Word Size* Function — Starts trap-instruction exception handling. ...
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Table 2-3 Instructions Classified by Function (cont) Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W 2.6.4 Basic Instruction Formats The H8S/2655 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field ...
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Figure 2-12 shows examples of instruction formats. (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2-12 ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, ...
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Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding ...
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Table 2-6 Effective Address Calculation No. Addressing Mode and Instruction Format 1 Register direct (Rn Register indirect (@ERn Register indirect with displacement @(d:16, ERn) or @(d:32, ERn disp 4 Register indirect ...
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Table 2-6 Effective Address Calculation (cont) No. Addressing Mode and Instruction Format 5 Absolute address @aa:8 op abs @aa:16 op abs @aa:24 op abs @aa:32 op abs Immediate #xx:8/#xx:16/#xx: IMM Effective Address Calculation 31 Don’t care 31 Don’t ...
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Table 2-6 Effective Address Calculation (cont) No. Addressing Mode and Instruction Format 7 Program-counter relative @(d:8, PC)/@(d:16, PC) disp op 8 Memory indirect @@aa:8 • Normal mode op abs • Advanced mode op abs Effective Address Calculation ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state ...
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End of bus request Bus-released state End of exception handling Exception-handling state RES = high *1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
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Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from ...
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Normal mode SP CCR CCR* PC (16 bits) (a) Interrupt control modes 0 and 1 Advanced mode SP CCR PC (24 bits) (c) Interrupt control modes 0 and 1 Note: *Ignored when returning. Figure 2-16 Stack Structure after Exception Handling ...
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Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than ...
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Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred "state." The memory cycle or ...
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Address bus AS RD HWR, LWR Data bus Figure 2-18 Pin States during On-Chip Memory Access 66 Bus cycle T1 Unchanged High High High High-impedance state ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access ...
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Address bus AS RD HWR, LWR Data bus Figure 2-20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2655 Series has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width ...
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Note that the functions of each pin depend on the operating mode. The H8S/2655 Series can be used only in modes This means that the mode pins must be set to select one of these modes. Do ...
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Register Descriptions 3.2.1 Mode Control Register (MDCR) Bit : 7 — Initial value : 1 R/W : — Note: * Determined by pins MD MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2655 ...
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Bit 6—Reserved: Read-only bit, always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt ...
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Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an ...
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Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part ...
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Pin Functions in Each Operating Mode The pin functions of ports vary depending on the operating mode. Table 3-3 shows their functions in each operating mode. Table 3-3 Pin Functions in Each Mode Port Mode 1 ...
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Memory Map in Each Operating Mode Figure 3-1 shows a memory map for each of the operating modes. The address space is 64 kbytes in modes (normal modes), and 16 Mbytes in modes ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 3 On-chip RAM* H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers External address H'FFFF08 space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or ...
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For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception sources. Table 4-2 lists the exception ...
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Table 4-2 Exception Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ 0 IRQ 1 IRQ 2 IRQ ...
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Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2655 Series enters the reset state. A reset initializes the internal state of the CPU and the registers ...
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Reset Sequence The H8S/2655 Series enters the reset state when the RES pin goes low. To ensure that the H8S/2655 Series is reset, hold the RES pin low for at least power-up. To reset the H8S/2655 ...
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RES Address bus RD HWR, LWR (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) ...
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Traces Traces are enabled in interrupt control modes 2 and 3. Trace mode is not activated in interrupt control modes 0 and 1, irrespective of the state of the T bit. For details of interrupt control modes, see section ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ 52 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
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Stack Status after Exception Handling Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) (a) Interrupt control modes 0 and 1 Note: * Ignored on return. ...
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Notes on Use of the Stack When accessing word data or longword data, the H8S/2655 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2655 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Four interrupt control modes — Any of four interrupt control modes can be ...
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Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input Internal interrupt request WOVI to TEI Interrupt controller Legend : IRQ sense control register ISCR : IRQ ...
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Table 5-1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ External interrupt requests 5.1.4 Register Configuration Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers Name System control register IRQ sense ...
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Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 MACS Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 ...
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Interrupt Control Registers (ICRA to ICRC) Bit : 7 ICR7 ICR6 0 Initial value : R/W : R/W The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than ...
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Table 5-4 Correspondence between Interrupt Sources and IPR Settings Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK As shown in table 5-4, multiple interrupts are assigned to one IPR. Setting a value in the range from ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ to IRQ . Bit : IRQ7E IRQ6E Initial value : 0 R/W R/W : IER is initialized ...
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Bits IRQ Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ 7 (IRQ0SCA, IRQ0SCB) Bits IRQ7SCB to IRQ7SCA to IRQ0SCB IRQ0SCA 5.2.6 IRQ Status Register (ISR) 7 Bit ...
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Bits 7 to 0—IRQ to IRQ 7 0 IRQ interrupt requests. 0 Bit n IRQnF Description 0 [Clearing conditions] (Initial value) • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When interrupt ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ be used to restore the H8S/2655 Series from software standby mode. NMI Interrupt: NMI is the highest-priority ...
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IRQnSCA, IRQnSCB Edge/level detection circuit IRQ input n Note Figure 5-2 Block Diagram of Interrupts IRQ Figure 5-3 shows the timing of setting IRQnF. ø IRQ n input pin IRQnF The vector numbers for IRQ Detection ...
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Internal Interrupts There are 52 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. ...
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Table 5-5 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 SWDTEND (software activation interrupt end) WOVI (interval timer) CMI (compare match) Reserved ...
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Table 5-5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow ...
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Table 5-5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Interrupt Source CMIA0 (compare match A0) CMIB0 (compare match B0) OVI0 (overflow 0) Reserved CMIA1 (compare match A1) CMIB1 (compare match B1) OVI1 (overflow 1) Reserved DEND0A (channel 0/ channel ...
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Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2655 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. ...
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Figure 5-4 shows a block diagram of the priority decision circuit. ICR Interrupt acceptance Interrupt control and source 3-level mask control Interrupt control modes 0, 1, and 3 Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control ...
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Table 5-7 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Control Mode Legend * : Don't care (2) 8-Level Control In interrupt control modes 2 and 3, 8-level mask level determination is performed according to ...
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Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR and ICR, acceptance of multiple interrupts is enabled, and so ...
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Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared ...
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Program execution status Interrupt generated? Yes Control level 1 interrupt? Yes No IRQ 0 No Yes IRQ 1 Yes TEI2 Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to ...
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Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR, and ICR. • Control level 0 interrupt requests are enabled when ...
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If an interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, ...
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Control level 1 interrupt? IRQ 0 Yes Figure 5-7 Flowchart of Procedure Up to Interrupt Acceptance in 114 Program execution status Interrupt generated? Yes Yes NMI No No Yes No IRQ No IRQ 1 Yes TEI2 Yes No I=0 Yes ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5-8 shows a ...
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Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5-8 Flowchart of Procedure Up to Interrupt Acceptance in 116 Program execution status No Interrupt generated? Yes Yes NMI Level 6 interrupt? No Yes No Mask ...
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Interrupt Control Mode 3 Control of IRQ interrupts and on-chip supporting module interrupts is performed by a combination of interrupt masking set by the I and UI bits and control level setting by ICR, based on 8-level interrupt mask ...
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If an interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, it performs interrupt acceptance control. ...
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Highest-priority selection Priority level > mask level? Figure 5-10 Flowchart of Procedure Up to Interrupt Acceptance in 5.4.6 Interrupt Exception Handling Sequence Figure 5-11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control ...
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Figure 5-11 Interrupt Exception Handling 120 ...
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Interrupt Response Times The H8S/2655 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5-10 shows ...
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Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is ...
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Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or ...
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DTC and DMAC Activation by Interrupt 5.6.1 Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Activation request ...
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Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected ...
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Table 5-12 Interrupt Source Selection and Clearing Control Settings DMAC DTC DTA DTCE Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt ...
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Overview The H8S/2655 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, ...
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Pseudo-SRAM (PSRAM) direct interface — PSRAM interface can be set for areas (in advanced mode) — Burst operation (static column mode) — T cycle insertion to secure RAS precharging time P — Choice of auto-refreshing or ...
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Block Diagram Figure 6-1 shows a block diagram of the bus controller External bus control signals BREQ BACK BREQO WAIT External DRAM/ PSRAM control signals Figure 6-1 Block Diagram of Bus Controller Area decoder ...
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Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Address strobe Read High write/write enable/upper write enable Low write/lower column address strobe/lower write enable Chip select 0 Chip select 1 Chip ...
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Table 6-1 Bus Controller Pins (cont) Name Chip select 4/row address strobe 4 Chip select 5/row address strobe 5 Chip select 6 Chip select 7 Upper column address strobe/ column address strobe/output enable/refresh Lower column strobe Wait Bus request Bus ...
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Register Configuration Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 Modes Initial value : R/W Mode 4 Initial value : R/W ABWCR is an 8-bit ...
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Access State Control Register (ASTCR) 7 Bit : AST7 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area enabled, and bits ...
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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Bus Control Register H (BCRH) Bit : 7 ICIS1 Initial value : 1 R/W : R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to ...
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Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states Bit 3—Burst Cycle Select 0 (BRSTS0): Selects ...
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Bus Control Register L (BCRL) 7 Bit : BRLE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the area partition unit, the LCAS signal, DMAC ...
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Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode. Bit 5 EAE Description 0 Addresses H'010000 to H'01FFFF are in on-chip ROM (in ...
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Bit 2—Area Partition Unit Select (ASS): Selects the area partition unit. Bit 2 ASS Description 0 Area partition unit is 128 kbytes (1 Mbit) 1 Area partition unit is 2 Mbytes (16 Mbits) Bit 1—Write Data Buffer Enable (WDBE): Selects ...
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Memory Control Register (MCR) Bit : 7 TPC Initial value : 0 R/W : R/W MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and ...
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Bit 5—RAS Down Mode (RCDM): When areas are designated as DRAM space and access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode), ...
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Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on ...
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DRAM Control Register (DRAMCR) Bit : 7 RFSHE Initial value : 0 R/W : R/W DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized ...
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Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), this bit selects whether normal refreshing (CAS-before-RAS refreshing for the DRAM interface, auto- refreshing for the PSRAM interface) or self-refreshing is performed. Bit 5 RMODE Description 0 • ...
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Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 internal clocks obtained by dividing the system clock (ø). When the input clock is selected with bits ...
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Refresh Timer/Counter (RTCNT) Bit : 7 Initial value : 0 R/W : R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare ...
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Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 128-kbyte or 2-Mbyte units, and performs bus control for external space in area ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Table 6-3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The H8S/2655 Series memory interfaces comprise a basic bus interface ...
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Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on ...
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Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the ...
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Chip Select Signals The H8S/2655 Series can output chip select signals (CS driven low when the corresponding external space area is accessed. In normal mode, only the CS signal can be output. Figure 6-3 shows an example of CS ...
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Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment ...
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Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D for accesses. The amount of data that can be accessed at one time is one byte ...
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Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data bus write, ...
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Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed , the upper half (D The LWR pin is fixed high. Wait states cannot ...
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Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states can be inserted. ø Address ...
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Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D for the even address, and the lower half (D Wait states cannot ...
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Address bus Read HWR LWR Write Note Figure 6-9 Bus Timing for 16-Bit 2-State Access ...
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Address bus D Read HWR Write Note Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) 164 ...
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Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D for the even address, and the lower half (D Wait states ...
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Address bus Read HWR LWR Write Note Figure 6-12 Bus ...
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Address bus Read HWR LWR Write Note Figure 6-13 Bus ...
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Wait Control When accessing external space, the H8S/2655 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin w wait insertion ...
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Figure 6-14 shows an example of wait state insertion timing. ø WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus Note: indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing ...
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DRAM Interface 6.5.1 Overview When the H8S/2655 Series is in advanced mode, external space areas can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the ...
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Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as ...
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Pins Used for DRAM Interface Table 6-7 shows the pins used for DRAM interfacing and their functions. Table 6-7 DRAM Interface Pins With DRAM Pin Setting HWR WE/UWE LWR LCAS/LWE LCAS LCAS CS RAS RAS 3 ...
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Basic Timing Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and ...
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Precharge State Control When DRAM is accessed, RAS precharging time must be secured. With the H8S/2655 Series, one T state is always inserted when DRAM space is accessed. This can be changed to two T p setting the TPC ...
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Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion When the bit in ASTCR corresponding to an area designated ...
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WAIT Address bus CS (RAS) n CAS Read Data bus HWR, LWR Write Data bus Notes: indicates the timing of WAIT pin sampling Figure 6-17 Example of Wait State Insertion Timing 176 By program ...
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Byte Access Control When DRAM with a 16 configuration is connected, the control signals needed for byte access differ depending on the kind of DRAM used. Either the 2-CAS system or the 2-WE system can be selected according to ...
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(RAS) n CAS (UCAS) Byte control LCAS (LCAS) HWR (WE) Note Figure 6-18 (a) 2-CAS System (LCASS = 0) Control Timing (Upper Byte Write Access ...
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H8S/2655 (Address shift size set to 9 bits) CS (RAS) CAS (UCAS) LWR (LCAS) HWR (WE Figure 6-19 (a) Example of 2-CAS System (LCASS = 0) DRAM Connection H8S/2655 (Address shift size set to 9 bits) ...
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A CS HWR (UWE) Byte control LWR (LWE) Note Figure 6-20 2-WE System Control Timing (Upper Byte Access) H8S/2655 (Address shift size set to 8 bits) Note Figure 6-21 Example ...
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Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number ...