HD6433712P HITACHI, HD6433712P Datasheet
HD6433712P
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HD6433712P Summary of contents
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H8/3714 Series HD6433712 HD6433713 HD6433714, HD6473714 Hardware Manual ...
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The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU, and is ideal for realtime control. The H8/3714 Series ...
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Section 1 Overview ......................................................................................................... 1.1 Overview......................................................................................................................... 1.2 Internal Block Diagram .................................................................................................. 1.3 Pin Arrangement and Functions ..................................................................................... 1.3.1 Pin Arrangement................................................................................................. 1.3.2 Pin Functions ...................................................................................................... Section 2 CPU ................................................................................................................... 15 2.1 Overview......................................................................................................................... 15 2.1.1 Features............................................................................................................... 15 2.1.2 Address Space..................................................................................................... 16 2.1.3 ...
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Application Notes ........................................................................................................... 49 2.8.1 Notes on Data Access ......................................................................................... 49 2.8.2 Notes on Bit Manipulation.................................................................................. 51 Section 3 System Control 3.1 Overview......................................................................................................................... 55 3.2 Exception Handling ........................................................................................................ 55 3.2.1 Reset ................................................................................................................... 55 3.2.2 Interrupts............................................................................................................. 56 3.2.3 Interrupt Control ...
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Section 6 Clock Pulse Generators 6.1 Overview......................................................................................................................... 99 6.1.1 Block Diagram.................................................................................................... 99 6.2 System Clock Generator ................................................................................................. 100 6.3 Subclock Generator ........................................................................................................ 103 Section 7 I/O Ports ........................................................................................................... 105 7.1 Overview......................................................................................................................... 105 7.1.1 Port Types and Mask Options............................................................................. 107 7.1.2 ...
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Port 9 ............................................................................................................................ 128 7.8.1 Overview............................................................................................................. 128 7.8.2 Register Configuration and Description ............................................................. 128 7.8.3 Pin Functions ...................................................................................................... 132 7.8.4 Pin States ............................................................................................................ 134 Section 8 Timers ............................................................................................................... 135 8.1 Overview......................................................................................................................... 135 8.1.1 Prescaler Operation............................................................................................. 136 8.2 Timer A........................................................................................................................... ...
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Register Descriptions...................................................................................................... 171 9.2.1 PWM Control Register (PWCR) ........................................................................ 171 9.2.2 PWM Data Registers U and L (PWDRU, PWDRL) .......................................... 172 9.3 Operation ........................................................................................................................ 173 Section 10 SCI1 .................................................................................................................. 175 10.1 Overview......................................................................................................................... 175 10.1.1 Features............................................................................................................... 175 10.1.2 Block Diagram.................................................................................................... ...
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Clock................................................................................................................... 198 11.3.3 Data Transfer Format.......................................................................................... 198 11.3.4 Data Transmit/Receive ....................................................................................... 200 11.4 Interrupts......................................................................................................................... 202 11.5 Application Notes ........................................................................................................... 202 Section 12 VFD Controller/Driver 12.1 Overview......................................................................................................................... 203 12.1.1 Features............................................................................................................... 203 12.1.2 Block Diagram.................................................................................................... 203 12.1.3 Pin Configuration................................................................................................ 204 12.1.4 ...
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Section 14 Electrical Specifications 14.1 Absolute Maximum Ratings ........................................................................................... 229 14.2 HD6473714 Electrical Characteristics ........................................................................... 230 14.2.1 HD6473714 DC Characteristics ......................................................................... 230 14.2.2 HD6473714 AC Characteristics ......................................................................... 236 14.2.3 HD6473714 A/D Converter Characteristics....................................................... 239 14.3 HD6433712, HD6433713 and HD6433714 Electrical ...
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... ROM and 384 bytes of RAM in the H8/3713 kbytes of ROM and 512 bytes of RAM in the H8/3714, providing a choice for systems of different sizes. The ZTAT™* versions of the H8/3714 come with user-programmable PROM. Table 1 summarizes the features of the H8/3714 Series. Note: * ZTAT (zero turn-around time trademark of Hitachi, Ltd. Section 1 Overview 1 ...
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Table 1-1 Features Item Description CPU General-register architecture • General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed • Max. operating speed: 4.19 MHz • Add/subtract: 0.5 µs (operating at • Multiply/divide: 3.5 µs (operating ...
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Table 1-1 Features (cont) Item Description Timers • Timer A: 8-bit interval timer Count-up timer with selection of eight internal clock signals divided from the system clock ( )* and four clock signals divided from the subclock ( SUB • ...
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... Built-in pulse generators for system clock and subclock • Timer A can run on the subclock for use as a time base Product lineup Mask ROM Version ZTAT HD6433714H HD6433714P HD6433713H HD6433713P HD6433712H HD6433712P , IRQ 5 Product Code Version HD6473714H HD6473714P — — — ...
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Internal Block Diagram Figure 1 internal block diagram of the H8/3714 Series. Subclock pulse generator P9 /PWM 0 P9 /SCK / / /SCK /SI /CS ...
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Pin Arrangement and Functions 1.3.1 Pin Arrangement The pin arrangements for the H8/3714 Series are shown in figure 1-2 (FP-64A) and figure 1-3 (DP-64S / / /AN ...
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/PWM /SCK / / /SCK / /UD ...
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Pin Functions 1. List of pin functions Table 1-2 lists the pin functions of the LSI. Table 1-2 List of Pin Functions Pin No. FP-64A DP-64S Name and Function ...
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Table 1-2 List of Pin Functions (cont) Pin No. FP-64A DP-64S Name and Function / / / / / ...
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Table 1-2 List of Pin Functions (cont) Pin No. FP-64A DP-64S Name and Function ...
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Pin functions Table 1-3 explains the functions of each pin in more detail. Table 1-3 Pin Functions Type Symbol FP-64A DP-64S I/O Power V CC supply pins disp Clock pins OSC 1 ...
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Table 1-3 Pin Functions (cont) Type Symbol FP-64A DP-64S I/O RES System control TEST Interrupt pins IRQ 0 IRQ 1 IRQ 4 IRQ 5 Pin No. Name and Functions 17 26 Input Reset: When this pin goes to low level, ...
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Table 1-3 Pin Functions (cont) Type Symbol FP-64A DP-64S I/O Timer pins IRQ 0 IRQ 1 UD EVENT TMOE 14-bit PWM pin PWM Serial SO 1 communication SO 2 interface (SCI pins SI 2 SCK 1 SCK 2 ...
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Table 1-3 Pin Functions (cont) Type Symbol FP-64A DP-64S I/O I/O ports ...
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Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features The main features of the H8/300L CPU are listed ...
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Address Space The H8/300L CPU supports an address space kbytes for storing program code and data. The memory map varies with the ROM size. Figure 2-1 gives memory map. H'0000 H'002B H'3FFF H'5FFF H'7DFF H'FD80 ...
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Register Configuration Figure 2-2 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H Control registers 15 ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H ...
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Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For ...
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Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-4. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2-5 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address ...
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Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. Address Modes 1 Register direct 2 Register indirect ...
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Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the ...
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Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 ...
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Table 2-2 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct Register indirect, @ Register indirect with displacement, @(d:16, Rn) ...
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Table 2-2 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format 5 Absolute address @aa abs @aa: abs 6 Immediate #xx IMM #xx: IMM 7 Program-counter relative ...
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Table 2-2 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format 8 Memory indirect, @@aa abs Notation: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation ...
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Instruction Set The H8/300L CPU can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data ...
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Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) <EAd> Destination operand (EAs) <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag ...
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Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-6 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) Moves data between two general registers or between a general register ...
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Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-6 Data Transfer ...
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Arithmetic Operations Table 2-5 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, Shift Operations for their object codes. Table 2-5 Arithmetic Instructions Instruction Size* Function ADD B/W Rd ± Rs SUB Performs addition or subtraction on data ...
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Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction Size* Function AND B Rd Performs a logical AND operation on a general register and another general register or immediate data. ...
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Figure 2-7 shows the instruction code format of arithmetic, logic, and shift instructions Notation: op: Operation field rm, rn: Register field IMM: Immediate data ...
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Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-8 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory to 1. The bit ...
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Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function BXOR B C XORs the carry flag with a specified bit in a general register or memory and stores the result in the carry flag. BIXOR B C XORs the carry flag ...
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Notation: op: Operation field rm, rn: Register ...
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Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-8 Bit Manipulation Instruction Codes (cont IMM ...
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Branching Instructions Table 2-9 describes the branching instructions. Table 2-9 Branching Instructions Instruction Size Function Bcc — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI ...
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Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2-9 Branching Instruction Codes 8 7 disp 8 ...
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System Control Instructions Table 2-10 describes the system control instructions. Figure 2-10 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* Function RTE — Returns from an exception-handling routine. SLEEP — Causes a transition from active ...
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Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-10 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-11 shows its object code ...
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Notation: op: Operation field Figure 2-11 Block Data Transfer Instruction Code Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by ...
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CPU States 2.6.1 Overview There are three CPU states: program execution state, program halt state, and exception-handling state. Program execution state includes active mode and subactive mode. In program halt state there are sleep mode, standby mode, and watch ...
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Reset state Reset occurs Program halt state Note: On the transitions between modes, see 3.3, System Modes. 2.6.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are two modes in this state, ...
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Basic Operation Timing CPU operation is synchronized by a clock ( system clock oscillator circuit, or the subclock ( denotes in active mode and i Generators. The period from the rising edge of memory cycle or bus cycle consists ...
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Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states. The data bus width is 8 bits, so access is made in byte size only. This means that two instructions must be used for a word ...
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Application Notes The following points are to be observed in using the H8/300L CPU. 2.8.1 Notes on Data Access 1. The address space of the H8/300L CPU includes some empty areas in addition to the RAM, registers, and ROM ...
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H'0000 Interrupt vector area (44 bytes) H'002B On-chip ROM *1 H'7DFF *2 H'FD80 On-chip RAM (320 bytes) H'FEC0 Used also for VFD display RAM (64 bytes) H'FF00 On-chip RAM (128 bytes) H'FF7F H'FF80 32-byte data buffer H'FF9F H'FFA0 Internal I/O ...
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Notes on Bit Manipulation The H8/300L CPU executes bit manipulation instructions by a read-modify-write operation on 8-bit data. When bit manipulation instructions are executed in the cases illustrated below, care must be taken since the operation may affect other ...
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As noted above, the H8/300L CPU executes bit manipulation instructions by a read-modify-write operation on 8-bit data. Since the same address is used for the I/O port data register and reading of pin input, a bit manipulation instruction designating a ...
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Table 2-12 lists the registers that share the same address, while table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers Assigned to the Same Address Register Name Timer load register B/timer counter B Timer load register C/timer ...
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Section 3 System Control 3.1 Overview This section explains the reset state, exception handling, and system modes. 3.2 Exception Handling Exception handling includes processing of reset exceptions and of interrupts. Table 3-1 summarizes the exception sources and their priorities. Reset ...
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Reset state RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program starting address (3) First instruction of program 3.2.2 Interrupts The interrupt sources include external ...
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Table 3-2 Interrupt Sources Priority Interrupt High Reset *1 (Reserved) IRQ 0 IRQ 1 *1 (Reserved) *1 (Reserved) IRQ 4 IRQ 5 Key scan Timer A overflow Timer B overflow Timer C overflow Timer D overflow Timer E overflow Direct ...
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Interrupt Control Registers Table 3-3 lists the registers that are used to control interrupts. Table 3-3 Interrupt Control Registers Register Name Port mode register 1 IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt enable ...
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Bit 7: Noise cancel (NOISE CANCEL) This bit enables or disables the noise canceller function of pin IRQ Bit 7 NOISE CANCEL Description 0 Disables the noise canceller function of pin IRQ 1 Enables the noise canceller function of pin ...
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Bit 1: P1 /IRQ pin function switch (IRQC1 Bit 1 IRQC1 Description 0 P1 /IRQ pin functions /IRQ pin functions as IRQ 1 1 Bit 0: P1 /IRQ pin function switch (IRQC0) ...
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Bit 1: IRQ pin input edge select (IEG1) 1 Bit 1 IEG1 Description 0 Falling edge of IRQ 1 Rising edge of IRQ Bit 0: IRQ pin input edge select (IEG0) 0 Bit 0 IEG0 Description 0 Falling edge of ...
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Interrupt enable register 2 (IENR2) Bit 7 — Initial value 0 Read/Write R/W IENR2 is an 8-bit read/write register that enables or disables direct transfer interrupts and timer overflow interrupts. Bits 7 and 6: Reserved bits ...
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Bit 7: A/D converter interrupt enable (IENAD) Bit 7 IENAD Description 0 Disables interrupt requests by IRRAD. 1 Enables interrupt requests by IRRAD. Bit 6: Key scan interrupt enable (IENKS) Bit 6 IENKS Description 0 Disables interrupt requests by IRRKS. ...
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Bits 5 and 4: IRQ and IRQ 5 Bits 5 and 4 IRRI5, IRRI4 Description 0 No interrupt request from the corresponding pin (IRQ 1 Setting condition: Set when the corresponding pin (IRQ designated for interrupt input in PMR1 and ...
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Bit 5: Direct transfer interrupt request (IRRDT) Bits 5 IRRDT Description 0 No direct transfer interrupt request. 1 Setting conditions: In subactive mode, when the system control register 2 (SYSCR2) DTON bit = 1, the system control register 1 (SYSCR1) ...
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Bit 6: Key scan interrupt request (IRRKS) Bit 6 IRRKS Description 0 No key scan interrupt request. 1 Setting conditions: When the VFD controller/driver requests a key scan interrupt, the IRRKS flag is set to 1. Clearing method: Cleared when ...
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When an IRQ , IRQ , IRQ , or IRQ priority is from IRQ (high) to IRQ 0 A noise canceller function can be selected for IRQ circuit samples the IRQ input every 256 states. If ...
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Program execution state No IRQ 0 No Yes IRQ 1 Yes CCR contents saved Notation: PC: Program counter CCR: Condition code register I: I bit of CCR Figure 3-3 Flow Up to Interrupt Acceptance No Interrupt request? Yes 14 interrupts ...
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The following operations take place when an interrupt occurs. 1. When an interrupt is requested by external interrupt pin input peripheral module, an interrupt request signal is sent to the interrupt controller. 2. When the interrupt controller ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling Notation Upper 8 bits of program counter (PC Lower 8 bits of ...
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Interrupt is accepted Interrupt level decision and wait for Instruction end of instruction prefetch Interrupt request signal Internal address bus (1) Internal read signal Internal write signal Internal data bus (2) (16 bits) (1) Instruction prefetch address (Instruction is not ...
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Return from an Interrupt After completion of interrupt handling, the handler routine ends by executing an RTE instruction, to resume the original program from the point the interrupt. When RTE is executed, the values saved on the stack are ...
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Valid Interrupts in Each Mode Table 3-5 shows the valid interrupts in each mode. For details of the modes, see 3.3, System Modes. Table 3-5 Valid Interrupts in Each Mode Interrupt IRQ 0 IRQ 1 IRQ 4 IRQ 5 ...
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Notes on Stack Area Use When word data is accessed in the H8/300L Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer ...
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System Modes The H8/300L CPU is equipped with power-down modes for minimizing power dissipation. These and the other system modes are described below. There are five modes altogether, as follows. • Active mode • Sleep mode • Standby mode ...
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Active Mode In active mode, the CPU executes instructions in synchronization with the system clock. 3.3.2 Low-Power Operation Mode The H8/300L CPU supports four low-power operation modes: sleep mode, standby mode, watch mode, and subactive mode. These modes are ...
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Table 3-6 shows the internal states in each mode. Table 3-6 Internal States in Operation Modes Function System clock Subclock CPU operation Instructions RAM Registers I/O Peripheral module IRQ 0 interrupts IRQ 1 IRQ , IRQ 4 Timer A Timer ...
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Sleep mode Operation in sleep mode is described below. • Transition to sleep mode The system goes from active mode to sleep mode when a SLEEP instruction is executed while the SSBY bit in system control register 1 (SYSCR1) ...
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Clearing standby mode Standby mode is cleared by an external interrupt (IRQ — Clearing by interrupt (IRQ When an IRQ or IRQ 1 time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a ...
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Clearing watch mode Watch mode is cleared by a time-base interrupt from timer IRQ input at the pin. RES — Clearing by timer A time-base interrupt or IRQ When timer A overflows or an IRQ control ...
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Clearing subactive mode Subactive mode is cleared by a SLEEP instruction or by input at the — Clearing by SLEEP instruction When a SLEEP instruction is executed in subactive mode, subactive mode is cleared. If the DTON bit of ...
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Application Notes 1. In order to ensure sufficient time for the clock pulse generator to reach stable operation after clearing of standby mode or watch mode, or after a direct transfer from subactive to active mode, bits STS2 to ...
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System Control Registers Table 3-7 shows how the system control registers (SYSCR1 and SYSCR2) are configured. These two registers are used to control the power-down modes. Table 3-7 Register Configuration Name System control register 1 System control register 2 ...
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Bits Standby timer select (STS2 to STS0) When a mode in which the system clock is stopped (standby, watch, or subactive mode) is cleared, the system waits for stable clock operation for a time ...
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System Control Register 2 (SYSCR2) Bit 7 — Initial value 1 Read/Write — Note: * Write is enabled only in subactive mode. Note: * Write is enabled only in subactive mode. SYSCR2 is an 8-bit read/write register for control ...
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Overview The H8/3714 has 32 kbytes of on-chip mask ROM. The H8/3713 has 24 kbytes, and the H8/3712 has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two- state access for ...
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PROM Mode 4.2.1 Selection of PROM Mode If the on-chip ROM is a PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the HN27C256H. ...
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H8/3714 FP-64A DP-64S 17 26 RES ...
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Address in MCU mode H'0000 On-chip ROM H'7DFF Figure 4-3 Memory Map in PROM Mode 90 Address in PROM mode H'0000 H'7DFF ...
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Programming The write, verify, and other modes are selected as shown in table 4-3 in PROM mode. Table 4-3 Mode Selection in PROM Mode CE Mode Write L Verify H Programming disabled H Notation: L: Low level H: High ...
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V = 6.0 V ± 0. Yes No n < Error Figure 4-4 High-Speed Programming Flow Chart Start Select write or verify mode = 12.5 V ± 0 ...
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Table 4-4 DC Characteristics (preliminary) (Conditions 6.0 V ±0. Item , OE, CE Input high level voltage , OE, CE Input low level voltage Output ...
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... Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C256H or to Intel specifications will result in a correct V 2. Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned ...
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Avoid touching the socket adapter or chip during programming, since this may cause contact faults and write errors. 4. Some commercially available EPROM programmers execute a device test before writing, reading, or verifying. The device test is a leakage ...
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... If write errors occur repeatedly while the same PROM programmer is being used, stop programming and check for problems in the PROM programmer and socket adapter, etc. Please notify your Hitachi representative of any problems occurring during programming or in screening after high-temperature baking. Write program and verify written data ...
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Overview The H8/3714 has 512 bytes of high-speed static RAM on-chip. The H8/3713 and the H8/3712 each has 384 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte ...
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Section 6 Clock Pulse Generators 6.1 Overview Clock oscillator circuitry (CPG: Clock Pulse Generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, ...
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System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator providing external clock input. 1. Connecting a crystal oscillator • Circuit configuration Figure 6-2 shows a ...
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Connecting a ceramic oscillator • Circuit configuration Figure 6-4 shows a typical method of connecting a ceramic oscillator Ceramic oscillator Figure 6-4 Typical Connection to Ceramic Oscillator 3. Notes on board design ...
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To be avoided Figure 6-5 Board Design of Oscillator Circuit 4. External clock input • Circuit configuration When an external clock is used input at pin OSC Figure 6-6 shows a typical connection. OSC ...
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Subclock Generator 1. Connecting a 32.768 kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz crystal oscillator, as shown in figure 6-7. Follow the same precautions as noted for the system ...
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Figure 6-9 Pin Connection When Not Using Subclock 104 V CC Open H8/300 Fig. 6-7 ...
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Overview The H8/3714 Series has five 8-bit I/O ports (of which four are high-voltage ports), one 6-bit I/O port*, and one 8-bit input port. Table 7-1 indicates the functions of each port. Ports 1 and 9 are standard input/output ...
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Table 1 Port Functions Port Description Port 0 8-bit standard input port Port 1 Pin P1 : 1-bit high-voltage 7 input port Pin P1 : 1-bit standard input 6 port Pins and P1 5 ...
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Port Types and Mask Options The choice of I/O pin options and the resulting states are shown in table 7-2. Upon reset, the PDR, PCR, and PMR registers are initialized, cancelling the choices of peripheral functions. When the chip ...
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Table 7-3 shows the mask options with mask ROM versions. A mask ROM version is compatible with a ZTAT™ version only when C and D options are selected for all pins. Table 7-3 Correspondence between Mask ROM and ZTAT Type ...
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MOS pull-up CMOS buffer Notes: 1. Dotted lines indicate mask option low-power modes (except sleep mode), the MOS pull-up is switched off by a STBY signal. Figure 7-1 MOS Pull-Up Circuit Configuration Table 7-4 MOS ...
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MOS Pull-Down Ports and 7, which are high-voltage I/O ports, can be designated by mask option as having or not having MOS pull-down resistors for their (PMOS open-drain) outputs. (This does not ™ apply to ZTAT ...
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Port 0 7.2.1 Overview Port 8-bit standard input-only port. Figure 7-3 shows the pin configuration. 7.2.2 Register Configuration and Description Table 7-5 shows the port 0 register configuration. Table 7-5 Port 0 Registers Name Abbrev. Port ...
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Bit n ANn Explanation 0 Pin P0 /AN is used for general input Pin P0 / analog input channel Port data register 0 (PDR0) Bit 7 PDR0 7 Initial value — Read/Write ...
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Port 1 7.3.1 Overview Port 1 consists of four standard I/O pins, one standard input-only pin, and one high-voltage input- only pin. Figure 7-4 shows the pin configuration. Port 1 Note: IO indicates input/output. 7.3.2 Register Configuration and Description ...
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PMR1 is an 8-bit read/write register that controls the selection of pin functions for pins /IRQ , P1 EVENT cancellation function on and off. Upon reset, PMR1 is initialized to H'0C. Note: ...
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Bit 4: P1 /IRQ pin function switch (IRQC4 This bit selects whether pin P1 Bit 4 IRQC4 Explanation 0 P1 /IRQ pin functions /IRQ pin functions for IRQ 4 4 Note: * ...
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Port control register 1 (PCR1) Bit 7 — Initial value 1 Read/Write — PCR1 is an 8-bit register for controlling whether each of port 1 pins P1 functions as an input pin or output pin. Setting a PCR1 bit ...
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Port mode register 4 (PMR4) Bit 7 TEO TEO ON Initial value 0 Read/Write R/W PMR4 is an 8-bit read/write register that switches the P1 TMOE pin waveform output. Bits are reserved; they always read 1, ...
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Pin Functions Table 7-9 shows the port 1 pin functions. Table 7-9 Port 1 Pin Functions Pin Pin Functions and Selection Method P1 /V Selected by mask option 7 disp P1 high-voltage input pin 7 P1 /EVENT Function is ...
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Pin States Table 7-10 shows the port 1 pin states in each operating mode. Table 7-10 Port 1 Pin States Pins Reset P1 /V High 7 disp impedance or V disp P1 /EVENT, High 6 P1 /IRQ / impedance ...
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Port 4 7.4.1 Overview Port 8-bit high-voltage I/O port. Figure 7-5 shows the pin configuration. Note: IO indicates input/output. 7.4.2 Register Configuration and Description Table 7-11 shows the port 4 register configuration. Table 7-11 Port 4 ...
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Pin Functions Table 7-12 shows the port 4 pin functions. Table 7-12 Port 4 Pin Functions Pin Pin Functions and Selection Method P4 /FS to After designation of the segment pins to be used in bits SR4 to SR0 ...
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Port 5 7.5.1 Overview Port 8-bit high-voltage I/O port. Figure 7-6 shows the pin configuration. Note: IO indicates input/output. 7.5.2 Register Configuration and Description Table 7-14 shows the port 5 register configuration. Table 7-14 Port 5 ...
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Pin Functions Table 7-15 shows the port 5 pin functions. Table 7-15 Port 5 Pin Functions Pin Pin Functions and Selection Method P5 /FS to After designation of the segment pins to be used in bits SR4 to SR0 ...
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Port 6 7.6.1 Overview Port 8-bit high-voltage I/O port. Figure 7-7 shows the pin configuration. Port 6 Note: IO indicates input/output. 7.6.2 Register Configuration and Description Table 7-17 shows the port 6 register configuration. Table 7-17 ...
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Pin Functions Table 7-18 shows the port 6 pin functions. Table 7-18 Port 6 Pin Functions Pin Pin Functions and Selection Method P6 /FD /FS to After designation of the digit pins and segment pins to be used in ...
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Port 7 7.7.1 Overview Port 8-bit high-voltage I/O port. Figure 7-8 shows the pin configuration. Note: IO indicates input/output. 7.7.2 Register Configuration and Description Table 7-20 shows the port 7 register configuration. Table 7-20 Port 7 ...
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Pin Functions Table 7-21 shows the port 7 pin functions. Table 7-21 Port 7 Pin Functions Pin Pin Functions and Selection Method P7 /FD to After designation of the digit pins to be used, in bits DR3 to DR0 ...
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Port 9 7.8.1 Overview Port 8-bit standard I/O port. Figure 7-9 shows the pin configuration. Port 9 Note: IO indicates input/output. 7.8.2 Register Configuration and Description Table 7-23 shows the port 9 register configuration. Table 7-23 ...
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Bit 7: P9 /UD pin function switch (UP/DOWN) 7 This bit selects whether pin P9 control input. Up/down control input (UD) is valid only when bit TMC6 = 1 in timer mode register C (TMC). Bit 7 UP/DOWN Description 0 ...
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Bit 3: P9 /SO pin function switch (SO1 This bit selects whether pin P9 Bit 3 SO1 Description 0 P9 /SO pin functions for /SO pin functions for Bit 2: ...
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Port control register 9 (PCR9) Bit 7 PCR9 PCR9 7 Initial value 0 Read/Write W PCR9 is an 8-bit register for controlling whether each of port 9 pins P9 input or output pin. Setting a PCR9 bit to 1 ...
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Pin Functions Table 7-24 shows the port 9 pin functions. Table 7-24 Port 9 Pin Functions Pin Pin Functions and Selection Method P9 /UD Functions are switched as follows by means of the UP/DOWN bit* in PMR2 7 and ...
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Table 7-24 Port 9 Pin Functions (cont) Pin Pin Functions and Selection Method P9 /SCK Functions are switched as follows by means of bit SCK2* in PMR2, bits PS1 4 2 and PS0* in serial control register 2 (SCR2), and ...
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Table 7-24 Port 9 Pin Functions (cont) Pin Pin Functions and Selection Method P9 /SCK Functions are switched as follows by means of bit SCK1 in PMR2,* bits 1 1 SMR13 to SMR10 in serial mode register 1 (SMR1)*, and ...
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Overview The H8/3714 Series provides on-chip two prescalers (prescaler S and prescaler W) with different input clocks, and five timers (timers A through E). Prescaler 13-bit counter clocked by the system clock ( = f used ...
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Prescaler Operation 1. Prescaler S (PSS) Prescaler 13-bit counter using the system clock ( = f input clock cycle causes prescaler S to increment once. Prescaler S is initialized to H'0000 by a reset, and starts ...
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System f OSC OSC 1 clock pulse OSC generator 2 Subclock pulse X generator 2 System Prescaler S clock divider 1/2 Subclock Prescaler W divider SUB 1/8 System clock selection (LSON bit in system control register ...
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Timer A 8.2.1 Overview Timer 8-bit interval timer. It can be connected to a 32.768 kHz crystal oscillator for use as a real-time clock time base. 1. Features Features of timer A are given below. • ...
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Register configuration Table 8-2 shows the register configuration of timer A. Table 8-2 Timer A Registers Name Abbrev. Timer mode register A TMA Timer counter A TCA 8.2.2 Register Descriptions 1. Timer mode register A (TMA) Bit 7 — ...
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Bits Clock select (TMA2 to TMA0) Bits select the clock input to TCA. The selection is made as follows by the combination of these bits and bit TMA3. Bit 3 Bit 2 Bit 1 ...
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Timer counter A (TCA) Bit 7 TCA7 Initial value 0 Read/Write R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to ...
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Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a time base for a real-time clock by counting clock signals output by prescaler W. The overflow period of timer A ...
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Timer B 8.3.1 Overview Timer 8-bit up-counter that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer B are given below. • ...
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Pin configuration Table 8-3 shows the timer B pin configuration. Table 8-3 Pin Configuration Name Abbrev. Event input pin P1 4. Register configuration Table 8-4 shows the register configuration of timer B. Table 8-4 Timer B Registers Name Abbrev. ...
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Bits Reserved bits Bits are reserved; they always read 1, and cannot be modified. Bits Clock select (TMB2 to TMB0) Bits select the clock input to TCB. For ...
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Timer load register B (TLB) Bit 7 TLB7 Initial value 0 Read/Write W TLB is an 8-bit write-only register for setting the reload value of timer counter B (TCB). When a reload value is set in TLB, the same ...
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Auto-reload timer operation Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer. When a reload value is set in TLB, the same value is loaded into TCB, becoming the value from ...
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Timer C 8.4.1 Overview Timer 8-bit up/down counter that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer C are ...
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Pin configuration Table 8-5 shows the timer C pin configuration. Table 8-5 Pin Configuration Name Event input pin Up/down select pin 4. Register configuration Table 8-6 shows the register configuration of timer C. Table 8-6 Timer C Registers Name ...
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Bit 7: Auto-reload function select (TMC7) Bit 7 selects the auto-reload function of timer C. Bit 7 TMC7 Description 0 Interval timer function selected. 1 Auto-reload function selected. Bit 6: Counter up/down control 1 (TMC6) This bit selects whether the ...
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Bits select the clock input to TCC. For external clock counting, either the rising or falling edge can be selected. Bit 2 Bit 1 Bit 0 TMC2 TMC1 TMC0 Description Internal clock: /8192. 0 ...
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Timer load register C (TLC) Bit 7 TLC7 Initial value 0 Read/Write W TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set in TLC, the same value is loaded ...
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After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow), setting bit IRRTC interrupt request register 2 (IRR2). If bit IENTC = 1 in interrupt enable register ...
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Timer D 8.5.1 Overview Timer 8-bit event counter, which is incremented by input of an external event signal. Either rising or falling edges of the external event signal can be counted. 1. Features Features of timer ...
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Pin configuration Table 8-7 shows the timer D pin configuration. Table 8-7 Pin Configuration Name Abbrev. Event input pin P1 /EVENT 6 4. Register configuration Table 8-8 shows the register configuration of timer D. Table 8-8 Timer D Registers ...
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Bits Reserved bits Bits are reserved; they always read 1, and cannot be modified. Bit 0: Edge select (EDG) Bit 0 selects the rising or falling edge of input at external event pin P1 ...
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Timer Operation 1. Operation on external clock Timer D operates on an external clock input at pin P1 The rising or falling edge of this input is selected by the EDG bit in timer mode register D (TMD). After ...
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Timer E 8.6.1 Overview Timer 8-bit up-counter that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. In addition, it can output a square wave with a ...
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Block diagram Figure 8-6 shows a block diagram of timer E. Prescaler S Notation: TME: Timer mode register E TCE: Timer counter E TLE: Timer load register E IRRTE: Timer E overflow interrupt request flag (interrupt request register 2) ...
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Register configuration Table 8-10 shows the register configuration of timer E. Table 8-10 Timer E Registers Name Abbrev. Timer mode register E TME Timer counter E TCE Timer load register E TLE Port mode register 4 PMR4 8.6.2 Register ...
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Bits Clock select (TME2 to TME0) Bits select the clock input to TCE. Bit 2 Bit 1 Bit 0 TME2 TME1 TME0 Description Internal clock: /8192 Internal clock: ...
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Timer load register E (TLE) Bit 7 TLE7 Initial value 0 Read/Write W TLE is an 8-bit write-only register for setting the reload value of TCE. When a reload value is set in TLE, the same value is loaded ...
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Bit 7: Timer E output select (TEO) Bit 6: Timer E output on/off (TEO ON) Bit 5: Fixed frequency select (FREQ) Bit 4: Variable frequency select (VRFR) P1 /IRQ /TMOE pin functions are switched as follows, by means of bits ...
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Timer Operation Timer 8-bit up-counter that is incremented each time a clock pulse is input. It functions as an interval or auto-reload timer. It can also output a square wave having a 50% duty cycle. Each ...
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Square wave output A 50% duty square wave can be output at pin P1 port mode register 4 (PMR4) and bit IRQC5 in port mode register 1 (PMR1). When bit VRFR = 0 in PMR4, the square wave has ...
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Table 8-11 Frequencies of Output Waveforms Generated by Timer E Overflow Internal Clock Count Time 8 (250 kHz) 8 µs /32 (62.5 kHz) 32 µs /128 (15.62 kHz) 128 µs /256 (7.8125 kHz) 256 µs /512 (3.9062 kHz) 512 µs ...
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Interrupts Timer interrupts are requested when a timer overflows or underflows. Each timer is assigned its own vector address. The priority of interrupts is in the order of timer A (high) to timer E (low). Further ...
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Overview The H8/3714 Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 9.1.1 Features Features of the 14-bit PWM are as follows. • Choice ...
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Pin Configuration Table 9-1 shows the output pin assigned to the 14-bit PWM. Table 9-1 Pin Configuration Name PWM waveform output pin 9.1.4 Register Configuration Table 9-2 shows the register configuration of the 14-bit PWM. Table 9-2 Register Configuration ...
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Register Descriptions 9.2.1 PWM Control Register (PWCR) Bit 7 — Initial value 1 Read/Write — PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FE. Bits Reserved bits Bits ...
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PWM Data Registers U and L (PWDRU, PWDRL) PWDRU Bit 7 — Initial value 1 Read/Write — PWDRL Bit 7 PWDRL7 PWDRL6 Initial value 0 Read/Write W PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 ...
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Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 2 (PMR2 that pin P9 PWM output. 2. Set bit PWCR0 in the PWM control ...
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f64 Figure ...
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Overview Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. 10.1.1 Features SCI1 features are as follows. • Choice of 8-bit or 16-bit data transfer • Choice of eight internal clock sources ( /1024, ...
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Pin Configuration Table 10-1 shows the SCI1 pin configuration. Table 10-1 Pin Configuration Name Abbrev. SCI1 clock pin SCK SCI1 data input pin SI SCI1 data output pin SO 10.1.4 Register Configuration Table 10-2 shows the SCI1 register configuration. ...
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Register Descriptions 10.2.1 Serial Mode Register 1 (SMR1) Bit 7 — SMR16 Initial value 1 Read/Write — SMR1 is an 8-bit write-only register, for selecting the operation mode and the prescaler divider ratio. Another function is to initialize the ...
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Bits Clock select (SMR13 to SMR10) Bits select the clock supplied to SCI1. Bit 3 Bit 2 Bit 1 Bit 0 SMR13 SMR12 SMR11 SMR10 Pin SCK ...
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Serial Data Register L1 (SDRL1) Bit 7 SDRL17 SDRL16 Initial value * Read/Write R/W Note: * Not fixed SDRL1 is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data register ...
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Bit 7: Extended data bit (SO1 LAST BIT) Bit 7 holds the last bit of transmitted data after transmission ends. Output from pin SO1 can be altered by software by modifying this bit either before or after transmission. If this ...
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Bit 2: Pin P9 /SI function switch (SI1 Bit 2 selects whether pin P9 2 Bit 2 SI1 Description 0 Pin P9 /SI functions Pin P9 /SI functions clearing ...
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Operation 10.3.1 Overview SCI1 sends and receives data in synchronization with clock pulses. SCI1 operation modes are set by bits serial mode register 1 (SMR1) and bits port mode register 2 ...
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Data Transfer Format Figure 10-2 shows the synchronous data transfer format. Data can be sent and received in lengths of 8 bits or 16 bits. Data is sent and received starting from the least significant bit, in LSB-first format. ...
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Set bit SMR16 in SMR1 and set bits SMR15 and SMR14 to a value other than 00, designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10. Writing data to ...
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After data reception is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. • Read the received data from SDRL1 and SDRU1, as follows. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, ...
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In simultaneous data transmit/receive, the transmit operation and receive operation described in 10.3.4 sections 2 and 3 take place at the same time. See those sections for further details. During a transmit/receive operation, a dummy read of SMR1 will result ...
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Serial start (SMR1 dummy read) pending state SMR1 write Serial clock pending state octal counter = 000 or hexadecimal counter = 0000 10.3.6 Serial Clock Error Detection In the transfer state extraneous pulse is superimposed on the normal ...
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Transfer complete (IRRS1 Disable interrupts IRRS1 SMR1 write IRRS1 = 1? Normal completion Figure 10-4 Procedure for Detecting Serial Clock Errors 10.3.7 Interrupts SCI1 can generate interrupts for completion of transfer and for transmit/receive errors. These interrupts are assigned to ...
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Overview Serial communication interface 2 (SCI2) has a 32-byte data buffer, for synchronous serial transfer bytes of data in one operation. 11.1.1 Features SCI2 features are as follows. • Automatic transfer ...
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Pin Configuration Table 11-1 shows the SCI2 pin configuration. Table 11-1 Pin Configuration Name SCI2 clock pin SCI2 data input pin SCI2 data output pin SCI2 chip select output pin Note: Functions of pins P9 4 (PMR2) and port ...
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Register Descriptions 11.2.1 Start Address Register (STAR) Bit 7 — Initial value 1 Read/Write — STAR is an 8-bit read/write register, for designating the transfer start address in the memory area from H'FF80 to H'FF9F allocated to the 32-byte ...
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Serial Control Register 2 (SCR2) Bit 7 — Initial value 1 Read/Write — SCR2 is an 8-bit read/write register, for selecting whether SCI2 transmits or receives, for gap insertion during continuous transfer, and for serial clock selection. Upon reset, ...
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Bits 1 and 0: Serial clock select (PS1 to PS0) Bits 1 and 0 select one of three internal clock sources or an external clock. Bit 1 Bit 2 PS1 PS1 PS0 PS0 Pin SCK Clock Source ...
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Bit 4 SO2 LAST BIT Description 0 Output from pin SO 1 Output from pin SO Bit 3: Overrun flag (OVR) If the amount of data transferred exceeds the buffer size setting extraneous pulse is superimposed on ...
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Bit 0: Start/busy flag (STF) Setting bit starts an SCI2 transfer operation. This bit stays at 1 during the transfer, and is cleared to 0 after the transfer is complete. It can therefore be used as a ...