X1243 Xicor, X1243 Datasheet
X1243
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X1243 Summary of contents
Page 1
... Vback pin allows the device to be backed non- rechargeable battery. The RTC is fully operational from 1.8 to 5.5 volts. The X1243 provides a 2K byte EEPROM array, giving a safe, secure memory for critical user and configura- tion data. This memory is unaffected by complete fail- ure of the main and backup supplies. ...
Page 2
... The RTC has leap-year correction and a century byte. The clock will also correct for months hav- ing fewer than 31 days and will have a bit that controls 24 hour or AM/PM format. When the X1243 powers up after the loss of both V increment until at least one byte is written to the clock register ...
Page 3
... X1243 the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occuring during a read are unaffected by the read operation. Writing to the Real Time Clock The time and date may be set by writing to the RTC registers ...
Page 4
... ESC0 REAL TIME CLOCK REGISTERS Year 2000 (Y2K) The X1243 has a century byte that “rolls over” from when the years byte changes from 99 to 00. The Y2K byte can contain only the values 20. The alarm enable bits are located in the MSB of the particular register. When all enable bits are set to ‘ ...
Page 5
... Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The X1243 does not correct for the leap year in the year 2100. STATUS REGISTER (SR) The Status Register is located in the RTC area at address 003FH ...
Page 6
... A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 3. Table 3. Block Protect Bits Protected Addresses X1243 None ...
Page 7
... X1243 initiate another change to the CCR contents. If the sequence is not completed for any reason (by send- ing an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. —Writing all zeros to the status register resets both the WEL and RWEL bits. — ...
Page 8
... After receiving the 8 data bits, the X1243 again responds with an acknowledge. The master then ter- minates the transfer by generating a stop condition. The X1243 then begins an internal write cycle of the data to the nonvolatile memory. During the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master ...
Page 9
... Signals from the Slave Page Write The X1243 has a page write operation initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit more bytes to the memory array and more bytes to the clock/control registers ...
Page 10
... X1243 the address counter would point to location 7 on the page that was just written. If the master supplies more than the maximum bytes in a page, then the previously loaded data is over written by the new data, one byte at a time. The master terminates the Data Byte loading by issu- ing a stop condition, which causes the device to begin the non-volatile write cycle ...
Page 11
... In a similar operation, called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 11. The X1243 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter ...
Page 12
... X1243 DEVICE ADDRESSING Following a start condition, the master must output a Slave Address Byte. The first four bits of the Slave Address Byte specify access to the EEPROM array or to the CCR. Slave bits ‘1010’ access the EEPROM array. Slave bits ‘1101’ access the CCR. ...
Page 13
... X1243 Device Identifier Array 1 0 CCR Figure 13. Slave Address, Word Address, and Data Bytes (64 Byte pages A10 Slave Address Byte R/W Byte 0 High Order Word Address A8 Byte 1 ...
Page 14
... X1243 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias.................. -65˚C to +135˚C Storage Temperature....................... -65˚C to +150˚C Voltage on any pin with respect to ground-1.0V to 7.0V DC Output Current .............................................5 mA Lead Temperature (Soldering, 10 Seconds) .... 300˚C DC OPERATING CHARACTERISTICS Temperature = -40°c to +85°c, unless otherwise stated.) Symbol ...
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... X1243 0V. BACK Others=GND or V SDA SCL BACK GND GND or V SDA CC, CLK 3.0mA at 5V, 1.5mA at 1. Threshold voltages based on the higher of Vcc or Vback. 10: Driven by external 32.768KHz square wave oscillator on X1, X2 open. ...
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... X1243 AC Specifications - T = -40˚C to +85˚ Symbol f SCL Clock Frequency SCL (1) t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus must be free before a new transmission BUF can start t Clock LOW Time LOW ...
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... X1243 Write Cycle Timing SCL 8th bit of last byte SDA Power Up Timing Symbol (1) t Time from Power Up to Read PUR (1) t Time from Power Up to Write PUW 1. Delays are measured from the time V odically sampled and not 100% tested. Nonvolatile Write Cycle Timing ...
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... Part Mark Information 8-Lead TSSOP EYWW XXXXX X1243 = 2.7 to 5.5V +70°C 1243I = 2.7 to 5.5V, -40 to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fi ...