UPD70F3210GK-9EU NEC, UPD70F3210GK-9EU Datasheet
UPD70F3210GK-9EU
Related parts for UPD70F3210GK-9EU
UPD70F3210GK-9EU Summary of contents
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User’s Manual V850ES/KF1 32-Bit Single-Chip Microcontrollers Hardware V850ES/KF1: µ µ µ µ PD703208 µ µ µ µ PD703208(A) µ µ µ µ PD703208Y µ µ µ µ PD703208Y(A) µ µ µ µ PD703209 µ µ µ µ PD703209(A) µ µ ...
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User’s Manual U15862EJ3V0UD ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...
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... Addition of Caution in 1.4.4 Pin configuration (top view) (V850ES/KJ1 Addition of description in CHAPTER 2 PIN FUNCTIONS and addition of Table 2-1 Pin I/O Buffer Power Supplies pp.93, 95 Modification of description on recommended connection of P70 to P77, P78 to P715, IC, V I/O Circuits and Recommended Connection of Unused Pins p. 134 Modification of description in 3.4.8 (2) Access to special on-chip peripheral I/O registers p. 285 Modification of description in 5 ...
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Pages p. 430 Addition of 13.6 (3) A/D converter sampling time and A/D conversion start delay time p. 432 Addition of 13.7 How to Read A/D Converter Characteristics Table p. 441 Addition of description in CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 and design application systems using these products. The target products are as follows. • Standard products: µ PD703208, 703208Y, 703209, 703209Y, ...
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PD703208 µ PD703208Y µ PD703209 µ PD703209Y µ PD703210 µ PD703210Y µ PD703212 µ PD703212Y µ PD703213 µ PD703213Y µ PD703214 To find the details of a register where the name is known → Refer to APPENDIX A REGISTER ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KF1, V850ES/KG1, and V850ES/KJ1 V850ES Architecture User’s Manual V850ES/KF1, V850ES/KG1, V850ES/KJ1 Hardware User’s Manual Documents related ...
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... CHAPTER 2 PIN FUNCTIONS ................................................................................................................55 2.1 List of Pin Functions ..................................................................................................................55 2.2 Pin Status.....................................................................................................................................64 2.3 Description of Pin Functions .....................................................................................................66 2.3.1 V850ES/KF1...................................................................................................................................66 2.3.2 V850ES/KG1 ..................................................................................................................................74 2.3.3 V850ES/KJ1 ...................................................................................................................................83 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins..........................................93 2.5 Pin I/O Circuits ............................................................................................................................96 CHAPTER 3 CPU FUNCTIONS ..............................................................................................................98 3.1 Features .......................................................................................................................................98 3.2 CPU Register Set ........................................................................................................................99 3.2.1 Program register set .....................................................................................................................100 3.2.2 System register set.......................................................................................................................101 3.3 Operation Modes.......................................................................................................................107 3 ...
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CHAPTER 4 PORT FUNCTIONS ..........................................................................................................137 4.1 Features .................................................................................................................................... 137 4.1.1 V850ES/KF1 ................................................................................................................................ 137 4.1.2 V850ES/KG1 ............................................................................................................................... 137 4.1.3 V850ES/KJ1 ................................................................................................................................ 137 4.2 Basic Port Configuration......................................................................................................... 138 4.2.1 V850ES/KF1 ................................................................................................................................ 138 4.2.2 V850ES/KG1 ............................................................................................................................... 139 4.2.3 V850ES/KJ1 ................................................................................................................................ 140 4.3 Port ...
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Bus Hold Function ....................................................................................................................282 5.8.1 Functional outline .........................................................................................................................282 5.8.2 Bus hold procedure ......................................................................................................................283 5.8.3 Operation in power save mode.....................................................................................................283 5.9 Bus Priority................................................................................................................................284 5.10 Boundary Operation Conditions .............................................................................................284 5.10.1 Program space .............................................................................................................................284 5.10.2 Data space ...................................................................................................................................284 5.11 Bus Timing.................................................................................................................................285 5.12 ...
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Cautions ...................................................................................................................................... 368 CHAPTER 9 8-BIT TIMERS H0 AND H1............................................................................................369 9.1 Functions .................................................................................................................................. 369 9.2 Configuration............................................................................................................................ 369 9.3 Control Registers ..................................................................................................................... 372 9.4 Operation .................................................................................................................................. 376 9.4.1 Operation as interval timer........................................................................................................... 376 9.4.2 PWM pulse generator mode operation ........................................................................................ ...
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Operation ...................................................................................................................................428 13.5.1 Basic operation.............................................................................................................................428 13.5.2 Conversion operation (software trigger mode) .............................................................................429 13.5.3 Power fail monitoring function ......................................................................................................429 13.6 Cautions.....................................................................................................................................430 13.7 How to Read A/D Converter Characteristics Table ...............................................................432 CHAPTER 14 D/A CONVERTER ..........................................................................................................436 14.1 Functions ...................................................................................................................................436 14.2 Configuration.............................................................................................................................437 ...
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Functions .................................................................................................................................. 501 17.2 Configuration............................................................................................................................ 502 17.3 Control Registers ..................................................................................................................... 504 17.4 Operation .................................................................................................................................. 513 17.4.1 Operation stop mode ................................................................................................................... 513 17.4.2 3-wire serial I/O mode.................................................................................................................. 513 17.4.3 3-wire serial I/O mode with automatic transmit/receive function .................................................. 521 2 ...
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Noise elimination for NMI pin........................................................................................................619 19.2.5 Edge detection function for NMI pin..............................................................................................620 19.3 Maskable Interrupts ..................................................................................................................622 19.3.1 Operation......................................................................................................................................622 19.3.2 Restore.........................................................................................................................................624 19.3.3 Priorities of maskable interrupts ...................................................................................................625 19.3.4 Interrupt control register (xxlCn) ...................................................................................................629 19.3.5 Interrupt mask registers ...
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Overview ................................................................................................................................... 671 22.2 Configuration............................................................................................................................ 671 22.3 Operation .................................................................................................................................. 672 CHAPTER 23 REGULATOR ..................................................................................................................675 23.1 Overview ................................................................................................................................... 675 23.2 Operation .................................................................................................................................. 675 CHAPTER 24 ROM CORRECTION FUNCTION..................................................................................677 24.1 Overview ................................................................................................................................... 677 24.2 Control Registers ..................................................................................................................... 678 24.2.1 Correction address ...
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Figure No. 3-1 CPU Address Space .................................................................................................................................. 108 3-2 Address Space Image................................................................................................................................ 109 3-3 Data Memory Map (Physical Addresses) ................................................................................................... 111 3-4 Program Memory Map ............................................................................................................................... 112 3-5 Internal ROM/Internal Flash Memory Area (128 KB) ................................................................................. 113 3-6 Internal ROM ...
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Figure No. 4-34 Block Diagram of PCM4 and PCM5 ...........................................................................................................233 4-35 Block Diagram of PCS0 to PCS3 ...............................................................................................................238 4-36 Block Diagram of PCS4 to PCS7 ...............................................................................................................239 4-37 Block Diagram of PCT0, PCT1, PCT4, and PCT6 .....................................................................................244 4-38 Block Diagram of ...
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... Timing of Interval Timer Operation............................................................................................................. 377 9-4 Register Settings in PWM Pulse Generator Mode ..................................................................................... 379 9-5 Operation Timing in PWM Pulse Generator Mode ..................................................................................... 381 9-6 Connection Example of 8-Bit Timer Hn and 8-Bit Timer/Event Counter 5n................................................ 385 9-7 Transfer Timing.......................................................................................................................................... 386 9-8 Register Settings in Carrier Generator Mode ............................................................................................. 387 9-9 Carrier Generator Mode ............................................................................................................................. 389 10-1 Block Diagram of RTO ...
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Figure No. 12-1 Block Diagram of Watchdog Timer 1..........................................................................................................409 12-2 Block Diagram of Watchdog Timer 2..........................................................................................................416 13-1 Block Diagram of A/D Converter ................................................................................................................420 13-2 Operation Sequence ..................................................................................................................................424 13-3 Relationship Between Analog Input Voltages and A/D Conversion Results...............................................427 13-4 Power Fail ...
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Figure No. 17-1 Block Diagram of CSIAn ............................................................................................................................ 503 17-2 3-Wire Serial I/O Mode Timing................................................................................................................... 518 17-3 Format of Transmit/Receive Data .............................................................................................................. 519 17-4 Transfer Bit Order Switching Circuit........................................................................................................... 520 17-5 Automatic Transmission/Reception Mode Operation Timings.................................................................... 529 17-6 Automatic Transmission/Reception ...
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... Environment for Writing Program to Flash Memory ...................................................................................688 25-5 Communication with Dedicated Flash Programmer (UART0) ....................................................................688 25-6 Communication with Dedicated Flash Programmer (CSI00) ......................................................................689 25-7 Communication with Flash Programmer (CSI00+HS) ................................................................................689 25-8 Example of Connection of V 25-9 Signal Collision (Input Pin of Serial Interface) ............................................................................................692 25-10 Malfunction of Other Device .......................................................................................................................693 25-11 Signal Collision (RESET Pin) .....................................................................................................................694 25-12 Flash Memory Manipulation Procedure ...
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Table No. 2-1 Pin I/O Buffer Power Supplies...................................................................................................................... 55 2-2 Pin Operation Status in Operation Modes of V850ES/KF1 .......................................................................... 64 2-3 Pin Operation Status in Operation Modes of V850ES/KG1 ......................................................................... 65 2-4 Pin Operation Status in Operation Modes of V850ES/KJ1 ...
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Table No. 5-7 Bus Priority.................................................................................................................................................284 6-1 Operation Status of Each Clock .................................................................................................................299 7-1 Configuration of 16-Bit Timer/Event Counters ..............................................................................303 7-2 Valid Edge of TI0n0 Pin and Capture Trigger of CR0n0 Register ..............................................................305 7-3 Valid Edge of TI0n1 ...
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Table No. 17-3 Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values ......................... 509 17-4 CSIA0 Buffer RAM ..................................................................................................................................... 511 17-5 CSIA1 Buffer RAM ..................................................................................................................................... 512 17-6 Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values ...
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Table No. 25-4 Signals Generated by Dedicated Flash Programmer (PG-FP3).................................................................690 25-5 Pins Used by Each Serial Interface............................................................................................................692 25-6 Communication Modes...............................................................................................................................696 25-7 Flash Memory Control Commands.............................................................................................................697 25-8 Response Commands................................................................................................................................698 28-1 Surface Mounting Type Soldering Conditions ............................................................................................745 28 LIST OF TABLES (4/4) ...
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V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Product Lineup V850ES/KJ1 V850ES/KG1 V850ES/KF1 CHAPTER 1 INTRODUCTION 144-pin plastic LQFP (fine pitch) (20 × 20) µ PD70F3217 Flash memory: 128 KB, RAM µ bus version PD70F3217Y µ PD703217 Mask ...
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Differences Between Products Function Timer Part No. 8-Bit 16-Bit TMH Watch WDT µ PD703208 µ PD703208Y µ PD703209 µ PD703209Y µ PD703210 µ PD703210Y µ PD70F3210 µ PD70F3210Y µ PD703212 ...
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V850ES/KF1 1.2.1 Features (V850ES/KF1) Number of instructions: 83 Minimum instruction execution time (operation at main clock (f General-purpose registers: 32 bits × 32 registers Instruction set: Signed multiplication (16 × 16 → 32 clocks ...
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... " " NEC Corporation to know the specification of quality grade on the devices and its recommended applications. ...
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... P06/INTP3 18 P40/SI00 19 P41/SO00 Notes 1. IC: Connect directly normal operation mode ( µ PD70F3210, 70F3210Y Connect SCL0 and SDA0 can be used only for the µ PD703208Y, 703209Y, 703210Y, and 70F3210Y. ...
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... Power supply for port Ground for port SS HLDAK: Hold acknowledge HLDRQ: Hold request IC: Internally connected INTP0 to INTP6: Interrupt request from peripherals KR0 to KR7: Key return NMI: Non-maskable interrupt request P00 to P06: Port 0 P30 to P35, P38, P39: Port 3 P40 to P42: Port 4 ...
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Function block configuration (V850ES/KF1) (1) Internal block diagram NMI INTC INTP0 to INTP6 16-bit TI000, TI001,TI010, TI011 timer/event TO00, TO01 counter 8-bit TI50, TI51 timer/event TO50, TO51 counter 8-bit timer H: TOH0, TOH1 2 ch ...
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... Two 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels are provided on chip. (h) Watch timer This timer counts the reference time (0 ...
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CHAPTER 1 INTRODUCTION (i) Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a ...
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Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O Port Function P0 7-bit I/O General-purpose port P3 8-bit I/O P4 3-bit I/O P5 6-bit I/O P7 8-bit input P9 9-bit I/O ...
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V850ES/KG1 1.3.1 Features (V850ES/KG1) Number of instructions: 83 Minimum instruction execution time (operation at main clock (f General-purpose registers: 32 bits × 32 registers Instruction set: Signed multiplication (16 × 16 → 32 clocks ...
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... " " NEC Corporation to know the specification of quality grade on the devices and its recommended applications. ...
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... P06/INTP3 21 P40/SI00 22 P41/SO00 23 P42/SCK00 24 P30/TXD0 25 Notes 1. IC: Connect directly normal operation mode ( µ PD70F3214, 70F3214Y Connect SCL0 and SDA0 can be used only for the µ PD703212Y, 703213Y, 703214Y, and 70F3214Y. Caution Make EV the same potential can be used when V ...
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... EV : Power supply for port Ground for port SS HLDAK: Hold acknowledge HLDRQ: Hold request IC: Internally connected INTP0 to INTP6: Interrupt request from peripherals KR0 to KR7: Key return NMI: Non-maskable interrupt request P00 to P06: Port 0 P10, P11: Port 1 P30 to P39: Port 3 P40 to P42: ...
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Function block configuration (V850ES/KG1) (1) Internal block diagram NMI INTC INTP0 to INTP6 TI000, TI001, TI010, TI011, 16-bit TI020, TI021, TI030, TI031 timer/event TO00 to TO03 counter 8-bit TI50, TI51 timer/event TO50, TO51 counter 8-bit ...
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... Four 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels are provided on chip. (h) Watch timer This timer counts the reference time (0 ...
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CHAPTER 1 INTRODUCTION (i) Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a ...
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Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O Port Function P0 7-bit I/O General-purpose port P1 2-bit I/O P3 10-bit I/O P4 3-bit I/O P5 6-bit I/O P7 8-bit input ...
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V850ES/KJ1 1.4.1 Features (V850ES/KJ1) Number of instructions: 83 Minimum instruction execution time (operation at main clock (f General-purpose registers: 32 bits × 32 registers Instruction set: Signed multiplication (16 × 16 → 32 clocks ...
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... " " NEC Corporation to know the specification of quality grade on the devices and its recommended applications. ...
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... Note 2 P38/SDA0 35 Note 2 P39/SCL0 36 Notes 1. IC: Connect directly normal operation mode ( µ PD70F3217, 70F3217Y Connect SCL0, SDA0, SCL1, and SDA1 can be used only for the µ PD703216Y, 703217Y, and 70F3217Y. Caution Make EV the same potential ...
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... EV : Power supply for port Ground for port SS HLDAK: Hold acknowledge HLDRQ: Hold request IC: Internally connected INTP0 to INTP6: Interrupt request from peripherals KR0 to KR7: Key return NMI: Non-maskable interrupt request P00 to P06: Port 0 P10, P11: Port 1 P30 to P39: Port 3 P40 to P42: ...
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Function block configuration (V850ES/KJ1) (1) Internal block diagram NMI INTC INTP0 to INTP6 TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, 16-bit TI040, TI041, TI050, TI051 timer/event TO00 to TO05 counter 8-bit TI50, TI51 timer/event TO50, TO51 ...
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... Six 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels are provided on chip. (h) Watch timer This timer counts the reference time (0 ...
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CHAPTER 1 INTRODUCTION (i) Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a ...
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Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O Port Function P0 7-bit I/O General-purpose port P1 2-bit I/O P3 10-bit I/O P4 3-bit I/O P5 6-bit I/O P6 16-bit I/O ...
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The names and functions of the pins of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into three systems; AV between these power supplies and ...
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Pin Name I/O Pull-up Resistor P40 I/O Yes P41 P42 P50 I/O Yes P51 P52 P53 P54 P55 P60 I/O Yes P61 P62 P63 P64 P65 P66 P67 P68 P69 P610 P611 P612 P613 Note P614 No P615 P70 Input ...
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Pin Name I/O Pull-up Resistor P713 Input No Port 7 P714 P715 P80 I/O Yes Port 8 P81 P90 Port 9 I/O Yes P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 PCD0 I/O ...
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Pin Name I/O Pull-up Resistor PCT0 I/O No PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 PDH0 I/O No PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDL0 I/O No PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 ...
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Non-port pins Pin Name I/O Pull-up Resistor A0 Output Yes Address bus for external memory (when using a separate bus A10 A11 A12 A13 A14 A15 A16 Output No Address ...
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... Internal system clock output Chip select output Positive power supply for external Ground potential for external Bus hold acknowledge output Bus hold request input Internally connected External interrupt request input (maskable, analog noise elimination) User’s Manual U15862EJ3V0UD (2/5) Alternate Function Products ...
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... KR6 KR7 NMI Input Yes External interrupt input (non-maskable, analog noise elimination) RD Output No Read strobe signal output for external memory Connecting capacitor for regulator output stabilization REGC – – RESET Input – System reset input RTP00 Output Yes Real-time output port ...
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Pin Name I/O Pull-up Resistor SI00 Input Yes SI01 SI02 SIA0 SIA1 SO00 Output Yes SO01 SO02 SOA0 SOA1 TI000 Input Yes TI001 TI010 TI011 TI020 TI021 TI030 TI031 TI040 TI041 TI050 TI051 TI50 TI51 TO00 Output Yes TO01 TO02 ...
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... WAIT Input No External wait input WR0 Output No Write strobe for external memory (lower 8 bits) WR1 Write strobe for external memory (higher 8 bits) X1 Input No Connecting resonator for main clock X2 – No XT1 Input No Connecting resonator for subclock XT2 – No CHAPTER 2 PIN FUNCTIONS Function User’ ...
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Pin Status The address bus becomes undefined during accesses to the internal RAM and ROM. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. During peripheral I/O access, the address ...
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Table 2-3. Pin Operation Status in Operation Modes of V850ES/KG1 Operating Status Reset Pin AD0 to AD15 (PDL0 to PDL15) Hi A15 (P90 to P915) Hi-Z A16 to A21 (PDH0 to PDH5) Hi-Z WAIT (PCM0) Hi-Z CLKOUT (PCM1) ...
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Description of Pin Functions 2.3.1 V850ES/KF1 (1) P00 to P06 (Port 0) ... I/O Port 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O ...
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RXD0 (receive data) ... Input This is the serial receive data input pin for UART0. (iii) ASCK0 (asynchronous serial clock) ... Input This is the serial baud rate clock input pin for UART0. (iv) TI000, TI001, TI010 (timer input) ...
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P50 to P55 (port 5) ... I/O Port 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P50 to P55 can also be ...
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P70 to P77 (port 7) ... Input Port 8-bit input-only port in which all the pins are fixed to input. In addition to functioning as input ports pins, P70 to P77 can also be used for ...
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TO51 (timer output) ... Output This is the pulse signal output pin for the 8-bit timer. (v) SO01 (serial output) ... Output This is the serial transmit data output pin for CSI01. (vi) SI01 (serial input) ... Input This ...
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HLDRQ (hold request) ... Input This is the input pin by which an external device requests the V850ES/KF1 to release the external address/data bus and strobe pins. This pin supports asynchronous input for CLKOUT. When this pin is active, ...
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... REGC (regulator control) ... Input This is the pin for connecting a capacitor for the regulator. (14) X1, X2 (crystal for main clock) These pins are used to connect the resonator that generates the main clock. An external clock can also be input. (15) XT1, XT2 (crystal for subclock) These pins are used to connect the resonator that generates the subclock ...
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... These are the positive power supply pins. Connect all V (21) V (programming power supply) PP This is a positive power supply pin for the flash memory programming mode provided for products with flash memory. During normal mode operation, connect this pin to V (22) V (ground) SS These are the ground pins. Connect all V (23) IC (internally connected) This is an internally connected pin ...
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V850ES/KG1 (1) P00 to P06 (port 0) ... I/O Port 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can ...
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Control mode P30 to P39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode ...
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SCK00 (serial clock) ... I/O This is the serial clock I/O pin for CSI00. (5) P50 to P55 (port 5) ... I/O Port 6-bit I/O port for which input and output can be set in 1-bit ...
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... Port mode P90 to P915 can be set to input or output in 1-bit units by the port 9 mode register (PM9) (when used as the A0 to A15 pins, mode switching in 16-bit units is necessary). (b) Control mode (alternate function) P90 to P915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (PMC9) ...
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TI020, TI021, TI030, TI031 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (v) TO02, TO03 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (vi) ...
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CLKOUT (clock output) ... Output This is the internal system clock output pin. Since the port mode during the reset period, output is not performed from the CLKOUT pin. To perform CLKOUT output, set this pin ...
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Port mode PCT0, PCT1, PCT4, and PCT6 can be set to input or output in 1-bit units by the port CT mode register (PMCT). (b) Control mode PCT0, PCT1, PCT4, and PCT6 can be set to the port mode ...
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... REGC (regulator control) ... Input This is the pin for connecting a capacitor for the regulator. (15) X1, X2 (crystal for main clock) These pins are used to connect the resonator that generates the main clock. An external clock can also be input. (16) XT1, XT2 (crystal for subclock) These pins are used to connect the resonator that generates the subclock ...
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... V (programming power supply) PP This is the positive power supply pin used for the flash memory programming mode provided for products with flash memory. During normal mode operation, connect this pin to V (26) V (ground) SS These are the ground pins. Connect all V (27) IC (internally connected) This is an internally connected pin ...
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V850ES/KJ1 (1) P00 to P06 (port 0) ... I/O Port 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can ...
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Control mode P30 to P39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode ...
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SCK00 (serial clock) ... I/O This is the serial clock I/O pin for CSI00. (5) P50 to P55 (port 5) ... I/O Port 6-bit I/O port for which input and output can be set in 1-bit ...
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P60 to P615 (port 6) ... I/O Port 16-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P60 to P615 can also be ...
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Control mode (alternate function) P70 to P715 are shared with ANI0 to ANI15, but switching is not possible. (i) ANI0 to ANI15 (analog input) ... Input These are the analog input pins to the A/D converter (ADC). (8) P80, ...
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... P90 to P915 can be set to input or output in 1-bit units by the port 9 mode register (PM9). (b) Control mode (alternate function) P90 to P915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (PMC9) (when used as the A0 to A15 pins, mode switching in 16-bit units is necessary). ( A15 (address bus) ... Output These are the lower 16-bit address output pins within a 24-bit address on the address bus during external access ...
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PCD0 to PCD3 (port CD) ... I/O Port 4-bit I/O port for which input and output can be set in 1-bit units. PCD0 to PCD3 operate as an I/O port. (a) Port mode PCD0 to PCD3 ...
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PCS0 to PCS7 (port CS) ... I/O Port 8-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCS0 to PCS7 can also be used ...
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PDH0 to PDH7 (port DH) ... I/O Port 8-bit I/O port that can be set to input or output in 1-bit units. In addition to functioning as a port, PDH0 to PDH7 can also be used ...
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... V (programming power supply) PP This is the positive power supply pin used for the flash memory programming mode provided for products with flash memory. During normal mode operation, connect this pin to V (29) V (ground) SS These are the ground pins. Connect all V (30) IC (internally connected) This is an internally connected pin ...
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... Pin I/O Circuits and Recommended Connection of Unused Pins Pin Alternate Function P00 TOH0 P01 TOH1 P02 NMI P03 to P06 INTP0 to INTP3 P10 ANO0 P11 ANO1 P30 TXD0 P31 RXD0 P32 ASCK0 P33 TI000/TO00 P34 TI001 P35 TI010/TO01 P36, P37 – Note P38 ...
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... PDH6, PDH7 A22, A23 AV – REF0 AV – REF1 AV – SS Note Only for the µ PD703216Y, 703217Y, and 70F3217Y Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1 94 CHAPTER 2 PIN FUNCTIONS I/O Circuit Type Recommended Connection 10-F Input: Independently connect to EV resistor. Output: Leave open. 8-A 5-W 8-A 5-W 8-A 5-W 10-E 10-F 5-W 10-E 10-F 5-W 8-A 5 Input: Independently connect to BV resistor ...
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... Directly connect kΩ resistor. 2 – Directly connect kΩ resistor. – – – – 16 Directly connect Leave open. User’s Manual U15862EJ3V0UD (3/3) Target Product KG1, KJ1 – KG1, KJ1 – – All products – ...
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Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Input enable Type 5-A Pullup enable V DD Data P-ch Output N-ch disable Input enable Type 5-W Pullup enable ...
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Type 10-F Pullup enable V DD Data P-ch Open drain N-ch Output disable Input enable Type 12-B Pullup enable AV REF1 Data P-ch Output N-ch disable AV SS Input enable P-ch Analog output voltage N-ch Type 13-AE Mask option Data ...
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The CPU of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control. 3.1 Features Number of instructions: Minimum instruction execution time: 50 ...
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CPU Register Set The CPU registers of the V850ES/KF1, V850ES/KG1 and V850ES/KJ1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to ...
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Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. All of these registers can be used as a data variable ...
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System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, ...
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Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the ...
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NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the ...
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Program status word (PSW) A program status word (PSW collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the ...
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Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set to 1 only when the OV flag is set to 1 during saturated operation. Operation ...
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Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and ...
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... After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started. An external device can be connected to the external memory area by setting the PMCDH, PMCDL, PMCCM, PMCCS, and PMCCT registers to the control mode via software. ...
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Address Space 3.4.1 CPU address space The CPU of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 uses a 32-bit architecture and supports linear address space (data space) during operand addressing (data access). When addressing instruction addresses, ...
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Image external memory area in a linear address space (program area MB, internal ROM area, and internal RAM area are supported for instruction address addressing. During operand addressing (data access), ...
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Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow ...
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Memory map The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have reserved areas as shown below. Figure 3-3. Data Memory Map (Physical Addresses) 3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH Access-prohibited area 1000000H 0FFFFFFH External memory area (8 MB) 0800000H 07FFFFFH External memory area ...
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Notes 1. Only for the V850ES/KJ1. Access-prohibited area for the V850ES/KF1 and V850ES/KG1 for the V850ES/KF1 Remark Instruction execution for external ...
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Areas (1) Internal ROM area An area from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM/internal flash memory (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in ...
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Internal ROM/internal flash memory area (96 KB area from 0000000H to 0017FFFH is provided in the following products. Addresses 0018000H to 00FFFFFH are an access-prohibited area. • V850ES/KF1 ( µ PD703209, 703209Y) • V850ES/KG1 ( µ ...
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Interrupt/exception table The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. This group of handler addresses is called an interrupt/exception table. This table is located in the internal ROM area. When ...
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Internal RAM area An area maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area. (a) Internal RAM (6 KB area from 3FFD800H to 3FFEFFFH is provided as physical internal RAM. ...
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CHAPTER 3 CPU FUNCTIONS (b) Internal RAM area (4 KB area from 3FFE000H to 3FFEFFFH is provided as physical internal RAM in the following products. Addresses 3FF0000H to 3FFDFFFH are an access-prohibited area. • V850ES/KF1 ( µ ...
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On-chip peripheral I/O area area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-10. On-Chip Peripheral I/O Area Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode ...
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Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H FFFFF006H Port DH register FFFFF008H Port CS register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF00EH Port ...
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Address Function Register Name FFFFF118H Interrupt control register FFFFF11AH Interrupt control register FFFFF11CH Interrupt control register FFFFF11EH Interrupt control register FFFFF120H Interrupt control register FFFFF122H Interrupt control register FFFFF124H Interrupt control register FFFFF126H Interrupt control register FFFFF128H Interrupt control register ...
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Address Function Register Name FFFFF166H Interrupt control register FFFFF168H Interrupt control register FFFFF1FAH In-service priority register FFFFF1FCH Command register FFFFF1FEH Power save control register FFFFF200H A/D converter mode register FFFFF201H Analog input channel specification register FFFFF202H Power fail comparison mode ...
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Address Function Register Name FFFFF428H Port 4 mode register FFFFF42AH Port 5 mode register FFFF42CH Port 6 mode register FFFFF42CH Port 6 mode register L FFFFF42DH Port 6 mode register H FFFFF430H Port 8 mode register FFFFF432H Port 9 mode ...
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Address Function Register Name FFFFF5C0H 16-bit timer counter 5 FFFFF5C0H 8-bit timer counter 50 FFFFF5C1H 8-bit timer counter 51 FFFFF5C2H 16-bit timer compare register 5 FFFFF5C2H 8-bit timer compare register 50 FFFFF5C3H 8-bit timer compare register 51 FFFFF5C4H Timer clock ...
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Address Function Register Name FFFFF640H 16-bit timer counter 04 FFFFF642H 16-bit timer capture/compare register 040 FFFFF644H 16-bit timer capture/compare register 041 FFFFF646H 16-bit timer mode control register 04 FFFFF647H Prescaler mode register 04 FFFFF648H Capture/compare control register 04 FFFFF649H 16-bit ...
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Address Function Register Name FFFFF84CH Correction address register 3 FFFFF84CH Correction address register 3L FFFFF84EH Correction address register 3H FFFFF880H Correction control register FFFFF8B0H Prescaler mode register FFFFF8B1H Prescaler compare register FFFFFA00H Asynchronous serial interface mode register 0 FFFFFA02H Receive ...
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Address Function Register Name FFFFFC4CH Pull-up resistor option register 6 FFFFFC4CH Pull-up resistor option register 6L FFFFFC4DH Pull-up resistor option register 6H FFFFFC50H Pull-up resistor option register 8 FFFFFC52H Pull-up resistor option register 9 FFFFFC52H Pull-up resistor option register 9L ...
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Address Function Register Name FFFFFD22H Clocked serial interface receive buffer register 2 FFFFFD22H Clocked serial interface receive buffer register 2L FFFFFD24H Clocked serial interface transmit buffer register 2 FFFFFD24H Clocked serial interface transmit buffer register 2L FFFFFD26H Clocked serial interface ...
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Address Function Register Name FFFFFD96H IIC status register 1 FFFFFD9AH IIC flag register 1 FFFFFE00H CSIA0 buffer RAM 0 FFFFFE00H CSIA0 buffer RAM 0L FFFFFE01H CSIA0 buffer RAM 0H FFFFFE02H CSIA0 buffer RAM 1 FFFFFE02H CSIA0 buffer RAM 1L FFFFFE03H ...
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Address Function Register Name FFFFFE1AH CSIA0 buffer RAM D FFFFFE1AH CSIA0 buffer RAM DL FFFFFE1BH CSIA0 buffer RAM DH FFFFFE1CH CSIA0 buffer RAM E FFFFFE1CH CSIA0 buffer RAM EL FFFFFE1DH CSIA0 buffer RAM EH FFFFFE1EH CSIA0 buffer RAM F FFFFFE1EH ...
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Address Function Register Name FFFFFE36H CSIA1 buffer RAM B FFFFFE36H CSIA1 buffer RAM BL FFFFFE37H CSIA1 buffer RAM BH FFFFFE38H CSIA1 buffer RAM C FFFFFE38H CSIA1 buffer RAM CL FFFFFE39H CSIA1 buffer RAM CH FFFFFE3AH CSIA1 buffer RAM D FFFFFE3AH ...
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Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the following three special registers. • Power save control register (PSC) • Processor clock ...
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Cautions 1. Interrupts are not acknowledged for the store instruction for the PRCMD register. This is because continuous execution of store instructions by the program in steps <3> and <4> above is assumed. If another instruction is placed between step ...
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CHAPTER 3 CPU FUNCTIONS The operation conditions of the PRERR flag are described below. (a) Set conditions (PRERR = 1) (i) When a write operation to the special register takes place without write operation being performed to the PRCMD register ...
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Cautions Be sure to set the following register before using the V850ES/KF1, V850ES/KG1 and V850ES/KJ1. • System wait control register (VSWC) After setting the VSWC register, set the other registers as required. When using an external bus, set the ...
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Peripheral Function Watchdog timer 1 (WDT1) WDTM1 <Calculation of number of waits> Watchdog timer 2 (WDT2) WDTM2 16-bit timer/event counters TMC00 to TMC05 Note 1 (TM00 to TM05) Clocked serial interfaces 0 and 1 with CSIA0B0 to ...
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Remark In the calculation for the number of waits: : CPU clock frequency f CPU m: Set value of bits the VSWC register f : Internal system clock CLK When f < 16.6 MHz: 0 CLK ...
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Features 4.1.1 V850ES/KF1 Input-only ports: 8 pins I/O ports: 59 pins Shared with I/O pins of other peripheral functions Input/output can be specified in 1-bit units 4.1.2 V850ES/KG1 Input-only ports: 8 pins I/O ports: 76 pins Shared with I/O ...
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Basic Port Configuration 4.2.1 V850ES/KF1 The V850ES/KF1 incorporates a total of 67 I/O port pins consisting of ports CM, CS, CT, and DL (including 8 input-only port pins). The port configuration is shown ...
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V850ES/KG1 The V850ES/KG1 incorporates a total of 84 I/O port pins consisting of ports CM, CS, CT, DH, and DL (including 8 input-only port pins). The port configuration is shown below. Port ...
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V850ES/KJ1 The V850ES/KJ1 incorporates a total of 128 I/O port pins consisting of ports CD, CM, CS, CT, DH, and DL (including 16 input-only port pins). The port configuration is shown below. Port 0 ...
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Port Configuration Table 4-1. Port Configuration (V850ES/KF1) Item Control register Port mode registers PMn ( CM, CS, CT, DL) Pull-up resistor option registers PUn ( Ports ...
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... Port mode/control mode (alternate function) can be specified in 1-bit units. Specification is made by the port 0 mode control register (PMC0). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 0 (PU0). The valid edge of external interrupts (alternate function) can be specified in 1-bit units. ...
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Registers (a) Port 0 register (P0) The port 0 register (P0 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. After Reset: Undefined R/W P0 ...
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Port 0 mode control register (PMC0) This is an 8-bit register that specifies the port mode or control mode. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W PMC0 0 PMC06 PMC06 0 I/O ...
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... CHAPTER 4 PORT FUNCTIONS (d) Pull-up resistor option register 0 (PU0) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W Address: FFFFFC40H PU0 0 PU06 PU0n Control of on-chip pull-up resistor connection ( ...
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External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies the rising edge as the detection edge for the external interrupt pin. This register can be read/written in 8-bit or 1-bit units. Caution When ...
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Block diagram (port 0) Figure 4-1. Block Diagram of P00 and P01 WR PU PU0 PU0n WR PMC PMC0 PMC0n WR PM PM0 PM0n WR TOHn output PORT Output latch (P0n) RD Remarks 1. PU0: Pull-up resistor option register ...
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Figure 4-2. Block Diagram of P02 to P06 WR PU PU0 PU0n WR INTR INTR0 INTR0n WR INTF INTF0 INTF0n WR PMC PMC0 PMC0n WR PM PM0 PM0n WR PORT Output latch (P0n) Address RD NMI, INTP0 to INTP3 input ...
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... Specification is made by the port 1 register (P1). Port input/output can be specified in 1-bit units. Specification is made by the port 1 mode register (PM1). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 1 (PU1). Port 1 includes the following alternate functions. Table 4-6. Alternate-Function Pins of Port 1 (V850ES/KG1, V850ES/KJ1) ...
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Registers (a) Port 1 register (P1) Port 1 register (P1 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KG1, V850ES/KJ1 After Reset: Undefined ...
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... Pull-up resistor option register 1 (PU1) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. (i) 850ES/KG1, V850ES/KJ1 After Reset: 00H R/W PU1 0 0 PU1n 0 Not connected 1 Connected CHAPTER 4 PORT FUNCTIONS Address: FFFFFC42H ...
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Block diagram (port 1) Figure 4-3. Block Diagram of P10 and P11 PORT Output latch RD Remarks 1. PM1: Port 1 mode register RD: Port 1 read signal WR: Port 1 write register 2. ...
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... Specification is made by the port 3 function register H (PF3H). Control mode 1/control mode 2 specification can be done in 1-bit units. Specification is made by the port 3 function control register (PFC3). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 3 (PU3). CHAPTER 4 PORT FUNCTIONS ...
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Port 3 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 3 (V850ES/KF1) Pin Name Alternate Function Port 3 P30 TXD0 P31 RXD0 P32 ASCK0 P33 TI000/TO00 P34 TI001 P35 TI010/TO01 Note 2 P38 SDA0 Note 2 P39 ...
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Registers (a) Port 3 register (P3) The port 3 register (P3 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits ...
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Port 3 mode register (PM3) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PM3 ...
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Port 3 mode control register (PMC3) This is a 16-bit register that specifies the port mode/control mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the ...
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Port 3 function register H (PF3H) This is an 8-bit register that specifies N-ch open-drain output. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W PF3H 0 PF3n 0 N-ch open-drain output (when used ...
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... Pull-up resistor option register 3 (PU3) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1, V850ES/KJ1 After Reset: 00H R/W PU3 0 0 PU3n 0 Not connected 1 Connected Caution An on-chip pull-up resistor can be provided for P3n by a mask option. ...
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Block diagram (port PMC PMC3 PMC30 PORT TXD0 output Output latch RD Remark PU3: Pull-up resistor option register 3 PM3: Port 3 mode register PMC3: Port 3 mode control register RD: Port ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P31, P32, and P34 WR PU PU3 PU3n WR PMC PMC3 PMC3n WR PM PM3 PM3n WR PORT Output latch (P3n) Address RD RXD0, ASCK0, TI001 input Remarks 1. PU3: Pull-up ...
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Figure 4-6. Block Diagram of P33 and P35 WR PU PU3 PU3n WR PF PFC3 PFC3n WR PMC PMC3 PMC3n WR PM PM3 PM3n WR PORT TO00, TO01 output Output latch (P3n) Address RD TI000, TI010 input Remarks 1. PU3: ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P36 and P37 WR PM PM3 PM3n WR PORT Output latch (P3n) Address RD Remarks 1. PM3: Port 3 mode register RD: Port 3 read signal WR: Port 3 write signal ...
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Figure 4-8. Block Diagram of P38 and P39 WR PF PF3H PF3n WR PMC PMC3 PMC3n WR PM PM3 PM3n SDA0, SCL0 output WR PORT Output latch (P3n) Address RD SDA0, SCL0 input Remarks 1. PF3H: Port 3 function register ...
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... Specification is made by the port 4 mode control register (PMC4). N-ch open-drain can be specified in 1-bit units. Specification is made by the port 4 function register (PF4). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 4 (PU4). Port 4 includes the following alternate functions. ...
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Registers (a) Port 4 register (P4) The port 4 register (P4 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. After Reset: Undefined P4 0 ...
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CHAPTER 4 PORT FUNCTIONS (c) Port 4 mode control register (PMC4) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W Address: FFFFF448H PMC4 0 ...
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... Pull-up resistor option register 4 (PU4) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W PU4 0 0 PU4n 0 Not connected 1 Connected 168 CHAPTER 4 PORT FUNCTIONS Address: FFFFFC48H PU42 Control of on-chip pull-up resistor connection ( User’ ...
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Block diagram (port 4) Figure 4-9. Block Diagram of P40 WR PU PU4 PU40 WR PMC PMC4 PMC40 WR PM PM4 PM40 WR PORT Output latch (P40) RD SI00 input Remark PU4: Pull-up resistor option register 4 PM4: Port ...
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WR PU PU4 PU41 WR PF PF4 PF41 WR PMC PMC4 PMC41 WR PM PM4 PM41 WR PORT SO00 output Output latch (P41) Address RD Remark PU4: Pull-up resistor option register 4 PF4: Port 4 function register PM4: Port 4 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P42 WR PU PU4 PU42 WR PF PF4 PF42 WR PMC PMC4 PMC42 WR PM PM4 PM42 WR PORT SCK00 output Output latch (P42) Address SCK00 input RD Remark PU4: Pull-up ...
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... Specification is made by the port 5 function register (PF5). Control mode 1/control mode 2 can be specified in 1-bit units. Specification is made by the port 5 function control register (PFC5). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 5 (PU5). Port 5 includes the following alternate functions. ...
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Registers (a) Port 5 register (P5) The port 5 register (P5 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. After Reset: Undefined P5 0 ...
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Port 5 mode control register (PMC5) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W PMC5 0 PMC55 0 I/O port/KR5 input 1 ...
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CHAPTER 4 PORT FUNCTIONS (d) Port 5 function register 5 (PF5) This is an 8-bit register that specifies normal output/N-ch open-drain output. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W Address: FFFFFC6AH PF5 0 ...
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Port 5 function control register (PFC5) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W PFC5 0 PFC55 0 SCKA0 I/O 1 ...
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... CHAPTER 4 PORT FUNCTIONS (f) Pull-up resistor option register 5 (PU5) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H R/W Address: FFFFFC4AH PU5 0 0 PU5n Control of on-chip pull-up resistor connection ( ...
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Block diagram (port 5) Figure 4-12. Block Diagram of P50, P51, and P53 WR PU PU5 PU5n WR PFC PFC5 PFC5n WR PMC PMC5 PMC5n WR PM PM5 PM5n WR PORT RTP0n output Output latch (P5n) RD Address TI011, ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P52 WR PU PU5 PU52 WR PFC PFC5 PFC52 WR PMC PMC5 PMC52 WR PM PM5 PM52 TO50 output RTP02 output WR PORT Output latch (P52) RD Address Remark PU5: Pull-up ...
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WR PU PU5 PU54 WR PF PF5 PF54 WR PFC PFC5 PFC54 WR PMC PMC5 PMC54 WR PM PM5 PM54 SOA0 output RTP04 output WR PORT Output latch (P54) RD Address Remark PU5: Pull-up resistor option register 5 PF5: Port ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P55 WR PU PU5 PU55 WR PF PF5 PF55 WR PFC PFC5 PFC55 WR PMC PMC5 PMC55 WR PM PM5 PM55 SCKA0 output RTP05 output WR PORT Output latch (P55) RD ...
Page 182
... Specification is made by the port 6 function register (PF6). Control mode 1/control mode 2 can be specified in 1-bit units. Specification is made by the port 6 function control register (PFC6H). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 6 (PU6). Port 6 includes the following alternate functions. ...
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Registers (a) Port 6 register (P6) The port 6 register (P6 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits ...
Page 184
Port 6 mode register (PM6) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PM6 ...
Page 185
Port 6 mode control register (PMC6) This is a 16-bit register that specifies the port mode/control mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the ...
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Port 6 function register (PF6) This is a 16-bit register that specifies normal output/N-ch open-drain output. The PF6 register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the ...
Page 187
... Pull-up resistor option register 6 (PU6) This is a 16-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PU6 register are used as the PU6H register and as the PU6L register, respectively, this register can be read/written in 8-bit or 1-bit units ...
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Block diagram (Port 6) Figure 4-16. Block Diagram of P60 to P65, and P611 WR PU PU6n, PU611 WR PMC PMC6 PMC6n, PMC611 WR PM PM6n, PM611 WR PORT RTP1n, TO04 output Output latch (P6n, P611) RD Remarks 1. ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P66, P69, P610, and P612 WR PU PU6 PU6n WR PMC PMC6 PMC6n WR PM PM6 PM6n WR PORT Output latch (P6n) Address SI02, TI040, TI041, TI050 input RD Remarks 1. ...
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WR PU PU6 PU67 WR PF PF6 PF67 WR PMC PMC6 PMC67 WR PM PM6 PM67 WR PORT SO02 output Output latch (P67) Address RD Remark PU6: Pull-up resistor option register 6 PF6: Port 6 function register PM6: Port 6 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P68 WR PU PU6 PU68 WR PF PF6 PF68 WR PMC PMC6 PMC68 WR PM PM6 PM68 WR PORT SCK02 output Output latch (P68) Address CSI02 input enable signal SCK02 input ...
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WR PU PU6 PU613 WR PFC PFC6 PFC613 WR PMC PMC6 PMC613 WR PM PM6 PM613 WR PORT TO05 output Output latch (P613) Address RD TI051 input Remark PU6: Pull-up resistor option register 6 PFC6: Port 6 function control register ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P614 and P615 WR PM PM6 PM61n WR PORT Output latch (P61n) Address RD Remarks 1. PM6: Port 6 mode register RD: Port 6 read signal WR: Port 6 write signal ...
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Port 7 All the pins of port 7 are fixed to input. The number of input port pins for port 7 differs according to the product. V850ES/KF1 V850ES/KG1 V850ES/KJ1 (1) Port 7 functions Port input data read is possible ...
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Table 4-13. Alternate-Function Pins of Port 7 (V850ES/KJ1) Pin Name Alternate Function Port 7 P70 ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P77 ANI5 P76 ANI6 P77 ANI7 P78 ANI8 P79 ANI9 P710 ANI10 P711 ANI11 P712 ANI12 ...
Page 196
Registers (a) Port 7 register (P7) The port 7 register (P7) of the V850ES/KF1 and V850ES/KG1 is an 8-bit register that reads the pin level. This register can be read in 8-bit units. The port 7 register (P7) of ...
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Block diagram (Port 7) Figure 4-22. Block Diagram of P70 to P715 RD Remark RD: Port 7 read signal CHAPTER 4 PORT FUNCTIONS ANIn input User’s Manual U15862EJ3V0UD P7n/ANIn 197 ...
Page 198
... Specification is made by the port 8 function register (PF8). Control mode 1/control mode 2 can be specified in 1-bit units. Specification is made by the port 8 function control register (PFC8). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 8 (PU8). Port 8 includes the following alternate functions. ...
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Registers (a) Port 8 register (P8) The port 8 register (PM8 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KJ1 After Reset: Undefined ...
Page 200
Port 8 mode control register (PMC8) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KJ1 After Reset: 00H R/W PMC8 0 PMC81 0 I/O port ...