UPD720100AS1-2C NEC, UPD720100AS1-2C Datasheet
UPD720100AS1-2C
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UPD720100AS1-2C Summary of contents
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... FBGA (15 × 15) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. ...
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BLOCK DIAGRAM PME0 INTA0 WakeUp_Event OHCI Host Controller #1 PHY Port 1 Port 2 2 PCI Bus INTB0 PCI Bus Interface WakeUp_Event Arbiter OHCI Host Controller #2 Root Hub Port 3 Port 4 USB Bus Data Sheet S15535EJ2V0DS µ µ ...
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... Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4. EHCI Host Controller :handles high- (480 Mbps) signaling at port and 5. Root Hub :handles USB hub function in Host controller and controls connection (routing) between Host controller core and port. PHY :consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, ...
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PIN CONFIGURATION • 160-pin plastic LQFP (Fine pitch) (24 × × × × 24) µ PD720100AGM-8ED µ PD720100AGM-8EY NTEST1 NTEST2 TEST XT1/SCLK 5 XT2 LEGC VCCRST0 SMI0 IRI1 IRI2 IRO1 15 IRO2 ...
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... AD27 74 35 AD26 75 36 AD25 76 37 AD24 77 38 CBE30 78 39 IDSEL Remark AV (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. SS Pin Name Pin No. Pin Name AD5 SS AD23 83 AD4 SMC 84 AD3 SIN/TIN 85 AD2 SOT/TOUT ...
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FBGA (15 × × × × 15) µ PD720100AS1- 141 142 143 144 28 87 140 27 86 139 26 85 138 25 84 ...
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... RSDM3 85 42 RSDP3 86 43 N.C.( RSDP4 88 Remarks 1. Pin 43 can be opened. But this signal is connected to pin 45 in the package. Should not be connected to GND (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. SS Pin Name Pin No. Pin Name V 89 SELCLK DD NTEST1 ...
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PIN INFORMATION Pin Name I/O Buffer Type PCI I/O CBE (3 : 0)0 I PCI I/O PAR I PCI I/O FRAME0 I PCI I/O IRDY0 I/O ...
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... NAND Tree Test enable Test signal Test signal Serial ROM Clock Out Serial ROM Data High Serial ROM Input Enable V for Analog circuit PCI) or 3.3 V (3.3 V PCI) V for Analog circuit Not connect Data Sheet S15535EJ2V0DS µ µ µ µ PD720100A (2/2) Function 9 ...
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... USB interface DP(1:5), DM(1:5), RSDP(1:5), RSDM(1:5), PC1, PC2, RREF, SELDAT, SELCLK Above, “5 V” refers to a 3-V buffer with 5-V tolerant circuit. Therefore possible to have a 5-V connection for an external bus, but the output level will be only which is the V PCI buffer that has a 5-V tolerant circuit, which meets the 3-V PCI standard; it does not refer to a PCI buffer that meets the 5-V PCI standard ...
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Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Power supply voltage V DD Input voltage V I Output voltage V O Operating temperature T A Storage temperature T stg Terms Used in Recommended Operating Range Parameter Symbol Power ...
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Electrical Specifications Absolute Maximum Ratings Parameter Symbol Power supply voltage V DD Input voltage buffer V I Input voltage, 3.3 V buffer V I Output voltage buffer V O Output voltage, 3.3 V buffer V ...
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DC Characteristics (V = 3 Control Pin Block Parameter Off-state output current Output short circuit current Low-level output current 3.3 V Low-level output current 3.3 V Low-level output current 5.0 V Low-level output current 5.0 ...
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... Low-level output voltage SE1 Output signal crossover point voltage Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling level Output Levels for High-speed: ...
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Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range -1.0 0.0 0.2 0.4 0.6 0.8 1.0 Input Voltage Range (Volts) Figure 2-2. Full-speed Buffer -3.3 V -2 Min. Max. ...
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... Figure 2-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 Level Figure 2-5. Receiver Measurement Fixtures USB Vbus Connector D+ Nearest D- Device Gnd 143 Ω Pin Capacitance Parameter Input capacitance Output capacitance I/O capacitance PCI input pin capacitance PCI clock input pin capacitance PCI IDSEL input pin capacitance ...
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... Device state = D3 WD3C Oscillator output is stopped. Notes 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend on the number of active ports. 2. The number of active ports is set by the value of Port No field in PCI configuration space EXT register. ...
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System Clock Ratings Parameter Clock frequency Clock Duty cycle Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or Oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply ...
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AC Characteristics (V = 3 PCI Interface Block Parameter PCI clock cycle time PCI clock pulse, high-level width PCI clock pulse, low-level width PCI clock, rise slew rate PCI clock, fall slew rate PCI reset ...
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USB Interface Block Parameter Low Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Differential Rise and Fall Time matching Low-speed Data Rate Source Jitter Total (including frequency tolerance): To Next Transition For Paired Transitions Source ...
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... Consecutive Microframe Interval Difference Data source jitter Receiver jitter tolerance Hub event Timings Time to detect a downstream facing port connect event Time to detect a disconnect event at a downstream facing port: Duration of driving resume to a downstream port Time from detecting downstream resume to rebroadcast. Inter-packet Delay for packets traveling in ...
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... Figure 2-6. Transmit Waveform for Transceiver at DP/DM Level 1 Point 1 Level 2 0% Figure 2-7. Transmitter Measurement Fixtures USB Vbus Connector D+ Nearest D- Device Gnd 143 Ω 22 Point 3 Point 4 Point 2 Point 5 Point 6 Unit Interval 100% Test Supply Voltage 15.8 Ω 50 Ω Coax 15.8 Ω 50 Ω Coax 143 Ω Data Sheet S15535EJ2V0DS µ ...
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Timing Diagram PCI Clock 0.6V DD 0.5V DD 0.4V DD 0.3V DD 0.2V DD PCI Reset PCLK PWR_GOOD VBBRST0 PCI Signals PCI Output Timing Measurement Condition PCLK output delay output t cyc t t high low 100 ms (typ.) t ...
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PCI Input Timing Measurement Condition PCLK input USB Differential Data Jitter for Low-/full-speed t PERIOD Differential Data Lines USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed t PERIOD Crossover Point Differential Data Lines Diff. Data-to- ...
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... USB Receiver Jitter Tolerance for Low-/full-speed t PERIOD Differential Data Lines Low-/full-speed Disconnect Detection D+/D- V IZH (min D-/ Device Disconnected Full-/high-speed Device Connect Detection Device Connected UJR JR1 UJR1 Consecutive Transitions N × PERIOD JR1 ...
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... Low-speed Device Connect Detection Device Connected DCNN Connect Detected Data Sheet S15535EJ2V0DS µ µ µ µ PD720100A ...
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PACKAGE DRAWING 160-PIN PLASTIC LQFP (FINE PITCH) (24x24 120 121 160 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC LQFP (FINE PITCH) (24x24) 120 121 160 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC FBGA (15x15 Index mark φ ...
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... For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. µ µ µ µ PD720100AGM-8ED: 160-pin plastic LQFP (Fine pitch) (24 × × × × 24) µ ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • ...