CY7C1049B-17VI Cypress Semiconductor Corporation., CY7C1049B-17VI Datasheet

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CY7C1049B-17VI

Manufacturer Part Number
CY7C1049B-17VI
Description
CY7C1049B-17VI512K x 8 Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05169 Rev. *A
Features
Functional Description
The CY7C1049B is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Selection Guide
Note:
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
1.
• High speed
• Low active power
• Low CMOS standby power (Commercial L version)
• 2.0V Data Retention (400 W at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
CE
WE
OE
Logic Block Diagram
— t
— 1320 mW (max.)
— 2.75 mW (max.)
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
A
A
A
A
A
A
A
A
A
A
10
0
1
2
3
4
5
6
7
8
9
AA
= 12 ns
INPUT BUFFER
DECODER
COLUMN
512K x 8
ARRAY
[1]
Com’l
Com’l/Ind’l L
Ind’l
POWER
DOWN
3901 North First Street
7C1049B-12 7C1049B-15 7C1049B-17 7C1049B-20
240
12
8
-
-
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O
through I/O
address pins (A
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049B is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
220
15
8
-
-
7
San Jose
) is then written into the location specified on the
0
through A
512K x 8 Static RAM
Pin Configuration
195
0.5
17
8
-
GND
I/O3
I/O
I/O
V
I/O
WE
CE
CC
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
0
1
2
5
6
7
8
9
18
CA 95134
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
).
0
Revised September 13, 2002
SOJ
through I/O
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
185
0.5
20
8
9
CY7C1049B
NC
A
A
A
A
OE
I/O
I/O
GND
V
I/O
I/O
A
A
A
A
A
NC
18
17
16
15
CC
14
13
12
11
10
7
6
5
4
7
) are placed in a
408-943-2600
7C1049B-25
180
0.5
25
8
9
0

Related parts for CY7C1049B-17VI

CY7C1049B-17VI Summary of contents

Page 1

... Data Retention (400 W at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features [1] Functional Description The CY7C1049B is a high-performance CMOS static RAM or- ganized as 524,288 words by 8 bits. Easy memory expansion Logic Block Diagram INPUT BUFFER A 0 ...

Page 2

... MAX Max Com’ > V – 0.3V, CC Com’ > V – 0.3V < 0.3V Ind’l IN Ind’l L CY7C1049B Ambient Temperature +70 C 4.5V–5.5V – +85 C 7C1049B-15 7C1049B-17 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0.4 V 2 ...

Page 3

... IN CC Ind’ < 0.3V Ind’l L Test Conditions MHz 5. 481 5V R2 GND 5 pF 255 INCLUDING JIG AND SCOPE (b) 1.73V CY7C1049B 7C1049B-20 7C1049B-25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 0.3 2 –0.3 0.8 –0.3 0.8 –1 +1 –1 –1 +1 –1 ...

Page 4

... Document #: 38-05169 Rev. *A Over the Operating Range 7C1049B-12 Min. Max. [ less than less than t HZCE LZCE HZOE LZOE CY7C1049B 7C1049B-15 7C1049B-17 Min. Max. Min ...

Page 5

... No input may exceed V + 0.5V. CC Document #: 38-05169 Rev. *A Over the Operating Range (continued) Description [5] Over the Operating Range Com’ > V Ind’ CY7C1049B 7C1049B-20 7C1049B-25 Min. Max. Min. Max ...

Page 6

... WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05169 Rev. *A DATA RETENTION MODE 3.0V V > CDR OHA ACE t DOE t LZOE 50 CY7C1049B 3. DATA VALID t HZOE t HZCE IMPEDANCE DATA VALID t PD 50% HIGH Page ...

Page 7

... During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05169 Rev SCE SCE PWE t SD DATA VALID [15, 16 SCE PWE t SD DATA VALID IN CY7C1049B Page ...

Page 8

... Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 17 DATA I/O Ordering Information Speed (ns) Ordering Code 12 CY7C1049B-12VC 15 CY7C1049B-15VC CY7C1049B-15VI 17 CY7C1049B-17VC CY7C1049BL-17VC CY7C1049B-17VI 20 CY7C1049B-20VC CY7C1049BL-20VC CY7C1049B-20VI CY7C1049BL-20VI 25 CY7C1049B-25VC CY7C1049BL-25VC CY7C1049B-25VI CY7C1049BL-25VI Document #: 38-05169 Rev. *A [16 SCE PWE t HZWE ...

Page 9

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 36-Lead (400-Mil) Molded SOJ V36 CY7C1049B 51-85090-*B Page ...

Page 10

... Document History Page Document Title: CY7C1049B 512K x 8 Static RAM Document Number: 38-05169 Issue REV. ECN NO. Date ** 110209 12/02/01 *A 116465 09/16/02 Document #: 38-05169 Rev. *A Orig. of Change SZV Change from Spec number: 38-00937 to 38-05169 CEA Add applications foot note to data sheet, page 1. CY7C1049B Description of Change ...

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