UPD29F064115F9-EB90X-CD5 NEC, UPD29F064115F9-EB90X-CD5 Datasheet

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UPD29F064115F9-EB90X-CD5

Manufacturer Part Number
UPD29F064115F9-EB90X-CD5
Description
UPD29F064115F9-EB90X-CD564M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY 4M-WORD BY 16-BIT (WORD MODE) PAGE MODE
Manufacturer
NEC

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Document No. M16062EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
Description
be erased at a low voltage (1.65 to 1.95 V, 1.8 to 2.1 V ) supplied from a power source, or the contents of the entire
chip can be erased. Memory organization is 4,194,304 words × 16 bits, so that the memory can be programmed in
word units. µ PD29F064115-X can be read high speed with page mode.
into four banks. While sectors in any bank are being erased or programmed, data can be read from the other three
banks thanks to the simultaneous execution architecture. The banks are 8M bits, 24M bits, 24M bits and 8M bits.
addition, program code that controls the flash memory can be also stored, and the program code can be programmed
or erased without the need to load it into RAM. 16 small sectors for storing parameters are provided, each of which
can be erased in 4K words units.
function internally executes program or erase and verification automatically. The programming time is about 0.5
seconds per sector. The erase time is less than 1 second per sector.
reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of
applications.
Features
• Four bank organization enabling simultaneous execution of program / erase and read
• High-speed read with page mode
• Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
• Memory organization : 4,194,304 words × 16 bits
• Sector organization : 142 sectors (4K words × 16 sectors, 32K words × 126 sectors)
• 3-state output
• Automatic program
• Unlock bypass program
• Automatic erase
• Program / Erase completion detection
The µ PD29F064115-X is a flash memory organized of 67,108,864 bits and 142 sectors. Sectors of this memory can
The µ PD29F064115-X can be read while its contents are being erased or programmed. The memory cell is divided
Input /output voltage is supplied to 2.7 to 3.3 V.
Because the µ PD29F064115-X enables the boot sector to be erased, it is ideal for storing a boot program. In
Once a program or erase command sequence has been executed, an automatic program or automatic erase
Because the µ PD29F064115-X can be electrically erased or programmed by writing an instruction, data can be
This flash memory is packed in 48-pin PLASTIC TSOP (I), 63-pin TAPE FBGA and 85-pin TAPE FBGA.
The boot sector is located at the highest address (sector) and the lowest address (sector)
• Program suspend / resume
• Chip erase
• Sector erase (sectors can be combined freely)
• Erase suspend / resume
• Detection through data polling and toggle bits
• Detection through RY (/BY) pin
64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
4M-WORD BY 16-BIT (WORD MODE)
The mark # # # # shows major revised points.
DATA SHEET
PAGE MODE
µ µ µ µ PD29F064115-X
MOS INTEGRATED CIRCUIT
©
2002

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UPD29F064115F9-EB90X-CD5 Summary of contents

Page 1

... Detection through RY (/BY) pin The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M16062EJ2V0DS00 (2nd edition) ...

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Sector group protection • Any sector group can be protected • Any protected sector group can be temporary unprotected • Any sector group can be unprotected • Sectors can be used for boot application • Hardware reset and standby ...

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Pin Configurations /xxx indicates active low signal. 48-pin PLASTIC TSOP (I) (12 × × × × 20) (Normal bent) A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 9 A20 10 /WE ...

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... Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the index mark. 4 63-pin TAPE FBGA (11 × × × × µ µ µ µ PD29F064115F9-DB80X-CD6 ] [ µ µ µ µ PD29F064115F9-DB85X-CD6 ] [ µ ...

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... Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the index mark. INPUT / OUTPUT PIN FUNCTION Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E). 85-pin TAPE FBGA (11 × × × × µ ...

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Block Diagram V CC Bank C address GND Bank A address Address A0 to A21 buffers Bank / Sector decoder /WP(ACC) Program / Erase voltage generator State /RESET control (Command /WE register) /CE /OE RY(/BY) Bank B ...

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Sector Organization / Sector Address Table Bank Sector Address Organization K words Bank D 4 3FFFFFH 3FF000H 4 3FEFFFH 3FE000H 4 3FDFFFH 3FD000H 4 3FCFFFH 3FC000H 4 3FBFFFH 3FB000H 4 3FAFFFH 3FA000H 4 3F9FFFH 3F9000H 4 3F8FFFH 3F8000H 32 3F7FFFH ...

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Sector Organization / Sector Address Table Bank Sector Address Organization K words Bank C 32 317FFFH 310000H 32 30FFFFH 308000H 32 307FFFH 300000H 32 2FFFFFH 2F8000H 32 2F7FFFH 2F0000H 32 2EFFFFH 2E8000H 32 2E7FFFH 2E0000H 32 2DFFFFH 2D8000H 32 2D7FFFH ...

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Sector Organization / Sector Address Table Bank Sector Address Organization K words Bank B 32 1FFFFFH 1F8000H 32 1F7FFFH 1F0000H 32 1EFFFFH 1E8000H 32 1E7FFFH 1E0000H 32 1DFFFFH 1D8000H 32 1D7FFFH 1D0000H 32 1CFFFFH 1C8000H 32 1C7FFFH 1C0000H 32 1BFFFFH ...

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Sector Organization / Sector Address Table Bank Sector Address Organization K words Bank B 32 0DFFFFH 0D8000H 32 0D7FFFH 0D0000H 32 0CFFFFH 0C8000H 32 0C7FFFH 0C0000H 32 0BFFFFH 0B8000H 32 0B7FFFH 0B0000H 32 0AFFFFH 0A8000H 32 0A7FFFH 0A0000H 32 09FFFFH ...

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Sector Group Address Table Sector group A21 A20 A19 A18 SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 ...

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Sector Group Address Table Sector group A21 A20 A19 A18 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 ...

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Product ID Code (Manufacturer Code / Device Code) Product ID Code I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Manufacturer Code Device code Sector group protection ...

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Command Sequence Command sequence Bus 1st bus Cycle Cycle Address Note1 Read / Reset ×××H 1 Note1 Read / Reset 3 555H Program 4 555H Note 2 Program Suspend 1 Note 3 Program Resume 1 Chip Erase 6 555H Sector ...

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Notes 1. Both these read / reset commands reset the device to the read mode. 2. Programming is suspended if B0H is input to the bank address being programmed program operation. 3. Programming is resumed if 30H ...

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SPA : Sector group address to be protected or protection-verified. Set the sector group address (SGA) and (A6, A3, A2, A1, A0 Sector group protection can be set for each sector group address. For details, refer to PAGE ...

Page 17

Electrical Characteristics Before turning on power, input GND ± 0 the /RESET pin until V Absolute Maximum Ratings Parameter Symbol Supply voltage V with respect to GND CC Input / Output V Q with respect to GND CC ...

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DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol High level output voltage V OH1 V OH2 Low level output voltage V OL Input leakage current I LI1 High voltage is applied I LI2 I/O leakage current I LO ...

Page 19

DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol High level output voltage V OH1 V OH2 Low level output voltage V OL Input leakage current I LI1 High voltage is applied I LI2 I/O leakage current I LO ...

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AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time ≤ ≤ ≤ ≤ Output Waveform Output Load 1 TTL + ...

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Read Cycle Parameter Symbol Read cycle time Address access time Page read cycle time Page address access time /CE access time /OE access time Output disable time Output hold time /RESET pulse width /RESET hold time before read /RESET low ...

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Write Cycle (Program / Erase) Parameter Write cycle time Address setup time (/WE to address) Address setup time (/CE to address) Address hold time (/WE to address) Address hold time (/CE to address) Input data setup time Input data hold ...

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Write Cycle (Program / Erase) Parameter From completion of automatic program / erase to data output time RY (/BY) delay time from valid program or erase operation Address setup time to /OE low in toggle bit Address hold time to ...

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Package Drawings 48-PIN PLASTIC TSOP (I) (12x20 NOTES 1) Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2) "A" excludes mold flash. (Includes mold flash : ...

Page 25

TAPE FBGA (11x8) E INDEX MARK φ φ Data Sheet M16062EJ2V0DS µ µ µ µ PD29F064115-X ...

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TAPE FBGA (11x8) E INDEX MARK φ φ ...

Page 27

Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µ PD29F064115-X. Types of Surface Mount Device µ PD29F064115GZ-MJH : 48-pin PLASTIC TSOP(I) (12 × 20) (Normal bent) µ PD29F064115F9-CD6 : 63-pin TAPE FBGA (11 × ...

Page 28

Revision History Edition/ Page Date This Previous edition edition − 2nd edition/ Throughout Modification Sep.2002 p.16 p.14 p.21 p.19 Addition 28 Type of Location revision − Preliminary Data Sheet → Data Sheet Command Sequence Remark 2 : SPA, SUA Read ...

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MEMO ] Data Sheet M16062EJ2V0DS µ µ µ µ PD29F064115-X 29 ...

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MEMO ] 30 Data Sheet M16062EJ2V0DS µ µ µ µ PD29F064115-X ...

Page 31

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • ...

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