UPD72001GC-11-3B6 NEC, UPD72001GC-11-3B6 Datasheet
UPD72001GC-11-3B6
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UPD72001GC-11-3B6 Summary of contents
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MULTI-PROTOCOL SERIAL CONTROLLERS DESCRIPTION The PD72001- MPSC (Multi-Protocol Serial Controller) which is a general-purpose communication LSI equipped with two sets of bidirectional parallel/serial converter circuits for data communication. This controller has a transmitter function to convert the parallel ...
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ORDERING INFORMATION Part Number PD72001C-11 PD72001G-11-22 PD72001GC-11-3B6 PD72001L-11 PD72001C-A8 PD72001G-A8-22 PD72001GC-A8-3B6 2 Package 40-pin plastic DIP (600 mil) 44-pin plastic QFP (10 10 mm) (resin thickness: 1.45 mm) 52-pin plastic QFP (14 14 mm) (resin thickness: 2.7 mm) 52-pin plastic ...
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SPECIFICATIONS Item Part number Supply voltage System clock frequency 11 MHz MAX. Maximum transfer rate 2.2 Mbps Process CMOS Internal circuit Parallel/serial converter circuit: Full-duplex channel Transmit buffer : Double Receive buffer : Quadruple Interrupt control ...
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... DCDB • 44-pin plastic QFP (10 10 mm) : RTSB DTRB/DRQR B X DTRA/DRQT B X DRQT CLK RESET DRQR A X RTSA IC: Internally Connected (Leave this pin unconnected CTSA XI1A/STR XI2A/SYNCA ...
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... CTSA DCDA Connection IC : Internally Connected (Leave this pin unconnected.) • 52-pin plastic QFJ (750 750 mil GND 13 GND ...
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System CLK CLK/Stby CLK Cont. DB D7-0 Buf 0-5 WR 10-15 RD/WR C/D Cont. B/A RESET DRQR A X DMA DRQT A X DTRB/DRQR B Cont. X DTRA/DRQT B X INT INT INTAK PRI Cont. PRO Interface Cont. ...
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PIN FUNCTIONS The functions of the MPSC can be broadly classified into “system interface functions” that control interfacing with the host system, and “transmission/reception functions” to transmit or receive data. This section explains the functions of the pins of ...
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Pin Name I B I/O INT O INTAK I PRI I PRO O DRQT DRQR DTRA/DRQT DTRB/DRQR DA, ...
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... L Setting prohibited (9) D7 through D0 (Data Bus) ... I/O These pins constitute a three-state 8-bit bidirectional data bus. This data bus is connected to the data bus of the host processor to transfer control words, status, and transmit/receive data. (10) INT (Interrupt) ... Output (open drain) This pin outputs an interrupt request signal interrupt occurs in the MPSC, it goes low (active). Because this is an open-drain output pin, it must be pulled up ...
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Non-vector mode (CR2A “0”) In this mode, the PRI pin controls only the generation of interrupts because the INTAK sequence is not used interrupt vector output mode other than Type A-3 and Type B-2 is ...
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When CR2A: D1 “0, 0” or “0, 1” This pin functions as the DTRB output pin. The function of this pin is the same as the DTRA pin, except this pin is used with channel B. (b) ...
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... When CR15 These pins function as SYNC pins. The functions of the SYNC pins differ as shown in Table 1-6, depending on the setting of CR4. (b) When CR15 “1” These pins function as XI2 pins and connect one end of the crystal for transmission/reception clock source oscillation. 12 RTS Cont. Bit ...
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Table 1-6. Functions of SYNC Pins and Setting of CR4 (when CR15 “0”) Operation Synchronization SYNC Pin Protocol Detection Mode Function D7 Start-stop Input synchro- nization COP Internal Output synchro- nization External Input 0 synchro- nization 0 BOP ...
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RS-232-C D/R Personal computer Terminal adapter for ISDN PD72001-11 PD98201 HDLC Dch SYNC ASYNC S-I/F Trans- former HDLC Bch SYNC ASYNC Bus PD72002-11 HDLC CPU ROM SYNC (with DMAC) ASYNC ISDN circuit RAM ...
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... Low-level output leakage current I LOL Supply current I DD Note System clock : 11 MHz Input pin : Inactive • High-level input voltage : (V • Low-level input voltage : 0.3 V Output pin : Leave unconnected. PD72001-11, 72001-A8 Condition = Condition CLK, STR Other pins CLK, STR ...
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Capacitance ( Parameter Symbol Input capacitance I/O capacitance AC Characteristics PD72001- – System interface: Parameter Symbol Clock cycle Clock high-pulse width Clock low-pulse ...
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... PRI hold time (vs. INTAK ) t PRI setup time (vs. INTAK ) t PRI hold time (vs. INTAK ) t INTAK data output delay time t INTAK data float delay time Note Measured value with 2-k pull-up resistor and 100-pF load capacitance connected PD72001-11, 72001-A8 Condition t CYD t CYC WCH –10 to +70 C WCL ...
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Modem control: Parameter Symbol CTS, DCD, SYNC pulse High t width Low CTS, DCD, SYNC INT delay time t STR SYNC setup time Communication control: Parameter Symbol Transmit enable command t DTETD1 (WR , ...
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AC Test Input/Output Waveform (except clock) 2.4 0.45 AC Test Clock Input Waveform Load Condition Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load capacitance of this device to within 100 ...
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... Low-level output leakage I LOL current Supply current I DD Note System clock : 8 MHz (T Input pin : Inactive • High-level input voltage : (V • Low-level input voltage : 0.3 V Output pin : Leave unconnected. Capacitance ( Parameter Symbol Input capacitance I/O capacitance 20 Condition = 3.3 V 0.3 V) ...
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AC Characteristics (T = – System interface: Parameter Symbol Clock cycle Clock high-pulse width t Clock low-pulse width Clock rise time Clock fall time Address setup time (vs Address hold time (vs. RD ...
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Serial control: Parameter Symbol Transmit/receive data cycle STR input clock cycle X X STR input X X clock pulse width STR delay time DTCTD1 t DTCTD2 TR C ...
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... PRI setup time (vs. INTAK ) t PRI hold time (vs. INTAK ) t INTAK data output delay time t INTAK data float delay time Note Measured value with 2-k pull-up resistor and 100-pF load capacitance connected Modem control: Parameter Symbol CTS, DCD, SYNC High t pulse width Low t CTS, DCD, SYNC ...
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Communication control: Parameter Symbol Transmit enable command ( DTETD1 CTS ) T D delay time X t DTETD2 Receive enable command (DCD ) t SRERC setup time (vs. start bit, STR Note ...
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AC Test Input Waveform (except clock) 2.2 0.5 AC Test Clock Input Waveform Load Condition Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load capacitance of this device to within 100 ...
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Clock Timing CLK Read Cycle Timing C/D, B/A RD D7-0 Write Cycle Timing C/D, B/A WR D7-0 Read/Write Cycle Timing (except transfer of transmit/receive data) RD CYK t t WKH WKL SAR ...
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Transmit Cycle Timing STR CA CA DTCTD3 T DA/B X INT DRQT A/B X Receive Cycle Timing STR CA CA DA/B X INT DRQR A/B X PD72001-11, 72001-A8 t CYC t WCL ...
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Transmitter Enable Timing CTS Receiver Enable Timing STR DCD Note LSB of the first receive data (SYNC, flag) Receive Clock Setting Timing a. In ASYNC mode STR C ...
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DCD Timing, Receive Clock Hold Timing a. In ASYNC mode STR DCD b. COP/BOP mode STR Note X DCD Note This bit is the MSB ...
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DMA Cycle Timing DRQT A/B X DRQR A PRO Output Timing PRI INT t DPIPO PRO INTAK Cycle Timing PRI (when vector output is disabled) PRI (when vector output is enabled) INTAK t WIAL RD Hi-Z D7-0 ...
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E/S Timing CTSA/B, DCDA/B, SYNCA/B INT SYNC Input Timing (external synchronization mode) STR CA CA/B X Last Bit of SYNC Character Note SYNCA/B Note SYNCA/B input must be cleared to “0” at the rising edge of R character. ...
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PACKAGE 40PIN PLASTIC DIP (600 mil NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to ...
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PIN PLASTIC QFP ( 10 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. PD72001-11, 72001-A8 23 ...
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PIN PLASTIC QFP ( 14 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition detail of lead ...
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PIN PLASTIC QFJ ( 750 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. PD72001-11, 72001- ...
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... Solder bath temperature: 260 C MAX., Time: 10 seconds MAX., Number of times: 1, Preheating temperature: 120 C MAX. (package surface temperature), Number of days: 7 (After that, prebaking for 10 hours at 125 C is necessary.) <Precaution> Products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package ...
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PD72001GC-11-3B6 : 52-pin plastic QFP (14 PD72001GC-A8-3B6: 52-pin plastic QFP (14 Soldering Method Infrared reflow Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.), Number of times: 3 MAX. VPS Package peak temperature: 215 C, Time: ...
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PD72001-11, 72001-A8 ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...