W238 Cypress Semiconductor Corporation., W238 Datasheet
W238
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W238 Summary of contents
Page 1
... VDDQ3 USB Note: 1. Internal pull-down resistors present on input marked with *. DOT Design should not solely rely on internal pull-down resister to set I/O pin LOW. • 3901 North First Street • San Jose W238 FSEL0 Function SRAM 0 Three-state Three-state 1 Test Test 0 66 MHz 100 MHz ...
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... trademark of Phillips Corporation. Intel is a registered trademark of Intel Corporation. PRELIMINARY 2 W238 ...
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... Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con- nect to 2.5V or 3.3V. Ground Connections: Ground for core logic, PLL circuitry. Ground Connections: Connect all ground pins to the common system ground plane. 3 W238 . DDQ2 . DDQ2 ...
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... Output Three-state Reset Timer Figure 1. Input Logic Selection Through Resistor Load Option Overview The W238 is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architec- ture platform using graphics integrated core logic. Functional Description I/O Pin Operation REF/SEL1 is a dual-purpose l/O pin ...
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... Offsets Among Clock Signal Groups Figure 2 and Figure 3 represent the phase relationship among the different groups of clock outputs from W238 when it is pro- viding a 66-MHz CPU clock and a 100-MHz CPU clock, re- Figure 2. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM CPU 100 Period ...
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... Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM CPU 100-MHz SDRAM 133-MHz 3V66 66-MHz PCI 33-MHz APIC 33-MHz REF 14.318-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM) PRELIMINARY 20 ns Cycle Repeats Cycle Repeat 6 W238 ...
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... Power Down Control W238 provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW. Figure 6. W238 PWRDWN# Timing Diagram Table 3. W238 Maximum Allowed Current W238 Condition Powerdown Mode ...
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... Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by se- lecting the appropriate value for bit 3 in data byte 0 of the I data stream. Refer to page 10 for more details. Figure 8. Typical Modulation Profile 8 W238 2 C ...
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... Figure 9. An Example of a Block Write fer a maximum of 32 data bytes. The slave receiver address for W238 is 11010010. Figure 9 shows an example of a block write. The command code and the byte count bytes are required as the first two bytes of any transfer. W238 expects a command code of 0000 0000 ...
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... W238 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits Byte 1 - Bits Byte N - Bits Byte 0: Control Register (1 = Enable Disable) Bit Pin# Bit 7 ...
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... Reserved Reserved 0 Reserved Reserved 0 Reserved Name Default Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved 11 W238 Pin Description Reserved Reserved Reserved Reserved Reserved Reserved 1 = PWRDWN TRISTATE# (Disabled/Enabled) Pin Function Pin Description Pin Description ...
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... Condition 3.3V±5% 3.3V±5% 2.5V±5% V DD3 [16] 0<V <V in DD3 I =(–1 mA =(1 mA =(–1 mA =(1 mA =(–1 mA =(1 mA Airflow 12 W238 Min. Max. Unit –0.5 4.6 V –0.5 3.6 V –0.5 4.6 V –65 150 °C Min. Max. Unit –0.5 4.6 V –0.5 V 2000 V Min. Max. Unit 3.135 3.465 V 3 ...
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... Host 100-MHz Host Min. Max. Min. 15.0 15.5 10.0 5.2 N/A 3.0 5.0 N/A 2.8 0.4 1.6 0.4 0.4 1.6 0.4 10.0 10.5 10.0 3.0 N/A 3.0 2.8 N/A 2.8 0.4 1.6 0.4 0.4 1.6 0.4 30.0 N/A 30.0 12.0 N/A 12.0 12.0 N/A 12.0 0.4 1.6 0.4 0.4 1.6 0.4 15.0 16.0 15.0 5.25 N/A 5.25 5.05 N/A 5.05 0.5 2.0 0.5 0.5 2.0 0.5 30.0 N/A 30.0 12.0 N/A 12.0 12.0 N/A 12.0 0.5 2.0 0.5 0.5 2.0 0.5 1.0 10.0 1.0 1.0 10.0 1.0 3 achieves its nominal operating level (typical condition V = 0.4V and V = 2.0V (1 mA) JEDEC specification W238 133-MHz Host Max. Min. Max. Unit 10.5 7.5 8 N/A 1.87 N N/A 1.67 N 1.6 0.4 1.6 ns 1.6 0.4 1.6 ns 10.5 10.0 10 N/A 3.0 N N/A 2.8 N 1.6 0.4 1.6 ns 1.6 0.4 1.6 ns N/A 30.0 N N/A 12.0 N N/A 12.0 N 1.6 0.4 1.6 ns 1.6 0.4 1.6 ns 16.0 15.0 16.0 ns 17, 19 N/A 5.25 N N/A 5.05 N 2.0 0.5 2 ...
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... Output Test Point Buffer Test Load T PERIOD Duty Cycle T HIGH T LOW T FALL T PERIOD Duty Cycle T HIGH T LOW T T RISE FALL Figure 10. Output Buffer Package Type 56-pin SSOP (300 mils) W238 Skew, Jitter Nom Vdd Measure Point 2.5V 1.25V 3.3V 1.5V 2.5V 1.25V 3.3V 1.5V 3.3V 1.5V 3.3V 1.5V 3.3V 1.5V ...
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... Package Diagram 56-Pin Shrink Small Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 PRELIMINARY 15 W238 ...