CY7C4231V-25JC Cypress Semiconductor Corporation., CY7C4231V-25JC Datasheet
CY7C4231V-25JC
Related parts for CY7C4231V-25JC
CY7C4231V-25JC Summary of contents
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... High-speed, low-power, first-in, first-out (FIFO) memories • (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • (CY7C4221V) • (CY7C4231V) • (CY7C4241V) • (CY7C4251V) • High-speed 66-MHz operation (15-ns read/write cycle time) • Low power ( mA) CC • ...
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... When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro- grammed into the FIFO. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. 2 CY7C4231V/4241V/4251V CY7C42X1V-25 CY7C42X1V- CY7C4231V CY7C4241V CY7C4251V ...
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... 2.0 5.0 0.5 0 Max > + < V < Com’l 20 Com’l 6 Test Conditions MHz 5. CY7C4231V/4241V/4251V 0.5V to +5.0V Ambient Temperature +70 C 3.3V 300mV 7C42X1V-25 7C42X1V-35 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2.0 5.0 2.0 5.0 V 0.5 0.8 0.5 0 +10 10 +10 10 +10 ...
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... R2=510 GND 3 ns 42X1V–4 Vth=2.0V 7C42X1V-15 Min. Max CY7C4231V/4241V/4251V ALL INPUT PULSES 90% 90% 10% 10 42X1V–5 7C42X1V-25 7C42X1V-35 Min. Max. Min. Max ...
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... REF t A VALID DATA t OE [9] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW1 5 CY7C4231V/4241V/4251V NO OPERATION NO OPERATION t WFF 42X1V–6 t REF t OHZ 42X1V–7 ...
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... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. CY7C4421V/4201V/4211V/4221V RSR RSS t t RSR RSS t t RSR RSS t RSF t RSF t RSF 6 CY7C4231V/4241V/4251V [11 OE=0 42X1V–8 ...
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... The first word is available the cycle after EF goes HIGH, always. CY7C4421V/4201V/4211V/4221V [13] t FRL t REF [14 OLZ When t < minimum specification, t CLK SKEW1 SKEW1 7 CY7C4231V/4241V/4251V 42X1V–9 (maximum) = either 2 FRL CLK SKEW1 CLK SKEW1 . ...
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... ENH ENS WEN1 t t ENS ENH WEN2 (if applicable) t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – CY7C4421V/4201V/4211V/4221V ENS t ENS [13 REF REF CY7C4231V/4241V/4251V DATAWRITE2 t ENH t ENH [13] t FRL t t REF SKEW1 DATA READ 42X1V–10 ...
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... SKEW1 DATA WRITE t WFF ENH A DATA READ t CLKL t t ENS ENH t t Note 16 ENS ENH [15] t PAE t ENS 9 CY7C4231V/4241V/4251V NO WRITE [8] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ 42X1V– WORDS Note 17 INFIFO t PAE t t ENS ENH 42X1V–12 ...
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... PAF offset = m. 20. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V. 21 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK ...
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... WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register con- tents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers. 11 CY7C4231V/4241V/4251V PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB 42X1V– ...
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... PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4421V (64 (256 m), CY7C4211V (512 – m), CY7C4221V (1K CY7C4231V (2K CY7C4251V (8K transition of WCLK when the number of available memory lo- cations is greater than m. 12 CY7C4231V/4241V/4251V ...
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... WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regard- less of the state of REN1 and REN2 synchronized to RCLK, i.e exclusively updated by each rising edge of RCLK. 13 CY7C4231V/4241V/4251V FF PAF PAE ...
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... A32 32-Lead Thin Quad Flatpack J65 32-Lead Plastic Leaded Chip Carrier A32 32-Lead Thin Quad Flatpack J65 32-Lead Plastic Leaded Chip Carrier 14 CY7C4231V/4241V/4251V READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG (EF EMPTY FLAG (EF) #2 DATA OUT (Q) ...
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... CY7C4221V-15AC CY7C4221V-15JC 25 CY7C4221V-25AC CY7C4221V-25JC 35 CY7C4221V-35AC CY7C4221V-35JC Low Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4231V-15AC CY7C4231V-15JC 25 CY7C4231V-25AC CY7C4231V-25JC 35 CY7C4231V-35AC CY7C4231V-35JC Low Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4241V-15AC CY7C4241V-15JC 25 CY7C4241V-25AC CY7C4241V-25JC 35 CY7C4241V-35AC CY7C4241V-35JC Low Voltage Synchronous FIFO Speed (ns) ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4421V/4201V/4211V/4221V 32-Lead Plastic Leaded Chip Carrier J65 CY7C4231V/4241V/4251V 51-85063-B 51-85002-B ...