CY62256V-70SNC Cypress Semiconductor Corporation., CY62256V-70SNC Datasheet

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CY62256V-70SNC

Manufacturer Part Number
CY62256V-70SNC
Description
32K x 8 static RAM, 70ns, wide voltage range: 2.7V-3.6V
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Functional Description
The CY62256V is a high-performance CMOS static RAM or-
ganized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE) and active
Cypress Semiconductor Corporation
• 55, 70 ns access time
• CMOS for optimum speed/power
• Wide voltage range: 2.7V 3.6V
• Low active power (70 ns, LL version)
• Low standby power (70 ns, LL version)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Logic Block Diagram
— 108 mW (max.)
— 18 W (max.)
WE
OE
CE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
INPUT BUFFER
512x512
DECODER
COLUMN
ARRA Y
POWER
DOWN
3901 North First Street
PRELIMINARY
C62256V–1
LOW output enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 98% when deselected. The CY62256V is in
the standard 450-mil-wide (300-mil body width) SOIC, TSOP,
and reverse TSOP packages.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
through I/O
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to ensure alpha immunity.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
7
San Jose
) is written into the memory location addressed by
Pin Configurations
32K x 8 Static RAM
GND
I/O
I/O
I/O
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
0
1
2
March 1996 – Revised May 1996
CA 95134
13
14
1
2
3
4
5
6
7
8
9
10
11
12
Top View
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY62256V
I/O
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
CC
4
3
2
1
0
fax id: 1069
0
3
7
6
5
4
C62256V–2
408-943-2600
through A
14
).
0

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CY62256V-70SNC Summary of contents

Page 1

... Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected Functional Description The CY62256V is a high-performance CMOS static RAM or- ganized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active Logic Block Diagram ...

Page 2

... C62256V– GND C62256V–4 CY62256V-55 CY62256V- 500 500 [1] 0. Ambient Temperature +70 C 2.7V to 3. ...

Page 3

... MAX LL Max > 0. > 0. < 0.3V Test Conditions MHz 3.0V CC ALL INPUT PULSES 3.0V 90% 10% GND < 1.75V 3 CY62256V CY62256V-55 CY62256V-70 Min. Max. Min. Max. Unit 2.4 2.4 0.4 0.4 2 +0.3V +0.3V 0.5 0.8 0.5 0 200 200 ...

Page 4

... HZCE LZCE HZOE LZOE = part ( Test Loads. Transition is measured 500 mV from steady-state voltage. 4 CY62256V [4] Min. Max. 2.0 200 3. CY62256V-55 CY62256V-70 Min. Max. Min. Max ...

Page 5

... CY62256V-55 Description Min [ [10, 11] [10, 11 OHA DOE DATA VALID 50% and t HZWE . IL 5 CY62256V CY62256V-70 Max. Min. Max DATA VALID t HZOE t HZCE HIGH IMPEDANCE Unit ...

Page 6

... During this period, the I/Os are in output state and input signals should not be applied. PRELIMINARY PWE t SD DATA VALID SCE DATA 14 DATA 6 CY62256V C62256V– VALID VALID IN t LZWE C62256V–12 C62256V–11 ...

Page 7

... AMBIENT TEMPERATURE ( C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.40 1.30 1.20 1.10 1.00 V =3.3V CC 0.90 0.80 55.00 40.00 AMBIENT TEMPERATURE ( C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 2.50 2.00 1.50 1.00 V =3. = 0.50 0.00 0.00 33.00 5.0 CAPACITANCE (pF) 7 CY62256V OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 50.00 40.00 V =3.3V CC 30. 20.00 10.00 135.00 2.00 2.25 2.50 2.75 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 10.00 8.00 6.00 4.00 2.00 0.00 135.00 0.00 0.06 0.12 0.18 OUTPUT VOLTAGE (V) NORMALIZED I vs ...

Page 8

... High Z Deselect, Output Disabled Ordering Information Speed (ns) Ordering Code 55 CY62256V-55SNC CY62256VL-55SNC CY62256VLL-55SNC CY62256V-55RZC CY62256VL-55RZC CY62256VLL-55RZC CY62256V-55ZC CY62256VL-55ZC CY62256VLL-55ZC 70 CY62256V-70SNC CY62256VL-70SNC CY62256VLL-70SNC CY62256V-70RZC CY62256VL-70RZC CY62256VLL-70RZC CY62256V-70ZC CY62256VL-70ZC CY62256VLL-70ZC Shaded area contains advanced information. Document #: 38-00519 PRELIMINARY Mode Power Standby (I SB Active (I CC ...

Page 9

... Package Diagrams 28-Lead 450-Mil (300-Mil Body Width) SOIC S22 PRELIMINARY 28-Lead Reverse Thin Small Outline Package RZ28 9 CY62256V ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 28-Lead Thin Small Outline Package Z28 CY62256V ...

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