HYB18H512321AF-14 Infineon Technologies AG, HYB18H512321AF-14 Datasheet
HYB18H512321AF-14
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HYB18H512321AF-14 Summary of contents
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... Edition 2005-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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... HYB18H512321AF–12/14/16/20, HYB18H512321AFL14/16/20 Revision History: Rev. 1.73 Previous Revision: Rev. 1.60 Page Subjects (major changes since last revision) 75 figure 61: changed DQ setting We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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... Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.4.6 DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5 Bank / Row Activation (ACT 4.6 Writes (WR 4.6.1 Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6.2 Write - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.3 Write - Consecutive Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.3.1 Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.3.2 Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.6.4 Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.6.5 Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.6.6 Write followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Data Sheet 4 HYB18H512321AF 512-Mbit GDDR3 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... Driver IV characteristics at 40 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.7.2 Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.8 Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.9 Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.10 Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.10.1 Operating Current Ratings ( HYB18H512321AF–12/14/16/ 5.10.2 Operating Current Ratings (HYB18H512321AFL14/16/20 5.11 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.12 AC Timings ( HYB18H512321AF–12/14/16/20 5.13 AC Timings ( HYB18H512321AFL14/16/20 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.1 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.2 Package Thermal Characteristics ...
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... Self-Refresh Entry Command Figure 55 Self Refresh Entry Figure 57 Self Refresh Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 59 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 60 DLL off: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 61 DLL off: Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 62 Write followed by Precharge Figure 63 DLL off: Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Data Sheet FAW 6 HYB18H512321AF 512-Mbit GDDR3 Rev. 1.73, 2005-08 ...
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... Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 66 40 Ohm Driver Pull-Down and Pull-Up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 67 60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 68 120 Ohm Active Termination Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 69 240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 70 PG-TFBGA 136 package (11mm x 14mm Data Sheet 7 HYB18H512321AF 512-Mbit GDDR3 Rev. 1.73, 2005-08 ...
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... Programmed Terminator Characteristic at 240 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 35 Operating Current Ratings ( 0 °C Table 36 Operating Current Ratings ( 0 °C Table 37 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 38 Timing Parameters (HYB18H512321AF–12/14/16/20 Table 39 Timing Parameters (HYB18H512321AFL14/16/20 Table 40 PG-TFBGA 136 Package Thermal Resistances Data Sheet T 85 ° ° ° ...
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... GDDR3 Graphics RAM 1 Overview 1.1 Features V • 2 voltage HYB18H512321AF–12/14/16/20 DDQ V • 2.0 V core voltage HYB18H512321AF–12/14/16/ • 1 voltage HYB18H512321AFL14/16/20 DDQ V • 1.8 V core voltage HYB18H512321AFL14/16/20 DD • Organization: 2048K 32 8 banks • 4096 rows and 512 columns (128 burst start locations) per bank • ...
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... DQ should be interpreted in a similar fashion. Read and write accesses to the HYB18H512321AF are burst oriented. The burst length is fixed to 4 and 8 and the two least significant bits of the burst address are ’Don’t Care’ and internally set to LOW. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command ...
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... CAS G BA0 H CKE V J DDQ A11 DDQ V P SSQ V R DDQ V T SSQ SEN V 11 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration DQ9 DQ8 SSQ V V DQ11 DQ10 DDQ V V RDQS1 WDQS1 SSQ V V DM1 ...
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... PRECHARGE, A8 determines whether one bank is precharged (selected by BA<0:2>, A8 LOW) or all 8 banks are precharged (A8 HIGH). During (EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are sampled with the positive edge of CLK. Data Sheet 12 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... CMOS input. This pin must be hardwired on DDQ is the reference voltage input. REF Figure 1) correponds LOW. HIGH H10 H11 K10 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration V V and must be provided DD DDA Signal RAS CAS WE CS CKE ...
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... Table 3 Ball Assignment with Mirror (cont’d) MF Logic State LOW L9 K11 H10 Data Sheet HIGH K11 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration Signal A10 A11 BA0 BA1 BA2 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... Output Buffers Input Buffers DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 15 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration BA0-BA2 Column Addresses A2-A7,A9 Column Address Buffer Row Decoder Row Decoder Row Decoder Row Decoder Memory Bank 6 Memory ...
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... During t only NOP or DESEL commands are allowed. XPN XPN . During only NOP or DESEL commands are allowed XSC XSC 16 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration A2-7 A9- ...
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... Data Sheet . The MRS command can only be issued when all banks are t is met. MRD “Reads (RD)” on Page 17 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration “Mode Register MRD 37. The EMRS command can only 55. Rev. 1.73, 2005-08 ...
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... The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory content. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AREF command. The HYB18H512321AF requires AREF cycles at an average periodic interval of ...
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... Figure 14 Minimum delay to another bank (with concurrent autoprecharge ( WTR ( WL HYB18H512321AF 512-Mbit GDDR3 Pin Configuration XSNR for an example of when the data Note Rev. 1.73, 2005-08 05122004-B1L1-JEN8 is XPN ...
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... Note: MRS, EMRS, AUTO REFRESH, SELF REFRESH and precharge POWER DOWN are only allowed if all 8 banks are idle. Data Sheet single bank WR ACTIVE ACT PRE WR/A RD/A IDLE PDEN POWER DOWN PDEX precharge SREX SREN SELF REFRESH all banks 20 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration RD PDEN PDEX active Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... ACT, PRE, WRITE, WRITE/A, READ, READ/A 10 ACT 12) - 13) - 12) - 14) - 14) - 15 RCD . 21 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration have to be taken always into account PRE command on another bank RRD . PRE command on another bank RRD Rev. 1.73, 2005-08 05122004-B1L1-JEN8 11) WTR ...
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... Self Refresh DESEL or NOP Exit Power Down DESEL or NOP Exit Self Refresh DESEL or NOP Entry Precharge Power Down DESEL or NOP Entry Active Power Down Auto Refresh Entry Self Refresh 22 HYB18H512321AF 512-Mbit GDDR3 Pin Configuration . XPN t . XSC 5 t period. A minimum XSR Rev ...
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... CK The following lists the rest of the signals on the scan chain Puts device into scan mode and re-maps pins to scan functionality 23 HYB18H512321AF 512-Mbit GDDR3 Boundary Scan Dedicated Scan Flops (1 per signal under test) DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], CAS, WE, CKE, BA[2:0], A[11:0], CK, CK and ZQ Two RFU’s (J-2 and J-3 on 136-ball package) will be on the scan chain and will read as a logic " ...
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... Two RFU balls (#56 and #57) in the scan order, will read as a logic“0”. Data Sheet BIT# BALL BIT# BALL 25 K-11 37 R-10 26 K-10 38 T-11 27 K-9 39 T-10 28 M-9 40 T-3 29 M-11 41 T-2 30 L-10 42 R-3 31 N-11 43 R-2 32 M-10 44 P-3 33 N-10 45 P-2 34 P-11 46 N-3 35 P-10 47 M-3 36 R-11 48 N-2 24 HYB18H512321AF 512-Mbit GDDR3 Boundary Scan BIT# BALL BIT# BALL 49 L-3 61 G-4 50 M-2 62 F-4 51 M-4 63 F-2 52 K-4 64 G-3 53 K-3 65 E-2 54 K-2 66 F-3 55 L-4 67 E-3 56 J-3 57 J-2 58 H-2 59 H-3 60 H-4 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... the device. No initialization sequence of DD DDQ SYMBOL MIN V V (DC) +0.15 IH REF V (DC) — HYB18H512321AF 512-Mbit GDDR3 Boundary Scan V or GND DD MAX UNITS NOTES 1)2) — -0.15 V REF Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... SYMBOL MIN t 40 SCK t 20 SES t 20 SEH t 14 SCS t 14 SCH t 10 SDS t 10 SDH 26 HYB18H512321AF 512-Mbit GDDR3 Boundary Scan Don't Care Scan Out Scan Out bit 2 bit 3 Don't Care MAX UNITS NOTES — — ns 1)2 — — — ...
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... SEN low or simply by switching power off The Scan initialization sequence for the Stand-Alone Mode is shown in Figure 7. Data Sheet SYMBOL MIN MAX t — — SAC t 1.5 — SOH Chapter 3.2 27 HYB18H512321AF 512-Mbit GDDR3 Boundary Scan UNITS NOTES Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... EMRS/MRS settings. Therefore they have to be initilized again after the boundary scan functionary has been left. operation. Data Sheet T = 200µs Figure 8 shows the scan initilization sequence for regular SGRAM 28 HYB18H512321AF 512-Mbit GDDR3 Boundary Scan t t SDS SDH VALID ...
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... SOE[MF] SOUT[WDQS] Pins Under Test T = 200µs Power-up: VDD stable Figure 8 Scan Initialization Sequence within regular SGRAM Mode Data Sheet t ATS ATH 700tck RESET at power - up 29 HYB18H512321AF 512-Mbit GDDR3 Boundary Scan t t SDS SDH VALID t t SCS SCH t SCS t t SDS ...
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... RESL t SN Data Sheet stable clock t RESL t t ATS ATH t SN invalid 700tck CAS latency Symbol t RESL HYB18H512321AF 512-Mbit GDDR3 Boundary Scan Standard Power up sequence starting with PRE ALL Limit Values Unit Notes min max Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... Functional Description 4.1 Initialization The HYB18H512321AF must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation or permanent damage to the device. The following sequence is highly recommended for Power-Up Apply power ( , , DD DDA DDQ V the same time as ...
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... Data Sheet ATH DES DES PA EMR CODE All Banks CODE BA0 = H, BA1 = L t 700 cycles RP MRS: MRS command EMR: EMRS command DES : Deselect 32 HYB18H512321AF 512-Mbit GDDR3 Functional Description MRS PA ARF CODE All Banks CODE BA0 = L, BA1 = RFC MRD MRD RP ...
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... ZQ within 10%). VDDQ VSSQ Symbol min nom ZQ 210 240 Termination type No termination Add / CMDs HYB18H512321AF 512-Mbit GDDR3 Functional Description to 270 , giving an output will be used. In this case, no calibration will ZQ/4 or ZQ/2 Terminator when receiving DQ ZQ/6 Driver when transmitting max Units 270 Termination activation ...
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... Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses 6 NMOS legs. Data Sheet ARF NOP t KO needs 700 cycles after the clock is applied and 34 HYB18H512321AF 512-Mbit GDDR3 Functional Description t after the Autorefresh KO ARF: Autorefresh Don't Care Keep Out time Rev ...
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... Figure 13 Self Calibration of PMOS and NMOS Legs Data Sheet Termination CKE (at RES EMRS[3:2] 00 Disabled 10 ZQ/4 11 ZQ/2 ZQ/6 ZQ/6 PMOS Match 35 HYB18H512321AF 512-Mbit GDDR3 Functional Description Number of Legs Notes VDDQ NMOS Calibration VSSQ VDDQ / 2 Strength Control [2:0] VSSQ Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... Tc 85 Data Sheet N/D N/D N/D D0 Data Terminations are disabled ZQ Value ZQ/6 ZQ (nominal) and by applying DDQ DDQ/2 36 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N Dx: Data from Bank / Column address Com.: Command RD: READ Addr.: Address N/D: NOP or Deselect ...
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... WR (write recovery time for autoprecharge) in clock cycles is calculated by dividing up to the next integer (WR[cycles] = mode register must be programmed to this value. 37 HYB18H512321AF 512-Mbit GDDR3 Functional Description (Figure ...
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... This allows self-refresh operation at higher temperatures for mobile applications. Data Sheet EMRS NOP t RP A.C.: Any command Don't Care where HYB18H512321AF 512-Mbit GDDR3 Functional Description NOP A.C. t MRD EMRS: Extended MRS command PA: PREALL command t is the clock cycle time. CK Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... Timing of Vendor Code and Revision ID Generation on DQ[7:0] Data Sheet Infineon Vendor Code DQ[3:0] 0010 N/D N/D N/D N/D EMRS Add Vendor Code and Revision ID 39 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N/D t RIDoff EMRS: Extended Mode Register Set Command Add: Address N/D: NOP or Deselect Don't Care Rev ...
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... Testmode mode Normal Testmode RFU A6 DLL Reset A8 DLL Reset Yes HYB18H512321AF 512-Mbit GDDR3 Functional Description Burst Length RFU all others CAS Latency Burst Type ...
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... Reserved states should not be used as unknown operation or incompatibility with future versions may result. Data Sheet MRS NOP t MRD Figure 38. 41 HYB18H512321AF 512-Mbit GDDR3 Functional Description NOP A.C. NOP t MRDR MRS: MRS command PA: PREALL command A.C.: Any other command as READ RD: READ command Don't Care Order of Accesses within a Burst (Type = sequential) ...
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... A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of operations once the DLL reset is completed. Data Sheet Figure 28. 42 HYB18H512321AF 512-Mbit GDDR3 Functional Description Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... ACT Col A8 Row B.Y B.Y B.Y t RAS (four activate window) is defined. No more than 4 FAW t window. Converting to clocks is done by dividing FAW 43 HYB18H512321AF 512-Mbit GDDR3 Functional Description RRD t between opening and RAS ACT Row: Row Address Row Col: Column Address B.X: Bank X B.X B.Y: Bank Y R/W: READ or WRITE command ...
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... Setup and Hold Timing for CKE is equal to CMD and ADDR Setup and Hold Timing. Data Sheet ACT ACT ACT t t RRD RRD t FAW t +3*t FAW RRD t FAW IPW HYB18H512321AF 512-Mbit GDDR3 Functional Description ACT ACT ACT RRD RRD RRD ACT: ACTIVATE command Don't Care t CL Don't Care Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... The input data is masked if the corresponding DM t DIPW signal is high. All timing parameters are defined with graphics DRAM terminations on. Data mask signal DM0 DM1 DM2 DM3 45 HYB18H512321AF 512-Mbit GDDR3 Functional Description (min). t DQSS define the width of low and high phase t DQSH and has ...
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... Note: WDQS can only transition when data is applied at the chip input and during pre- and postambles. Data Sheet DQSH DQSL WPRE t t Preamble DIPW HYB18H512321AF 512-Mbit GDDR3 Functional Description t t DQSH WPST t t Postamble DIPW Data masked Don't Care DMx: Represents one DM line Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
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... NOP NOP NOP DES: WRITE N/P: No Operation Com.: Command . t DQSS 47 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES DES D2 D3 NOP NOP NOP NOP D2 D3 Addr.: Address Deselect D#: Data NOP or DES ...
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... DES DES Dx0 Dx1 Dx2 Dx3 Dy0 Dx0 Dx1 Dx2 WR: WRITE DES: Deselect N/D: NOP / Deselect . t DQSS 48 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES Dy1 Dy2 Dy3 Dx3 Dy0 Dy1 Dy2 Dy3 Dx Cx: Bank / Column address x Dy Cy: Bank / Column address y Com ...
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... WR N/D DES B/Cy Dx0 Dx1 Dx2 Dx3 Dx0 Dx1 Dx2 Dx3 Com.: Command Addr.: Address WL: DES: N/ DQSS 49 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES DES Dy0 Dy1 Dy2 Dy3 Dy0 Dy1 Dy2 Dy3 B / Cx: Bank / Column address Cy: Bank / Column address y ...
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... WDQS can only transition when data is applied at the chip input and during pre- and postambles. Data Sheet DES DES DES DES DQSS t RAS 50 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES DES =4 WR/A Begin of t MIN RAS Autoprecharge satisfied t =4 WR/A Begin of t MIN ...
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... DES DES DES DES DES DES DES DES DQSS 51 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES RD B/C t WTR DES DES DES t WTR Bank / Column address D#: Data WR: WRITE Com.: Command RD: READ Addr ...
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... Data Sheet DES DES DES DES DES DES DQSS 52 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES DES DES DES DES DES Bank / Column address WL: Write Latency WR: WRITE CL: CAS Latency DTD: DTERDIS ...
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... DES DES DES DES DES DES Com.: Command Addr.: Address WL: Don't Care 0: RD DQSS 53 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES RD/A B/C t WTR t WR/A Begin of Autoprecharge DES DES DES DES t WTR t WR/A Begin of Autoprecharge ...
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... WDQS can only transition when data is applied at the chip input and during pre- and postambles. Data Sheet DES DES DES DES DES DES DQSS 54 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES PRE DES DES DES DES t WR N/D: NOP or Deselect Bank / Column address ...
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... A RD may also be followed by a PRE command. Since no interruption of bursts is allowed the minimum time between a RD command and a PRE is two clock cycles as shown in All timing parameters are defined with controller terminations on. 55 HYB18H512321AF 512-Mbit GDDR3 Functional Description t ). After the last RPRE . ...
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... DQSQ valid t QH window t QHS The GDDR3 SGRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching the termination on again. 56 HYB18H512321AF 512-Mbit GDDR3 Functional Description t HP Postamble t RPST DQSQ ...
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... The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. Data Sheet N/D N/D N Bank / Column address Dx: Com.: Command Addr.: Address DQSQ 57 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N RD: READ ...
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... The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. Data Sheet N/D N/D N/D N/D Dx0 Dx1 Dx2 Dx0 . t DQSQ 58 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N/D Dx3 Dy0 Dy1 Dy2 Dy3 Dx1 Dx2 Dx3 ...
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... N/D N/D N/D B/Cy Dx0 Dx1 Dx2 Dx0 B / Cx: Bank / Column address Cy: Bank / Column address y RD: READ Dx#: Data from Dy#: Data from Com.: Command Addr.: Address HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N/D Dx3 Dy0 Dy1 Dy2 Dy3 Dx1 Dx2 Dx3 Dy0 ...
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... N/D N/D N/D DTD Dx0 Dx1 Dx2 Dx3 N/D DTD N/D N/D N/D Dx0 Dx1 Dx2 Dx3 B / Cx: Bank / Column address x Dx#: Data from Com.: Command Addr.: Address HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N N/D N/D N/D N/D RD: READ Don't Care DTD: DTERDIS DQs : Terminations off ...
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... CAS latency = 7 CAS latency = Bank / Column address RD/A: READ with auto-precharge Begin of Dx: Autoprecharge Com.: Command Addr.: Address requirement must be met at the beginning of Autoprecharge RAS t DQSQ 61 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N N/D: NOP or Deselect Don't Care ...
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... DES WR B/Cw t RTW D0r B / Cr: Bank / Column address for READ B / Cw: Bank / Column address for WRITE RD: READ WR: WRITE DES: Deselect t and DQSS 62 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES DES Write latency = 3 D3r D0w D1w D2w DES DES ...
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... RDQS. Data Sheet PRE N/D N/D CAS latency = Bank / Column address RD: Com.: Command PRE: Addr.: Address Dx: N/D: t DQSQ 63 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N Don't Care READ DQs : Terminations off PRECHARGE RDQS : Not driven Data from NOP or Deselect Rev ...
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... Write (i.e. Write to DTERDIS transition). ACT and PRE/PREALL may be applied at any time before or after a DTERDIS command. AP: AutoPrecharge Don't Care N/D N/D N/D Data Terminations are disabled 64 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N/D DTD: DTERDIS Don't Care Com.: Command N/D : NOP or Deselec Addr ...
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... Read command applied to the second Graphics DRAM rank system. In this case, RDQS would be driven by the second Graphics DRAM. Data Sheet N/D N/D N/D N/D N N/D N/D N/D N/D N/D N/D N/D N/D N/D N/D Com.: Command Addr.: Address HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N/D N N/D N/D N/D N/D N/D N/D N/D N/D N/D N Cx: Bank / Column address x Don't Care RD: ...
Page 66
... N/D N/D N/D N/D B/Cx CAS latency = 7 N/D RD N/D N/D N/D B/Cx CAS latency = 7 Com.: Command B / Cx: Bank / Column address x Addr.: Address RD: DTD: N/D: Dx#: 66 HYB18H512321AF 512-Mbit GDDR3 Functional Description N/D N/D N/D N/D Dx0 Dx1 Dx2 Dx3 N/D N/D N/D N/D Dx0 Dx1 Dx2 Dx3 Don't Care READ DQs : Terminations off DTERDIS RDQS : Not driven ...
Page 67
... DES DES DES WR B/Cw DES DES DES WR B/Cw Dxw: WRITE Com.: Command DTERDIS Addr.: Address Deselect t . DQSS 67 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES DES Write latency = 3 D0w D1w D2w D3w DES DES DES DES Write latency = 4 D0w ...
Page 68
... HYB18H512321AF 512-Mbit GDDR3 Functional Description t . A8/AP sampled with the PRE command RP t requirement is met for the RAS precharged bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All banks Rev ...
Page 69
... CLK# CLK Command ACT NOP A0 - A11 Row BA0 - BA2 B.X Figure 51 Precharge Timing Data Sheet PRE NOP B.X t RAS HYB18H512321AF 512-Mbit GDDR3 Functional Description NOP ACT Row B PRE: Precharge ACT: Activate Row: Row Address B.X: Bank X Don't Care Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 70
... REFI The AREF command generates an update of the OCD output impedance and of the addresses, commands and DQ terminations. The timing parameter Chapter 4.2.2 ARF NOP A.C. t RFC 70 HYB18H512321AF 512-Mbit GDDR3 Functional Description (min). The refresh period t RFC the whole memory has REF . t REFI (min) is the minimum required time ...
Page 71
... Self-Refresh mode the next clock after Self-Refresh entry, however the clock must be restarted before the device can exit Self-Refresh operation. Don't Care AREF 1 Clock HYB18H512321AF 512-Mbit GDDR3 Functional Description t is met. RP CLK/CLK# may be halted PA.: Precharge ALL Command (or last of PREs to each bank) ...
Page 72
... CKE must remain HIGH for the entire Self-Refresh exit period and commands must be gated off with CS held HIGH. Alternately, NOP commands may be registered on each positive clock edge during the Self Refresh exit interval. Don't Care stable 72 HYB18H512321AF 512-Mbit GDDR3 Functional Description t must be satisfied before XSC A.C. t XSC A ...
Page 73
... The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESEL command). A valid executable command may be t applied XPN Power-Down Mode Exit 73 HYB18H512321AF 512-Mbit GDDR3 Functional Description later. A.C. A.C. t XPN NOP or DESELECT Command A.C.: Any Command Don't Care Rev ...
Page 74
... CK9 f 8 100 CK8 f 7 100 CK7 DES DES PA EMR t min. 700 cycles RP 74 HYB18H512321AF 512-Mbit GDDR3 Functional Description are also applicable for DLL off Unit -20 max min max 350 100 350 MHz 350 100 350 MHz 350 100 350 ...
Page 75
... DLL off: Write followed by Read Data Sheet Symbol Limit Values -16 min max t (WL 0.5 (WL*t DQSS CK 0.5 t 0.77 — DIPW t 0.55 — WPRE t 0.88 1.32 WPST t 8 — WTR t 14 — HYB18H512321AF 512-Mbit GDDR3 Functional Description -20 min max ) + (WL 0.5 (WL 0.5 0.88 — 0.63 — 1.0 1.5 8 — 14 — Rev. 1.73, 2005-08 05122004-B1L1-JEN8 Unit ...
Page 76
... DES Bank / Column address WR: WRITE PRE: PRECHARGE Dx#: Data Dy#: Data the value for the read latency which is set in the Mode AC 76 HYB18H512321AF 512-Mbit GDDR3 Functional Description PRE DES DES B DES PRE DES ...
Page 77
... RDQS DQ RDQS DQ Figure 63 DLL off: Read Burst Data Sheet Read Symbol Latency t RTW t ACOFF t DQSCK N/D N/D N/D CAS latency = 7 t DQSCK t ACOFF CAS latency = 8 77 HYB18H512321AF 512-Mbit GDDR3 Functional Description Limit Values Unit -16 -20 min max min max (CL+4-WL) RTW(min) CK 2.4 6.2 2.4 6.2 ns 2.4 6.2 2.4 6 ...
Page 78
... WR B/Cw t RTW t DQSCKOFF D0r t ACOFF B / Cr: Bank / Column address for READ B / Cw: Bank / Column address for WRITE RD: READ WR: WRITE DES: Deselect 78 HYB18H512321AF 512-Mbit GDDR3 Functional Description DES DES DES DES Write latency = 3 D3r D0w D1w D2w DES DES DES DES ...
Page 79
... Self Refresh in DLL off mode is basically the same like in DLL on mode. Table 25 Self Refresh Exit Timing Parameter Parameter Self Refresh Exit Time Data Sheet Read Symbol Limit Values Latency -16 min t 700 XSC 79 HYB18H512321AF 512-Mbit GDDR3 Functional Description Unit -20 max min max — 700 — Rev. 1.73, 2005-08 05122004-B1L1-JEN8 Note ...
Page 80
... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data Sheet Electrical Characteristics Symbol Rating min -0.5 DDQ V -0.5 IN -0.5 V OUT -55 T STG T J — I OUT 80 HYB18H512321AF 512-Mbit GDDR3 Unit max. 2 +150 C +125 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 81
... Input leakage current CLK Input leakage current Output leakage current V V tracks with . AC parameters are measured with 1) DDQ DD 2) HYB18H512321AF–12/14/16/20 3) HYB18H512321AFL14/16/ expected to equal 70 REF same. Peak-to-peak noise on 19mV for DC error and an additionnal ± 27mV for AC noise and are measured with ODT disabled ...
Page 82
... Symbol Limit Values min 0.7 MP(DC) DDQ V 0.42 IN(DC) V 0.3 ID(DC) V 0.5 ID(AC 0.7 IX(AC) DDQ V of the transmitting device and must track variations in the DC DDQ 82 HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics max. — V -0.15 REF — 0.25 REF V + 0.3 DDQ V 0.35. DDQ °C) c Unit max. V – 0.10 0.7 + 0.10 V DDQ ...
Page 83
... Pin Capacitances (VDDQ = 1.8V 25°C, f= 1MHz) Parameter Input capacitance: A0-A11, BA0-2,CKE, CS, CAS, RAS, WE, CKE, RES,CLK,CLK Input capacitance: DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0- DM3 Data Sheet V DDQ 60 Ohm DQ Test point DQS Symbol Min CI,CCK 1.5 CIO 2.5 83 HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics Max Unit Notes 2.5 pF 3.5 pF Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 84
... Pull-Up IV characteristics. Table 31 Programmed Driver IV Characterisitcs at 40 Ohm Voltage (V) Pull-Down Current (mA) Minimum 0.1 2.32 0.2 4.56 0.3 6.69 0.4 8.74 0.5 10.70 0.6 12.56 0.7 14.34 0.8 16.01 0.9 17.61 1.0 19.11 1.1 20.53 1.2 21.92 1.3 23.29 1.4 24.65 1.5 26.00 1.6 27.35 1.7 28.70 1.8 30.08 1.9 — 2.0 — Data Sheet 0 -10 -15 -20 -25 -30 -35 -40 -45 1,5 2,0 -50 Pull-Up Current (mA) Maximum Minimum 3.04 -2.44 5.98 -4.79 8.82 -7.03 11.56 -9.18 14.19 -11.23 16.72 -13.17 19.14 -15.01 21.44 -16.74 23.61 -18.37 26.10 -19.90 28.45 .21.34 30.45 -22.72 32.73 -24.07 34.95 -25.40 37.10 -26.73 39.15 -28.06 41.01 -29.37 42.53 -30.66 43.71 — 44.89 — 84 HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics Pull-Up Characterstics 0,5 1,0 1,5 2,0 VDDQ - Vout (V) Maximum -3.27 -6.42 -9.45 -12.37 -15.17 -17.83 -20.37 -22.78 -25.04 -27.17 -29.17 -31.25 -33.00 -35.00 -37.00 -39.14 -41.25 -43.29 -45.23 -47.07 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 85
... IV characteristic. Table 32 Programmed Terminator Characteristics at 60 Ohm Voltage (V) Terminator Pull-Up Current (mA) Minimum 0.1 -1.63 0.2 -3.19 0.3 -4.69 0.4 -6.12 0.5 -7.49 0.6 -8.78 0.7 -10.01 0.8 -11.16 0.9 -12.25 1.0 -13.27 Data Sheet 60 Ohm Termination Characterstics 0,0 0,5 1,0 VDDQ - Vout (V) Voltage (V) Maximum -2.18 1.1 -4.28 1.2 -6.30 1.3 -8.25 1.4 -10.11 1.5 -11.89 1.6 -13.58 1.7 -15.19 1.8 -16.69 1.9 -18.11 2.0 85 HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics 1,5 2,0 Terminator Pull-Up Current (mA) Minimum Maximum -14.23 -19.45 -15.14 -20.83 -16.04 -22.00 -16.94 -23.33 -17.82 -24.67 -18.70 -26.09 -19.58 -27.50 -20.44 -28.86 — -30.15 — -31.38 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 86
... Table 33 Programmed Terminator Characteristics af 120 Ohm Voltage (V) Terminator Pull-Up Current (mA) Minimum 0.1 -0.81 0.2 -1.60 0.3 -2.34 0.4 -3.06 0.5 -3.74 0.6 -4.39 0.7 -5.00 0.8 -5.58 0.9 -6.12 1.0 -6.63 Data Sheet 120 Ohm Termination Characterstics 0,0 0,5 1 -10 -12 -14 -16 VDDQ - Vout (V) Voltage (V) Maximum -1.09 1.1 -2.14 1.2 -3.15 1.3 -4.12 1.4 -5.06 1.5 -5.94 1.6 -6.79 1.7 -7.59 1.8 -8.35 1.9 -9.06 2.0 86 HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics 1,5 2,0 Terminator Pull-Up Current (mA) Minimum Maximum -7.11 -9.72 -7.57 -10.42 -8.02 -11.00 -8.47 -11.67 -8.91 -12.33 -9.35 -13.05 -9.79 -13.75 -10.22 -14.43 — -15.08 — -15.69 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 87
... ADD/CMD termination IV characteristic. Table 34 Programmed Terminator Characteristic at 240 Ohm Voltage (V) Terminator Pull-Up Current (mA) Minimum 0.1 -0.41 0.2 -0.80 0.3 -1.17 0.4 -1.53 0.5 -1.87 0.6 -2.20 0.7 -2.50 0.8 -2.79 0.9 -3.06 1.0 -3.32 Data Sheet 240 Ohm Termination Characterstics 0,0 0,5 1,0 0,0 -1,0 -2,0 -3,0 -4,0 -5,0 -6,0 -7,0 -8,0 VDDQ - Vout (V) Voltage (V) Maximum -0.55 1.1 -1.07 1.2 -1.58 1.3 -2.06 1.4 -2.53 1.5 -2.97 1.6 -3.40 1.7 -3.80 1.8 -4.17 1.9 -4.53 2.0 87 HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics 1,5 2,0 Terminator Pull-Up Current (mA) Minimum Maximum -3.56 -4.86 -3.79 -5.21 -4.01 -5.50 -4.23 -5.83 -4.46 -6.17 -4.68 -6.52 -4.90 -6.88 -5.11 -7.21 — -7.54 — -7.85 Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 88
... Operating Currents 5.10.1 Operating Current Ratings ( HYB18H512321AF–12/14/16/20 ) Table 35 Operating Current Ratings ( 0 °C Parameter Symbol I Operating Current I Operating Current I Precharge Power-Down Standby Current I Precharge Floating Standby Current I Precharge Quiet Standby Current I Active Power-Down Standy Current I Active Standby Current I Operating Current Burst Read ...
Page 89
... Operating Current Ratings (HYB18H512321AFL14/16/20) Table 36 Operating Current Ratings ( 0 °C Parameter Operating Current Operating Current Precharge Power-Down Standby Current Precharge Floating Standby Current Precharge Quiet Standby Current Active Power-Down Standy Current Active Standby Current Operating Current Burst Read Operating Current Burst Write ...
Page 90
... CKE is HIGH HIGH between all valid RFC RFC CKE is HIGH HIGH between valid commands; Other REFI RCD RCDRD 90 HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics t ), Data bus inputs are STABLE (HIGH =min( ); Address and control inputs ...
Page 91
... SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals, and inputs changing 50% of each data transfer for DQ signals. 4. Legend: A=Active; RA=Read with Autoprecharge; D=DESELECT. Data Sheet V VDDQ; HIGH is defined HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics V ; DDQ Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 92
... AC Timings ( HYB18H512321AF–12/14/16/20) Table 38 Timing Parameters (HYB18H512321AF–12/14/16/20) Parameter CAS latency Clock and Clock Enable System frequency CL = Clock high level width Clock low level width Minimum clock half period Command and Address Setup and Hold Timing ...
Page 93
... Table 38 Timing Parameters (HYB18H512321AF–12/14/16/20) Parameter CAS latency Data-in and Data Mask to WDQS Setup Time Data-in and Data Mask to WDQS Hold Time Data-in and DM input pulse width (each input) DQS input low pulse width DQS input high pulse width DQS Write Preamble Time ...
Page 94
... Table 38 Timing Parameters (HYB18H512321AF–12/14/16/20) Parameter CAS latency Rev. ID EMRS timing REV. ID EMRS to DQ off timing 1) DLLon mode the lesser of minimum and This value of tMRD applies only to the case where the ’DLL reset ’ bit is not activated. ...
Page 95
... AC Timings ( HYB18H512321AFL14/16/20) Table 39 Timing Parameters (HYB18H512321AFL14/16/20) Parameter CAS latency Symbol Clock and Clock Enable System frequency Clock high level width Clock low level width Minimum clock half period Command and Address Setup and Hold Timing Address/Command input setup ...
Page 96
... Table 39 Timing Parameters (HYB18H512321AFL14/16/20) Parameter CAS latency Symbol Data-in and Data Mask to WDQS Hold Time Data-in and DM input pulse width (each input) DQS input low pulse width DQS input high pulse width DQS Write Preamble Time DQS Write Postamble Time Write Recovery Time ...
Page 97
... CLK after the last valid (falling) WDQS edge of the slowest WDQS signal Please round up to the next integer of 6) RTW 7) This parameter is defined per byte. Data Sheet HYB18H512321AF 512-Mbit GDDR3 Electrical Characteristics Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 98
... Package 6.1 Package Outline Figure 70 PG-TFBGA 136 package (11mm x 14mm) Note: . The package is conforming with JEDEC MO-207i, VAR DR-z. Data Sheet 98 HYB18H512321AF 512-Mbit GDDR3 Package Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 99
... JEDEC JESD-51 standard. 2. Theta_jB : Junction to Board thermal resistance. The value has been obtained by simulation. 3. Theta_jC : Junction to Case thermal resistance. The value has been obtained by simulation. Data Sheet 2s0p 3 m/s 0 m HYB18H512321AF 512-Mbit GDDR3 Package Theta_jB Theta_jC 3 m Rev. 1.73, 2005-08 05122004-B1L1-JEN8 ...
Page 100
... Published by Infineon Technologies AG ...