HSP50110JI-52 Intersil Corporation, HSP50110JI-52 Datasheet
HSP50110JI-52
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HSP50110JI-52 Summary of contents
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... Tuner for Digital Demodulators N response of the • Digital PLLs • Related Products: HSP50210 Digital Costas Loop; A/D Products HI5703, HI5746, HI5766 • HSP50110/210EVAL Digital Demod Evaluation Board Ordering Information PART NUMBER HSP50110JC-52 HSP50110JI-52 LOOP FILTER GCA LOW PASS FIR FILTER ...
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Pinout IIN5 IIN4 IIN3 IIN2 GND IIN1 IIN0 ENI QIN9 QIN8 QIN7 QIN6 QIN5 QIN4 V CC QIN3 QIN2 QIN1 QIN0 PH1 PH0 Pin Descriptions NAME TYPE V - +5V Power Supply. CC GND - Ground. IIN9-0 I In-Phase Input. ...
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Pin Descriptions (Continued) NAME TYPE SOF I Sampler Offset Frequency. This serial input is used to load the Sampler Offset Frequency into the Re-Sampler NCO (see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK ...
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HI/LO OUTPUT SENSE † LEVEL THRESHOLD FOR HI/LO DETECT EXTERNAL AGC † SYNTHESIZER/MIXER 10 IIN0-9 COMPLEX CLK MULTIPLIER 10 QIN0-9 ENI COS INPUT MODE † INPUT FORMAT † PH0-1 SYNTHESIZER CFLD COF SHIFT REG COFSYNC COF EN † WORD WIDTH ...
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Note: the effective input sample rate to the internal processing elements is equal to the frequency with which ENI is asserted “low”. In Interpolated Input Mode, ...
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Carrier Frequency (CF) Register and the Carrier Offset Frequency (COF) Register. As the accumulator sum transitions from ROM produces quadrature outputs whose phase advances o o from 0 to 360 . The sum ...
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Figure 3. The AGC gain is given by: E Gain = (1 AGC MAPS TO AGC UPPER AND LOWER LIMITS ...
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The Integrate and Dump filter exhibits a frequency response given --- - sin fR /sin where f is normalized frequency relative to the input sample rate and R is the decimation ...
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This is evident by the narrow alias free part of the output bandwidth as shown in Figures 8 and 9. The more rapid roll off of the third order CIC produces an ...
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FIGURE 12. To create the alias profile, a composite response, the components of which are shown in the ”D” portion of Figure 12, is made from the sum of all ...
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TO DECIMATING FILTERS PROGRAMMABLE DIVIDER SAMPLE PHASE † OUT CONTROL DATARDY MUX SYNC CLK 32-BIT ADDER 5 CARRY OUTPUT SHIFTER 8 RE-SAMPLER 32 NCO REG + † MUX SOF ENABLE SOF REG SCF REG SOFSYNC SYNC SAMPLER ...
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CLK by a programmable factor When the programmable clock factor is 1, IOUT9 is pulled high, and the CLK signal should be used as the clock. The beginning of a serial data word is signaled ...
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The Compensation Filter output is then rounded and limited to a 10-bit output range 0 -9 corresponding to bit positions Setting DQT Gains ...
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Thus, the minimum input signal will be -21.66dB below full scale (-9.66 -12 for A/D Backoff). As before the maximum input signal in the absence of noise is -12dB down due to A/D backoff. From Equation 14, the gain relationships ...
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R R HI/ SIN/COS CIC SCALER LEVEL VECTOR FROM -36 2 DETECT CARRIER NCO IIN0- QIN0 COMPLEX MULTIPLIER MANTISSA (1.0 ...
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Serial Input Interfaces Frequency control data for the NCOs contained in the Synthesizer/Mixer and the Re-Sampler are loaded through two separate serial interfaces. The Carrier Offset Frequency Register controlling the Synthesizer NCO is loaded via the COF and COFSYNC pins. ...
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For added flexibility, the CFLD input provides an alternative mechanism for transferring data from the Microprocessor Interfaces’s Holding Registers to the Center Frequency Register. When CFLD is sampled “high” by the rising edge of clock, the contents of the Holding ...
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BIT POSITIONS FUNCTION 31-0 Center Frequency This register controls the center frequency of the Synthesizer/Mixer NCO. This 32-bit two’s complement value sets the center frequency as described in the Synthesizer/Mixer Section. Center Format: [XXXXXXXX]H BIT POSITION FUNCTION 31-0 Sampler Center ...
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BIT POSITION FUNCTION 0 Input Format 0 = Two’s complement input format Offset binary input format. Note real input with offset binary weighting is used, the unused quadrature input pins should be tied to 1000000000. 1 ...
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TABLE 10. DECIMATING FILTER CONFIGURATION REGISTER (Continued) BIT POSITION FUNCTION 31-23 Reserved. BIT POSITION FUNCTION 0 HI/LO Output Sense 1 = HI/LO output of 1 means input > threshold HI/LO output of 1 means input (See Input Level ...
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BIT POSITION FUNCTION 7-0 Phase Offset This 8 bit two’s complement value specifies a carrier phase offset of (n/128) where n is the two’s com- plement value. This provides a range of phase offsets from - to *(127/128). (See Synthesizer/Mixer ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications Note 8, V PARAMETER CLK to IOUT9-0, QOUT9-0, DATARDY, LOTP, SSTRB, SPH4-0, HI/LO WR High WR Low RD Low RD LOW to Data Valid RD HIGH to Output Disable Output Enable WR to CLK Output Disable Time ...
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Waveforms t WRL C0-7, A0-2 FIGURE 26. TIMING RELATIVE 2.0V 0.8V FIGURE 28. OUTPUT RISE AND FALL TIMES 24 HSP50110 IIN9-0, QIN9-0, ENI, PH1-0, CFLD, COF, SOF, COFSYNC, t WRH t WH OEI ...
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... Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use ...