ADM6999U Infineon Technologies AG, ADM6999U Datasheet
ADM6999U
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ADM6999U Summary of contents
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... Edition 2005-11-25 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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... ISAC , ITAC ® ® ® QUAT , QuadFALC , SCOUT ® ® 10BaseV , 10BaseVX are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft ® Corporation, Linux of Linus Torvalds, Visio Incorporated. ® ® ® , ASP , DigiTape , DuSLIC ® ...
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... Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.5 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.7 Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.8 Automatic Link Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.9 Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.10 Auto Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 Memory Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.1.1 Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.1.2 Address Recognition and Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Sheet 4 ADM6999U/UX Data Sheet Table of Contents Rev. 1.42, 2005-11-25 ...
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... Serial Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.1.1 Serial Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.2 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.1 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.2 EEPROM Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3 Expansion Bus Receive Signals Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.4 Expansion Bus Transmit Signals Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Data Sheet 5 ADM6999U/UX Data Sheet Table of Contents Rev. 1.42, 2005-11-25 ...
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... Figure 3 100Base-X Module 18 Figure 4 Serial LED Interface 27 Figure 5 Scan LED Interface 28 Figure 6 Router old architecture 44 Figure 7 New architecture by using ADM6999U/UX serial chip VLAN function 45 Figure 8 ADM6999U/UX serial chips EEPROM pins operation 59 Figure 9 EEPROM Writing Command 60 Figure 10 TP Interface 61 Figure 11 FX Interface 62 ...
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... PCR_x Registers Table 35 Table 13 Per Port Rising Threshold 42 Table 14 Per Port Falling Threshold 42 Table 15 Drop Scheme for each Queue 42 Table 16 ADM6996 Port Mapping with ADM6999U/UX 44 Table 17 VLAN_MTR_x Registers Table 49 Table 18 RC & EEPROM Content Relationship 59 Table 19 Absolute Maximum Ratings 63 Table 20 Recommended Operating Conditions 63 Table 21 DC Electrical Characteristics for 3 ...
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... VLAN are also supported. ADM6999U/UX learns user define bits of VLAN ID. An intelligent address recognition algorithm makes ADM6999U/UX to recognize up to 2048 different MAC addresses and enables filtering and forwarding at full wire speed. Port MAC address Locking function is also supported by ADM6999U/UX to use on Building Internet access to prevent multiple users share one port traffic. 1.2 ...
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... Applications ADM6999U/UX in 128-pin PQFP: • 16-port switch Figure 1 ADM6999U/UX’s Application Data Sheet 1.6Gbps Expansion bus ADM6999U 8 10/100 MDIX TX/FX 9 ADM6999U/UX Data Sheet Introduction ADM6999U 8 10/100 MDIX TX/FX Rev. 1.42, 2005-11-25 ...
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... XO VCCPLL GNDPLL CONTROL VREF GNDBIAS RTX VCCBIAS VCCA2 TXP0 TXN0 GNDA RXP0 RXN0 VCCAD Figure 2 ADM6999U/UX 128 Pin Diagram Data Sheet ADM6999U 10 ADM6999U/UX Data Sheet Input and Output Signals GNDIK (GFCEN) ETXD0 (P7FX) ETXD8 ETXD1 ETXD2 ETXD3 ETXCLK GNDO VCC3O ETXD4 ...
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... Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high (identical to output with no type attribute). OD/PP Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with the OD attribute output with the PP attribute. ST Schmitt-Trigger characteristics TTL TTL characteristics Data Sheet Input and Output Signals 11 ADM6999U/UX Data Sheet Rev. 1.42, 2005-11-25 ...
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... Pin Description Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. Twisted Pair Interface 126 RXP0 2 RXP1 11 RXP2 15 RXP3 24 RXP4 28 RXP5 37 RXP6 41 RXP7 127 RXN0 1 RXN1 12 RXN2 14 RXN3 25 RXN4 27 RXN5 38 RXN6 40 RXN7 123 TXP0 5 TXP1 8 TXP2 18 TXP3 21 TXP4 31 TXP5 34 TXP6 44 TXP7 124 ...
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... For two ADM6999U/UXs as 16port application : Master: ADM6999U/UX will read 93C46/66 EEPROM first Bank.(00 ~27 H Slave0: ADM6999U/UX will read 93C66 EEPROM second Bank.(40 ~67 H User must assert one SK cycle when idle stage and chip internal registers are being writing. 13 ADM6999U/UX ...
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... Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. 74 ERXD0 100 ERXD1 101 ERXD2 102 ERXD3 103 ERXD4 106 ERXD5 107 ERXD6 108 ERXD7 68 ERXD8 73 ERXDV 78 ECOL 77 ECRS 58 ETXCLK 72 ERXCLK LED Interface, 11 pins 67 Scan LED OE0 86 Serial LED LEDDATA Scan LED ...
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... Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. 98 LED0 97 LED1 96 LED2 95 LED3 92 LED4 91 LED5 90 LED6 89 LED7 92 Dual Color EEPROM/Management Interface 84 EEDO 80 EECS 81 EECK XOVEN 79 EEDI LEDMODE Misc. 85 CKO25M 117 Control 120 RTX 118 VREF 112 RC Data Sheet Pin Buffer Function ...
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... Table 3 ADM6999U/UX 128 Pin Descriptions Pin or Ball Name No. 113 XI 114 XO 49 TEST Chip Configuration 46 ALERT Power/Ground 3, 10, 16, 23, GNDA 29, 36, 42, 125 6, 7, 19, 20, VCCA2 32, 33, 45, 122 13, 26, 39, VCCAD 128 119 GNDBIAS 121 VCCBIAS 116 GNDPLL 115 VCCPLL 47, 52, 64, GNDIK 76, 83, 93, ...
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... Receiver The 100Base-X receiver consists of functional blocks required to recover and condition the 125Mbits/s received data stream. The ADM6999U/UX implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125Mbits/s received data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application ...
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... The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group’s boundary. Data Sheet 4B/5B DECODER BP_DSCR BP_4B5B RX STATE MACHINE 100BASE-X RECEIVER TX STATE MACHINE BP_SCR BP_ALIGN 18 ADM6999U/UX Data Sheet Descriptions SDP RXP RXN TXP 10/100 MLT-3 TX STATE MACHINE DRIVER TXN FOTX+ ...
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... The ADM6999U/UX performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10Mbits/s link status to form the reportable link status bit in serial management register 1 , and driven to the LNKACT pin ...
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... A bad start of stream delimiter (Bad SSD error condition that occurs in the 100Base-X receiver if carrier is detected (CRS asserted) and a valid /J/K set of code-group (SSD) is not received. If this condition is detected, then the ADM6999U/UX will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat corresponding to the received 5B code-groups until at least two idle code-groups are detected ...
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... Operation Modes The ADM6999U/UX 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-duplex mode, the ADM6999U/UX functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmitting and receiving ...
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... Jabber Function The jabber function monitors the ADM6999U/UX output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted ...
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... Address is stored in the Address Table. The ADM6999U/UX searches for the Source Address (SA incoming packet in the Address Table and acts as below: If the SA was not found in the Address Table (a new address), the ADM6999U/UX waits until the end of the packet (non-error packet) and updates the Address Table. If the SA was found in the Address Table, then aging value of each corresponding entry will be reset to 0 ...
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... If the Multicast address, the packet is forwarded across the bridge the DA is PAUSE Command (01-80-C2-00-00-01), then this packet will be dropped by ADM6999U/UX. ADM6999U/UX can issue and learn PAUSE command. 5. ADM6999U/UX will forward the packet with 01-80-C2-00-00-00 ), filter out the packet with 01- 80-C2-00-00-01 ), and forward the packet with 01-80-C2-00-00-02 ~ 01-80-C2-00-00-0F ) 3.4.1.3 Address Aging Address aging is supported for topology changes such as an address moving from one port to the other ...
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... ADM6999U/UX. Meanwhile port-base VLAN could be enabled according to the PVID value ( user define 4bits to map 16 groups written at register 13 ADM6999U/UX also supports 16 802.1Q VLAN groups. In VLAN four bytes tag include twelve VLAN ID. ADM6999U/UX learns user define four bits of VID. If users need to use this function, two EEPROM registers are needed to be programmed first: • ...
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... Example1: Port receives Untag packet and send to Untag port ADM6999U/UX will check the port user define four bits of VLAN ID first then check VLAN group resister. If the destination port is in the same VLAN as the receiving port then this packet will forward to the destination port without any change ...
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... A two pins interface, LEDDATA and LEDCLK, provides external shift register to capture the LED status indicated by the ADM6999U/UX. The status is encapsulated within the shift sequence, which is a consecutive stream of 8- bit status words. The first word is the DUPCOL status, the second is the speed status, and the last is the LNKACT status ...
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... Serial Interface. Totally two pins, LEDCLK, and 0: single color LEDDATA are used to output the LED status. 1: dual color Parallel Interface. Three pins per port are used to 0: single color output the LED status types. 28 ADM6999U/UX Data Sheet Descriptions Rev. 1.42, 2005-11-25 ...
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... EEPROM Content EEPROM provides ADM6999U/UX many options setting such as: • Port Configuration: Speed, Duplex, Flow Control Capability and Tag/Untag • VLAN & TOS Priority Mapping • Broadcast Storming rate and Trunk • Fiber Select, Auto MDIX select • VLAN Mapping • ...
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... VLAN 14 outbound Port Map or VLAN 28 outbound Port Map VLAN 15 outbound Port Map or VLAN 30 outbound Port Map P0 Buffer Threshold Control P2 Buffer Threshold Control P4 Buffer Threshold Control P6 Buffer Threshold Control P8 Buffer Threshold Control Reserved 30 ADM6999U/UX Bit 7-0 Default Value ...
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... ADM6999U/UX Data Sheet Descriptions Page Number ...
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... SW can read the register SW can read the register SW can read the register, with write mask the register can be cleared SW can read the register, with write mask the register can be cleared SW can read and write this register 32 ADM6999U/UX Data Sheet Descriptions Page Number ...
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... EEPROM Registers Description Signature Register ADM6999U/UX will check register 0 value before read all EEPROM content. If this value not match with 0x4154h then other values in EEPROM will be useless. ADM6999U/UX will use internal default value. User can not write Signature register when programming ADM6999U/UX internal register. ...
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... Port Base Priority Number From 1~0 mapping to Q1~Q0. Default 0. Enable Port Based Priority If this bit turn on then ADM6999U/UX will not check TOS or VLAN as priority reference. ADM6999U/UX will check port base priority only. ADM6999U/UX default is bypass mode which checks port base priority only. If users want check VLAN tag priority then must set chip at Tag mode ...
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... Speed Capability 0 , 10M 100M, default B Auto Negotiation Capability Enable 0 , disable enable, default B 802.3X Flow Control Capability 0 , disable enable, default B 35 ADM6999U/UX Data Sheet Descriptions Offset Address Page Number Rev. 1.42, 2005-11-25 ...
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... Data Sheet Offset 0A H Description Cascade Buffer Threshold Control. Casecade buffer threshold control. These bits function only when ADM6999U/UX is configured to the EBUS mode and bit[15 configured to 1. 010110 , default B Bit[13:10]: The buffers allocated to each port in the casecade switch is equal to Bit[13:10 Bit[15:14]: The totally used buffers in the switch ...
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... Disable, default enable Port6 Trunk port B Enable IPG Leveling 1/92 bit. 0/96 bit. When this bit is enable ADM6999U/UX will transmit packet out at 96 bit or 92 bit to clean buffer. If user disable this function then ADM6999U/UX will transmit packet at 96 bit Disable, default B ...
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... B Mapped Priority of Tag Value (VLAN default B Mapped Priority of Tag Value (VLAN default B Mapped Priority of Tag Value (VLAN default B Mapped Priority of Tag Value (VLAN default B bit[13:12]) H Weight Ratio 1:1 1:2 1:3 1:4 38 ADM6999U/UX Data Sheet Descriptions Reset Value 5500 H Rev. 1.42, 2005-11-25 ...
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... B Mapped Priority of Tag Value (TOS default B Mapped Priority of Tag Value (TOS default B Mapped Priority of Tag Value (TOS default B Mapped Priority of Tag Value (TOS default B /bit[13:12]) H Weight Ratio 1:1 1:2 1:3 1:4 39 ADM6999U/UX Data Sheet Descriptions Reset Value 5500 H Rev. 1.42, 2005-11-25 ...
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... Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID. The ADM6999U/UX will use bit[3:0] as VLAN group. • TOS IP Packet ADM6999U/UX check byte 12 &13 if this value is 0800h then ADM6999U/UX knows this is a TOS priority packet. Type 0800 Byte 12~13 IP header define Byte 14 Bit[7:0]: IP protocol version number & ...
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... Reserved 0 , default B Reserved 0 , default B CRC Check Disable 0 , enable CRC Check, default disable CRC check B Reserved 0 , default B Broadcast Storming Enable 0 , disable, default enable B Broadcast Storming Threshold See below table default B 41 ADM6999U/UX Data Sheet Descriptions Reset Value 0040 H Rev. 1.42, 2005-11-25 ...
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... Per Port Falling Threshold 00 All 100TX Disable Not All 100TX Disable Table 15 Drop Scheme for each Queue Discard Mode/ 00 Utilization TBD 0% Data Sheet 01 10 10% 20 10% 0. 25% 42 ADM6999U/UX Data Sheet Descriptions 50% Rev. 1.42, 2005-11-25 ...
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... enable, default B RMII TXEN Timing If user connect several ADM6999U/ Hubbing Switch then this bit turn on. If user connect RMII to RMII PHY then this bit must turn off. RMII mode supports half duplex only RMII PHY Hubbing Switch, default ...
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... LAN Port Figure 6 Router old architecture Below is new architecture by using ADM6999U/UX serial chip VLAN function. The advantages of below are: 1. WAN Port can upgrade to 100/10 Full/Half, Auto MDIX. 2. WAN/LAN Port is programmable and put on same Switch extra NIC and save the cost. ...
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... Write Register 15 as 0180 H How MAC Clone Operation: 1. LAN to LAN/CPU Traffic. ADM6999U/UX LAN traffic to LAN/CPU only. Traffic to another LAN port will be untag packet. Traffic to CPU is Tag packet with VID = 1. CPU can check VID to distinguish LAN traffic or WAN traffic. Data Sheet CPU with ...
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... WAN to CPU Traffic. ADM6999U/UX WAN traffic to CPU only. Traffic to CPU is Tag packet with VID = 2. CPU can check VID to distinguish LAN traffic or WAN traffic. 3. CPU to LAN Packet. ADM6999U/UX CPU Packet to LAN port must add VID = 1 in VLAN field. ADM6999U/UX check VID to distinguish LAN traffic or WAN traffic. LAN output packet is Untag. ...
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... Offset 13 H Description VLAN Mapping Table Expansion Port VLAN Mapping Table Port7 VLAN Mapping Table Port6 VLAN Mapping Table Port5 VLAN Mapping Table Port4 VLAN Mapping Table Port3 VLAN Mapping Table Port2 47 ADM6999U/UX Data Sheet Descriptions Reset Value FFFF H Rev. 1.42, 2005-11-25 ...
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... All VLAN groups will cover Port8 at 32 group mode. This feature is good for multiple ADM6999U/UX systems. Data Sheet Description VLAN Mapping Table Port1 VLAN Mapping Table Port0 bit Offset 13 H Description Port 7, Odd VLAN Mapping Table ...
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... VLAN Mapping Table Register 13 VLAN_MTR_14 VLAN Mapping Table Register 14 VLAN_MTR_15 VLAN Mapping Table Register 15 Data Sheet Offset Address ADM6999U/UX Data Sheet Descriptions Page Number Rev. 1.42, 2005-11-25 ...
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... H Description Port1, Odd Port Buffer Threshold Control Port0, Even Port Buffer Threshold Control Offset 24 H Description Port3, Odd Port Buffer Threshold Control Port2, Even Port Buffer Threshold Control 50 ADM6999U/UX Data Sheet Descriptions Reset Value 0000 H Reset Value 0000 H Rev. 1.42, 2005-11-25 ...
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... Port_7 15:8 rw Port_6 7:0 rw ADM6999U/UX supports buffer management scheme with dynamic thresholds to ensure the fair share of memory among different port queues. If users need each port to have a fixed threshold, they can configure the Bit 14 in the Dynamic threshold management: Bit[7]: The add bit. Bit[6:0]: The offset bits. ...
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... Data Sheet Offset 27 H Description Fix Queue Management for the Casecade port 0 , default B Fix Queue Management 0 , default B Total Buffer Threshold Control Expansion Port Buffer Threshold Control The configuration is the same as the other ports. 52 ADM6999U/UX Data Sheet Descriptions Reset Value 0000 H Rev. 1.42, 2005-11-25 ...
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... Offset 28 H Description Port1 PVID bit 11~4 These 8 bits combine with register default H Port0 PVID bit 11~4 These 8 bits combine with register default H 53 ADM6999U/UX Data Sheet Descriptions Reset Value 0000 Bit[13~10] as full 12 bit VID. H Bit[13~10] as full 12 bit VID. H Rev. 1.42, 2005-11-25 H ...
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... Offset 29 H Description Port3 PVID bit 11~4 These 8 bits combine with register default H Port2 PVID bit 11~4 These 8 bits combine with register default H 54 ADM6999U/UX Data Sheet Descriptions Reset Value 0000 Bit[13~10] as full 12 bit VID. H Bit[13~10] as full 12 bit VID. H Rev. 1.42, 2005-11-25 H ...
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... Offset 2A H Description Port5 PVID bit 11~4 These 8 bits combine with register default H Port4 PVID bit 11~4 These 8 bits combine with register default H 55 ADM6999U/UX Data Sheet Descriptions Reset Value 0000 Bit[13~10] as full 12 bit VID. H Bit[13~10] as full 12 bit VID. H Rev. 1.42, 2005-11-25 H ...
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... Port7 PVID bit 11~4 These 8 bits combine with register default H Port6 PVID bit 11~4 These 8 bits combine with register default H Offset ADM6999U/UX Data Sheet Descriptions Reset Value 0000 Bit[13~10] as full 12 bit VID. H Bit[13~10] as full 12 bit VID. H Reset Value D000 Rev. 1.42, 2005-11- ...
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... VLAN group,default B Tag Shift for VLAN Grouping VLAN Tagshift register. ADM6999U/UX will select 4/5 bit from total 12 bit VID as VLAN groupreference. Select bit from VID depend on bit 11 setting. For example Bit[10:8] = 001, Bit11 = 0,then ADM6999U/UX will select packet VID4~VID1 as VLAN group mapping very flexible for user on VLAN grouping ...
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... Field Bits Type Port_8 7:0 rw Data Sheet Description Expansion Port PVID bit 11~4 These 8 bits combine with register default H 58 ADM6999U/UX Data Sheet Descriptions Bit[13~10] as full 12 bit VID. H Rev. 1.42, 2005-11-25 ...
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... Input Keep at least 30 ms after RC from ADM6999U/UX will read data from EEPROM. After RC if CPU update EEPROM that ADM6999U/UX will update configuration registers too. When CPU programs EEPROM & ADM6999U/UX, ADM6999U/UX recognizes the EEPROM WRITE instruction only. If there is any Protection instruction before or after the EEPROM WRITE instruction, CPU needs to generate separated CS signal cycle for each Protection & ...
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... The timing for writing to EEPROM is a little bit different. See below graph. Must be carefully when CS goes down after writting a command, SK must issue at least one clock. This is a difference between ADM6999U/UX with EEPROM write timing. If system is without EEPROM then users must write ADM6999U/UX internal register by 93C66 timing ...
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... TXP TXN ADM6999U RXP RXN Figure 10 TP Interface Transformer requirement: • TX/RX rate 1:1 • TX/RX central tap connect together to VCCA2. Users can change TX/RX pin for easy layout but do not change polarity. ADM6999U/UX supports auto polarity on receiving side. 4.2 FX Interface Data Sheet 1:1 0.01U R1 49 49.9 VCCA2 ...
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... TXP TXN ADM6999U RXP RXN Figure 11 FX Interface Data Sheet +3.3V 127 127 ADM6999U/UX Data Sheet TX/FX Interface +3. 3.3V Fiber Transceiver 1 GND_RX 2 RD VCC_RX VCC(3.3) 6 VCC_TX VCC(3.3) 7 TD- 8 TD+ 9 GND_TX +3.3V 127 182 182 SD 83 Rev. 1.42, 2005-11-25 ...
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... Symbol Values Min. Typ. V – – 0.7 * – – – 0.7 * – – 100 I 63 ADM6999U/UX DC Characteristics Unit Note / Test Condition Max. 3.63 V – 1.8 V – 1.8 V – 1.8 V – 0.3 V – 0.3 V – CC 155 °C – 1.8 W – – Unit Note / Test Condition Max ...
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... ADM6999U/UX Data Sheet Serial Management Page Number Rev. 1.42, 2005-11-25 ...
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... Description SW Register is read and writable by SW Value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= Target for development.) 65 ADM6999U/UX Data Sheet Serial Management Page Number ...
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... SW can read and write this register Register is read and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is read and writable by SW. Description Offset ADM6999U/UX Data Sheet Serial Management Reset Value 0002 1120 H Rev. 1.42, 2005-11-25 ...
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... Flow Control Disable 802.3X on for full duplex or back pressure on for half duplex B Port 6 Duplex Status 0 , Half Duplex Full Duplex B Port 6 Speed Status Mbit 100 Mbit ADM6999U/UX Data Sheet Serial Management Reset Value 0000 0000 H Rev. 1.42, 2005-11-25 ...
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... Port 3 Linkup Status 0 , Link is not established Link is established B Port 2 Flow Control Enable 0 , Flow Control Disable 802.3X on for full duplex or back pressure on for half duplex B Port 2 Duplex Status 0 , Half Duplex Full Duplex B 68 ADM6999U/UX Data Sheet Serial Management Rev. 1.42, 2005-11-25 ...
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... B Port 0 Duplex Status 0 , Half Duplex Full Duplex B Port 0 Speed Status Mbit 100 Mbit/s B Port 0 Linkup Status 0 , Link is not established Link is established B 69 ADM6999U/UX Data Sheet Serial Management Rev. 1.42, 2005-11-25 ...
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... Full Duplex B Expansion Speed Status Two bits indicate the operating speed Mbit 100 Mbit 1000 Mbit/s B Expansion Linkup Status 0 , Link is not established Link is established B 70 ADM6999U/UX Data Sheet Serial Management Reset Value 0000 0000 H Rev. 1.42, 2005-11-25 ...
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... Port 3 Cable Broken Length Port 2 Cable Broken Port 2 Cable Broken Length Port 1 Cable Broken Port 1 Cable Broken Length Port 0 Cable Broken Port 0 Cable Broken Length Offset ADM6999U/UX Data Sheet Serial Management Reset Value 0000 0000 H Reset Value 0000 0000 H Rev. 1.42, 2005-11-25 ...
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... Port 4 Transmit Packet Byte Count TPBC_5 Port 5 Transmit Packet Byte Count TPBC_6 Port 6 Transmit Packet Byte Count TPBC_7 Port 7 Transmit Packet Byte Count Data Sheet Description Port 0 Receive Packet Count Table 26. 72 ADM6999U/UX Data Sheet Serial Management Offset Address Page Number ...
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... Port 6 Error Count EC_7 Port 7 Error Count EC_8 Port 8 Error Count Data Sheet Offset Address ADM6999U/UX Data Sheet Serial Management Page Number Rev. 1.42, 2005-11-25 ...
Page 74
... Overflow of Port 5 Receive Packet Count Overflow of Port 4 Receive Packet Count Overflow of Port 3 Receive Packet Count Overflow of Port 2 Receive Packet Count Overflow of Port 1 Receive Packet Count Overflow of Port 0 Receive Packet Count 74 ADM6999U/UX Data Sheet Serial Management Reset Value 0000 0000 H Rev. 1.42, 2005-11-25 ...
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... Overflow of Port 5 Transmit Packet Count Overflow of Port 4 Transmit Packet Count Overflow of Port 3 Transmit Packet Count Overflow of Port 2 Transmit Packet Count Overflow of Port 1 Transmit Packet Count Overflow of Port 0 Transmit Packet Count 75 ADM6999U/UX Data Sheet Serial Management Reset Value 0000 0000 H Rev. 1.42, 2005-11-25 ...
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... Overflow of Port 7 Collision Count Overflow of Port 6 Collision Count Overflow of Port 5 Collision Count Overflow of Port 4 Collision Count Overflow of Port 3 Collision Count Overflow of Port 2 Collision Count Overflow of Port 1 Collision Count Overflow of Port 0 Collision Count 76 ADM6999U/UX Data Sheet Serial Management Reset Value 0000 0000 H Rev. 1.42, 2005-11-25 ...
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... Serial Interface Timing ADM6999U/UX serial chip internal counter or EEPROM access timing. • EESK: Similar as MDC signal • EDI: Similar as MDIO • ECS: Must keep low Device Opcode Preamble Start Address (read) Figure 12 Serial Interface Timing X • Preamble: At least 32 continuous "1". ...
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... Port_number or counter index: User define clear port or counter • Idle: EECK must send at least one clock at idle time Data Sheet Device Opcode Port Number or Counter Index Start Address (reset) 78 ADM6999U/UX Serial Management Rev. 1.42, 2005-11-25 Data Sheet ...
Page 79
... CONF 10u s tESKL tESKL tESKH tESKH tESK tESK Symbol Values Min. Typ. T – 5120 ESK T 2550 – ESKL 79 ADM6999U/UX AC Characteristics 100ms tCONF Unit Note / Test Condition Max. – ms – – ns – 20us 30us tERDS tERDH Unit Note / Test Condition Max. – ...
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... T 10 – ERDH T – – EWDD T10 T10 T11 Symbol Values Min. Typ. 2 – 0.5 – ADM6999U/UX Data Sheet AC Characteristics Unit Note / Test Condition Max. 2570 ns – – ns – – ns – – Unit Note / Test Condition Max. – ns – ...
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... Values Min. Typ – – CKL T 10 – CKH T 4 – SDS T 2 – SDH 81 ADM6999U/UX AC Characteristics Unit Note / Test Condition Max – 75ns 100ns tSDCL tSDCL Unit Note / Test Condition Max. – ns – – ns – – ns – ...
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... Package ADM6999U/UX 128 Pin PQFP Outside Dimension Figure 19 ADM6999U/UX 128 Pin PQFP Outside Dimension Data Sheet 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12 ADM6999U/UX Data Sheet Package Rev. 1.42, 2005-11-25 ...
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... References [1] [2] [3] [4] [5] [6] Data Sheet 83 ADM6999U/UX Data Sheet References Rev. 1.42, 2005-11-25 ...
Page 84
... Terminology A B Data Sheet 84 ADM6999U/UX Data Sheet Terminology Rev. 1.42, 2005-11-25 ...
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... Published by Infineon Technologies AG ...