SAA7130HL NXP Semiconductors, SAA7130HL Datasheet
SAA7130HL
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SAA7130HL Summary of contents
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... PCI video broadcast decoder Rev. 04 — 11 April 2006 1. General description The SAA7130HL is a single chip solution to digitize and decode video, and capture it through the PCI-bus. Special means are incorporated to maintain the synchronization of audio to video. The device offers versatile peripheral interfaces (GPIO) that support various extended applications, e ...
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... Philips Semiconductors The SAA7130HL meets the requirements of PC design guides 98/99 and 2001 and is PCI 2.2 and Advanced Configuration and Power Interface (ACPI) compliant. The analog video is sampled by 9-bit ADCs, decoded by a multi-line adaptive comb filter and scaled horizontally, vertically and by field rate. Multiple video output formats (YUV and RGB) are available, including packed and planar, gamma-compensated or black-stretched ...
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... Audio Transport stream GPIO [ function available. 1.3 Related documents This document describes the functionality and characteristics of the SAA7130HL. Other documents related to the SAA7130HL are: • User manual SAA7130HL/34HL , describing the programmability • Application note SAA7130HL/34HL , pointing out recommendations for system implementation • ...
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... Propagate reset and ACPI state D3-hot 2.5 General Package: LQFP128 Power supply: 3.3 V only Power consumption of typical application Standby state (D3-hot): < 0.02 W SAA7130HL_4 Product data sheet Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... SAA7130HL 9-BIT VIDEO ADC DIGITAL VIDEO VIDEO COMB FILTER SCALER DECODER 9-BIT VIDEO ADC Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder 1.4 mm AUDIO OUTPUT PIXEL ENGINE: MATRIX GAMMA FORMAT REGISTER UNIT © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Version ...
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... Philips Semiconductors 5. Pinning information 5.1 Pinning The SAA7130HL is packaged in a rectangular Low profile Quad Flat Package (LQFP) with 128 pins, see All the pins are shown sorted by number in Functional pin groupings are given in the following tables: Power supply pins: PCI interface pins: ...
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... VG digital ground for digital circuit, core and input/outputs 64, 74, 93 and 128 1, 19, 38, VS digital supply voltage for digital circuit, core and 54, 65, 73 input/outputs and 92 Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder Pin Symbol Pin Symbol 74 V 106 n.c. SSD 75 GPIO11 ...
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... LOW PCI request output: the SAA7130HL requests master access to PCI-bus (active LOW PCI grant input: the SAA7130HL is granted to master access PCI-bus (active LOW) 126 PO and interrupt A output: this pin is an open-drain interrupt O/D output, conditions assigned by the interrupt register ...
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... SSA CV0_Y V DDA CV1_Y DRCV_C CV3_C V SSA CV4 [1] The SAA7130HL offers an interface for analog video and audio signals. The related analog supply pins are included in this table. SAA7130HL_4 Product data sheet Analog interface pins …continued Pin Type Description 95 AS analog supply voltage (3.3 V) ...
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... V_CLK (also gated) 56 GIO HSYNC 57 GIO VSYNC 58 GIO - 59 GIO - 60 GIO - 61 GIO VAUX2 67 GIO VAUX1 (e.g. VACTIVE) Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder TS capture Raw DTV/DVB inputs outputs - - - - - - - ADC_CLK (out) - ADC_C[0] (LSB) R/W, TS_LOCK - (channel decoder locked) TS_S_D - (bit-serial data) TS_CLK - (< ...
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... GPIO7 to GPIO0 [1] The SAA7130HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated functions can be selected: a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD ( ITU-R BT.601 ); zoom-video, with discrete sync signals; ITU-R BT.656 ; VIP (1.1 and 2.0), with sync encoded in SAV and EAV codes. b) Transport Stream (TS) capture input: from the peripheral DTV/DVB channel decoder ...
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... DMA channel. The virtual memory address space (from OS) is translated into physical (bus) addresses by the on-chip hardware Memory Management Unit (MMU). The application of the SAA7130HL is supported by reference designs and a set of drivers for the Windows operating system (Windows driver model compliant). SAA7130HL_4 ...
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... SET VIDEO FIFOS DMA CONTROL Fig 4. Functional diagram 6.2 Application examples The SAA7130HL enables PC TV capture applications both on the PC motherboard and on PCI add-on TV capture cards. add-on card applications. Figure 5 proposed tuner types incorporate the RF tuning function and the IF down conversion. Usually the IF down conversion stage also includes a single channel and analog sound FM demodulator ...
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... An external audio signal, that would have otherwise connected directly to the sound card, is now routed through the SAA7130HL. This analog pass-through is enabled as default by a system reset, i.e. without any driver involvement and before system setup ...
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... Philips Semiconductors the audio (left or right) input of the SAA7130HL for analog video decoding and direct audio streaming to the sound card. On the other hand, the 2nd IF signal of the digital IF-PLL is fed directly to the interface of the channel decoder (TDA10045), which decodes the signal into a digital DVB-T Transport Stream (TS) ...
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... Fig 7. WDM capture driver filters 6.4 PCI interface 6.4.1 PCI configuration registers The PCI interface of the SAA7130HL complies with the PCI specification 2.2 and supports power management and Advanced Configuration and Power Interface (ACPI) as required by the PC Design Guide 2001 . The PCI specification defines a structure of the PCI configuration space that is investigated during the boot-up of the system. The confi ...
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... The device vendor ID is hard coded to 1131h, which is the code for Philips as registered with PCI-SIG. The device ID is hard coded to 7130h. During power-up, initiated by PCI reset, the SAA7130HL fetches additional system information via the I codes for the system vendor ID, sub-system ID (board version) and ACPI related parameters into the confi ...
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... First step of reduced power consumption: no functional operation. Program registers are not accessible, but content is maintained. Most of the circuitry of the SAA7130HL is disabled with exception of the crystal and real-time clock oscillators, so that a quick recovery from possible. Second step of reduced power consumption: no functional operation. Program registers are not accessible, but content is maintained ...
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... Fig 8. MMU implementation (shown bit width indication is valid for 4 kB mode) 6.4.5 Status and interrupts on PCI-bus The SAA7130HL provides a set of status information about internal signal processing, video standard detection, peripheral inputs and outputs (pins GPIO) and behavior on the PCI-bus. This status information can be conditionally enabled to raise an interrupt on the PCI-bus, e ...
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... Playback from video tape cannot be expected to maintain correct timing, especially not during feature mode (fast forward, etc.). Table 14 The SAA7130HL decodes all color TV standards and non-standard signals as generated by video tape recorders e.g. automatic video standard detection can be applied, with preference options for certain standards, or the decoder can be forced to a dedicated standard ...
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... USA, South wide America 6.6 Video processing 6.6.1 Analog video inputs The SAA7130HL provides five analog video input pins: • Composite video signals (CVBS), from tuner or external source • S-video signals (pairs of Y-C), e.g. from camcorder • DTV/DVB ‘low-IF’ signal, from an appropriate DTV or combi-tuner Analog anti-alias fi ...
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... Comb filtering achieves higher luminance bandwidth, resulting in sharper picture and detailed resolution. Comb filtering further minimizes color crosstalk artifacts, which would otherwise produce erroneous colors on detailed luminance structures. The comb filter as implemented in the SAA7130HL is adaptive in two ways: • Adaptive to transitions in the picture content • ...
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... Philips Semiconductors 6.6.5 Copy protection detection The SAA7130HL detects if the decoded video signal is copy protected by the Macrovision system. The detection logic distinguishes the three levels of the copy protection as defined in rev. 7.01, and are reported as status information. The decoded video stream is not effected directly, but application software and Operation System (OS) has to ensure that this video stream maintains the ‘ ...
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... FID = 1) sample rate video region - cropped - scaled scaling video last pixel Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder VBI DMA 1st buffer (A) 2nd buffer (A) video DMA (A) e.g. interlaced 1st buffer (upper field) 2nd buffer (lower field) mhb997 © ...
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... FID = 1) sample rate scaling 3rd field (odd, FID = 0) sample rate 4th field (even, FID = 1) sample rate scaling Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder VBI DMA 1st buffer (A) 2nd buffer (A) 3rd buffer (B) 4th buffer (B) video DMA (A) e.g. interlaced ...
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... So-called full-field data transmission is also possible, utilizing all video lines for data coding. The SAA7130HL supports capture of VBI data by the definition of a VBI region to be captured as raw VBI samples, that will be sliced and decoded by software on the host CPU. The raw sample stream is taken directly from the ADC and is not processed or fi ...
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... The SAA7130HL offers a multitude of formats to write video streams over the PCI-bus: YUV and RGB color space, 15-bit, 16-bit, 24-bit and 32-bit representation, packed and planar formats. For legacy requirements a clipping procedure is implemented, that allows the defi ...
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... Feeding video stream to a local MPEG compression device on the same PCI board, e.g. for time-shift viewing applications The video port of the SAA7130HL supports the following 8-bit and 16-bit wide YUV video signalling standards (see • VMI: 8-bit wide data stream, clocked by LLC = 27 MHz, with discrete sync signals HSYNC, VSYNC and VACTIVE • ...
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... TV broadcast reception usually provides a DTV signal on low IF, i.e. down converted into a frequency range from 0 MHz to 10 MHz. Such signals can be fed to one of the 5 video inputs of the SAA7130HL for digitizing. The digital raw DTV is output at the video port, and is sent to the peripheral channel decoder, e.g. TDA8961 for VSB-8 decoding ...
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... Transport stream input: parallel or serial (also applicable as I • Peripheral interrupt input: four GPIO pins of the SAA7130HL can be enabled to raise an interrupt on the PCI-bus. By this means, peripheral devices can directly intercept the device driver on changed status or error conditions Any GPIO pin that is not used for a dedicated function is available for direct read and write access via the PCI-bus ...
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... The overall R and ground pins must be connected to the power and ground layers directly. An ample copper area directly under the SAA7130HL with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective R chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended. ...
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... Figure 14 bused signals point-to-point signals [5] see Figure 14 [5] see Figure 14 [4] see Figure 14 bused signals point-to-point signals Figure 14 [6] [5] [6] [7] [8] [ o(sink) Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder Min Typ Max - 0 100 0.3 DDD 0 5.75 0 ...
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... (RMS) i(max (RMS kHz; bandwidth kHz reference voltage (RMS kHz; i ITU-R BS.468 weighted; quasi peak Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder Min Typ Max - 8 - 0.375 0.75 1. ...
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... Figure 15 LLC active LLC2 active [13 LLC active LLC2 active 0 2.4 V 2.4 to 0.4 V [14] [15] LLC active LLC2 active [14] [15] LLC active LLC2 active Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder Min Typ Max 2.0 - 5.5 0 ...
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... 2 0.4 V [14] inverted and not delayed [14] [16] inverted and not delayed Figure 16 [13] 0 2 0.8 V Figure 16 [13] 0 2 0.8 V Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder Min Typ Max 27.8 37 333 27.8 ...
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... See also Application note SAA7130HL/34HL . [10] See User Manual SAA7130HL/34HL for Anti-Alias Filter (AAF). ...
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... Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder [1] 24.576 MHz Fundamental 3rd harmonic 1.5 7 3.3 3 ...
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... The SAA7130HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7130HL follows the IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture set by the Joint Test Action Group (JTAG) chaired by Philips. ...
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... Fig 17. 32-bit identification code SAA7130HL_4 Product data sheet Figure BST instructions supported by the SAA7130HL Description This mandatory instruction provides a minimum length serial path (1 bit) between pins TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections ...
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... scale (1) ( 0.27 0.20 20.1 14.1 22.15 16.15 0.5 0.17 0.09 19.9 13.9 21.85 15.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder detail ...
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... SAA7130HL_4 Product data sheet 2 called small/thin packages. Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder 3 350 mm so called © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] ...
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... The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. SAA7130HL_4 Product data sheet Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Product data sheet - Product specification - Product specification - Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder Doc. number Supersedes - SAA7130HL_3 9397 750 14308 SAA7130HL_2 9397 750 10358 SAA7130HL_1 9397 750 08669 - © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of Koninklijke Philips Electronics N.V. Rev. 04 — 11 April 2006 SAA7130HL PCI video broadcast decoder © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands Date of release: 11 April 2006 Document number: SAA7130HL_4 ...