ST62T32B STMicroelectronics, ST62T32B Datasheet
ST62T32B
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ST62T32B Summary of contents
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... ST623x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port). DEVICE SUMMARY OTP EPROM DEVICE (Bytes) (Bytes) ST62T32B 7948 - ST62E32B 7948 September 1998 PSDIP42 PQFP52 7-bit Interface CDIP42W (See end of Datasheet for Ordering Information) I/O Pins 30 30 ST62T32B ST62E32B Rev. 2.5 1/86 105 ...
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... Table of Contents ST62T32B/ST62E32B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3.5 Data Window Register (DWR 1.3.6 Data RAM/EEPROM Bank Register (DRBR 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2 ...
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Table of Contents 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST62T32B ST62E32B mon core is surrounded by a number of on-chip peripherals. The ST62E32B is the erasable EPROM version of the ST62T32B device, which may be used to em- ulate the ST62T32B device, as well as the respec- tive ST6232B ROM devices. PA0..PA1 / 20 mA Sink PA2/OVF / 20 mA Sink PA3/PWM/20 mA Sink ...
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... A/D Converter with 21 ana- log inputs and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications. Figure 3. ST62T32B Pin Configuration 52515049484746454443424140 OSCin ...
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... In output mode, the TIMER pin outputs the data bit when a time-out occurs.The user can select as option the availability of an on-chip pull this pin. ST62T32B ST62E32B 7/86 111 ...
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... ST62T32B ST62E32B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code in Program memory and user vectors; Data ...
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... PRPR it must write also to the image register. The image register must be written before PRPR interrpt occurs between the two instructions the PRPR is not af- fected. ST62T32B ST62E32B Program ROM Page Register (PRPR) Address: CAh — Write Only 7 - ...
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... Table 3. Additional RAM/EEPROM Banks. Device RAM EEPROM ST62T32B/E32B bytes bytes 10/86 114 Table 4. ST62T32B/E32B Data Memory Space DATA and EEPROM DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTE R DATA RAM PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER ...
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... ROM ADDRESS:A19h ST62T32B ST62E32B Data Window Register (DWR) Address: 0C9h — Write Only 7 - DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0 Bits 7 = Not used. Bit 6-0 = DWR5-DWR0: Data read-only memory Window Register Bits. These are the Data read- only memory Window bits that correspond to the upper bits of the data read-only memory space ...
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... ST62T32B ST62E32B MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM Bank (DRBR) Address: CBh — Write only DRBR4 DRBR3 - DRBR1 DRBR0 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 3 - DRBR3. This bit, when set, selects RAM Page 1 ...
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... ROW0 bytes in each row may be programmed simultaneously in Parallel Write mode. The number of available 64-byte banks ( device dependent. ST62T32B ST62E32B (PMODE). In BMODE, one byte is accessed at a time, while in PMODE bytes in the same row are programmed simultaneously (with conse- ...
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... ST62T32B ST62E32B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle resetting E2PAR2 without programming the EEPROM ...
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... PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V programming flow of the ST62T32B/E32B is de- scribed in the User Manual of the EPROM Pro- gramming Board. The MCUs can be programmed ST62E3xB EPROM programming tools available from STMicroelectronics ...
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... ST62T32B ST62E32B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 7; the controller being externally ...
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... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is ST62T32B ST62E32B automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hard- ware stack which eliminates the need for a stack pointer ...
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... ST62T32B ST62E32B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator. In addition, a Low Frequen- cy Auxiliary Oscillator (LFAO) can be switched in ...
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... Bit 0 = OSCOFF . Main oscillator turn-off. When low, this bit enables main oscillator to run. The main oscillator is switched off when OSCOFF is high. ST62T32B ST62E32B 3.1.3 Oscillator Safe Guard The Oscillator Safe Guard (OSG) affords drastical- ly increased operational integrity in ST62xx devic- es. The OSG circuit provides three basic func- tions: it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU ...
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... ST62T32B ST62E32B CLOCK SYSTEM (Cont’d) Figure 10. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency Figure 11. OSG Emergency Oscillator Principle Main Oscillator Emergency Oscillator Internal ...
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... When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f ST62T32B ST62E32B : ...
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... ST62T32B ST62E32B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...
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... RESET 2.8k POWER ON RESET WATCHDOG RESET ST62T32B ST62E32B initialisation routine from being interrupted. The in- itialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction ...
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... ST62T32B ST62E32B RESETS (Cont’d) Table 7. Register Reset Status Register Oscillator Control Register 0DBh EEPROM Control Register 0DFh Port Data Registers 0C0h to 0C2h Port Direction Register 0C4h to 0C6h Port Option Register 0CCh to 0CEh Interrupt Option Register 0C8h TIMER Status/Control 0D4h 0E8h ...
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... Table 8. Recommended Option Choices Functions Required Stop Mode & Watchdog Stop Mode Watchdog ST62T32B ST62E32B When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU. In the HARDWARE option, the Watchdog is per- manently enabled. Since the oscillator will run con- tinuously, low power mode is not available ...
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... ST62T32B ST62E32B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR) . This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits T5, and the SR bit are all set to “ ...
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... The software activation option should be chosen only when the Watchdog counter used as a timer. To ensure the Watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH ST62T32B ST62E32B 27/86 131 ...
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... ST62T32B ST62E32B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are ex- ecuted after activation, before the Watchdog can generate a Reset ...
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... MCU from STOP/WAIT modes. Interrupt request from the Non Maskable Interrupt source #0 is latched by a flip flop which is automat- ST62T32B ST62E32B ically reset by the core at the beginning of the non- maskable interrupt service routine. Interrupt request from source #1 can be configu- ...
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... ST62T32B ST62E32B INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred re- sult, the user should save all Data space registers which may be used within the interrupt routines ...
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... Port PDn ORPD-DRPD C3h-C7h Port PEn ORPE-DRPE FCh-FDh ST62T32B ST62E32B Bit 5 = ESB: Edge Selection bit . The bit ESB selects the polarity of the interrupt source #2. Bit 4 = GEN: Global Enable Interrupt . When this bit is set to one, all interrupts are enabled. When this bit is cleared to zero all the interrupts (excluding NMI) are disabled ...
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... ST62T32B ST62E32B IINTERRUPTS (Cont’d) Interrupt Polarity Register (IPR) Address: DAh — Read/Write PortE PortD PortC PortA PortB In conjunction with IOR register ESB bit, the polar- ity of I/O pins triggered interrupts can be selected by setting accordingly the Interrupt Polarity Regis- ter (IPR bit in IPR is set to one the corre- sponding port interrupt is inverted (e.g. IPR bit ...
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... TXMT TXIEN FF CLK Q CLR I Start 0 FF CLK Q 0 CLR MUX I Start 1 1 IOR bit 6 (LES) FF CLK Q CLR I Start 2 IOR bit 5 (ESB) IOR bit 4(GEN) ST62T32B ST62E32B INT #0 NMI (FFC,D)) INT #1 (FF6,7) RESTART FROM STOP/WA IT INT #2 (FF4,5) INT #3 (FF2,3) INT #4 (FF0,1) 33/86 137 ...
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... ST62T32B ST62E32B 3.5 POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following paragraphs. 3.5.1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a “ ...
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... Nevertheless, two cases must be consid- ered: – If the interrupt is a normal one, the interrupt rou- tine in which the WAIT or STOP mode was en- ST62T32B ST62E32B tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode ...
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... ST62T32B ST62E32B 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with pull-up, but without interrupt – Analog input – ...
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... Output Output Note Don’t care ST62T32B ST62E32B 4.1.1.2 Interrupt Options All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The inter- rupt trigger modes (falling edge, rising edge and low level) can be configured by software as de- scribed in the Interrupt Chapter for each port ...
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... ST62T32B ST62E32B I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated in Figure 23. All other transitions are potentially risky and ...
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... I/O PORTS (Cont’d) Table 14. I/O Port configuration for the ST62T32B/E32B MODE AVAILABLE ON PA0-PA7 PB0, PB3-PB7 Input PC5-PC7 (Reset state if PORT PULL option disabled) PD0-PD7 PE0-PE4 PA0-PA7 Input PB0, PB3-PB7 with pull up PC5-PC7 (Reset state if PORT PD0-PD7 PULL option enabled) PE0-PE4 PA0-PA7 Input ...
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... ST62T32B ST62E32B I/O PORTS (Cont’d) 4.1.3 ARTimer alternate functions As long as PWMEN (resp. OVFEN) bit is kept low, the PA3/PWM (resp. PA2/OVF) pin is used as standard I/O pin and therefore can be configured in any mode through the DDR and OR registers. If PWMEN (resp. OVFEN) bit is set, PA3/PWM (re- sp ...
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... I/O PORTS (Cont’d) Figure 24. Peripheral Interface Configuration of SPI, UART and AR Timer16 V DD PD4/RXD1 PD5/TXD1 PD3/Sout PD2/Sin PD1/Scl PA3/PWM PA4/CP1 PA5/CP2 PA2/OVF ST62T32B ST62E32B PID RXD DR UART IARTOE PID DR 0 MUX 1 TXD PID PP/OD OPR 1 DR MUX 0 OUT PID IN DR SYNCHRONOUS SERIAL I/O PID ...
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... ST62T32B ST62E32B I/O PORTS (Cont’d) 4.1.6 I/O Port Option Registers ORA/B/C/D/E (CCh PA, CDh PB, CEh PC, CFh PD, FEh PE) Read/Write 7 Px7 Px6 Px5 Px4 Px3 Px2 Bit 7-0 = Px7 - Px0: Port and E Option Register bits. 4.1.7 I/O Port Data Direction Registers DDRA/B/C/D/E (C4h PA, C5h PB, C6h PC, C7h PD, FDh PE) ...
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... TIMER SYNCHRONIZATION :12 f OSC ST62T32B ST62E32B The prescaler input can be the internal frequency f divided external clock applied to INT 15 . the TIMER pin. The prescaler decrements on the rising edge. Depending on the division factor pro- grammed by PS2, PS1 and PS0 bits in the TSCR. ...
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... ST62T32B ST62E32B TIMER (Cont’d) 4.2.1 Timer Operating Modes There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler ( TIMER pin signal), and to INT the output mode ...
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... Address: 0D3h — Read/Write 0 7 PS1 PS0 Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D2h — Read/Write Bit 7 = D7: Always read as ”0”. Bit 6-0 = D6-D0 : Prescaler Bits. ST62T32B ST62E32B PS0 Divided 128 ...
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... ST62T32B ST62E32B 4.3 ARTIMER 16 The ARTIMER16 is a timer module based bit downcounter with Reload, Capture and Com- pare features to manage timing requirements. Two outputs provide PWM and Overflow (OVF) output signals each with programmable polarity, and two inputs CP1 and CP2 control start-up, capture and/or reload operations on the central counter ...
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... Counter CMP Value CT ZEROFLG OVFFLG COMPFLG ST62T32B ST62E32B 4.3.1.2 Compare functions The value in the counter CT is continuously com- pared to 0000h and to the value programmed into the Compare Register CMP. The comparison range to 0000h and CMP is defined by using the MASK register to select which bits are used, there- fore the comparisons performed are: – ...
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... ST62T32B ST62E32B CENTRAL COUNTER (Cont’d) 4.3.1.3 Capture functions Content of the counter CT can always be down- loaded (captured) into the CP register at selecta- ble event occurrence on pins CP1 and CP2, while capture in RLCP is possible only when the bit RELOAD is cleared. Capture functions with RELOAD cleared are used ...
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... Figure 29. Mask Impact on the Compare Functions in PWM mode (PWMD=0, PWMPOL=1) Counter Bit 0...3 MASK 000Fh 0007h 0003&000C = 0000h 0003h 0001h CMP = 000Fh ST62T32B ST62E32B 0003&0007 = 0003&000F CLK most significant “1” is bit 3 ...
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... ST62T32B ST62E32B 4.3.3 TIMINGS MEASUREMENT MODES These modes are based on the capture of the down counter content into either CP or RLCP reg- isters. Some are used in conjunction with a syn- chronisation of the down counter by reload func- tions on external event on CPi pins or software RUNRES setting, while other modes do not affect the downcounting ...
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... Load Counter from RLCP and Startup CP1 CP1 disabled CP2 CP2 disabled ST62T32B ST62E32B Note: After Reset, the first CP2 event will capture the 0000h state of the counter into CP and then will restart the counter after loading it from RLCP. CP2FLG flag must always be cleared to execute another capture into CP ...
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... ST62T32B ST62E32B TIMINGS MEASUREMENT MODES(Cont’d) 4.3.3.2 Timing measurement without startup control The down counter is in free running mode with RUNRES bit set and RELOAD bit cleared. This means counter automatically restarts from FFFFh on zero overflow and signal generation on PWM and OVF pins is not affected. ...
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... OVFFLG is cleared). When 1 the overflow output is in toggle mode; OVF tog- gles its state on every overflow event (independ- ent to the state of OVFFLG). ST62T32B ST62E32B Bit 0 = This bit is reserved and must be set to 0. Status Control Register 2 (SCR2) Address: E1h - Read/Write/Clear only ...
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... ST62T32B ST62E32B CONTROL REGISTERS (Cont’d) Status Control Register 3 (SCR3) Address: E2h - Read/Write/Clear only 7 CP2POL CP2I E N CP2FLG CMPI E N CMFLG ZEROIEN ZEROFLG PWMMD Bit 7 = CP2POL. CP2 Edge Polarity Select . CP2POL defines the polarity for triggering the CP2 event defines the action on a falling edge on the CP2 input rising edge ...
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... AND of the compare Register CMP: [(MASK & CT) = (MASK&CMP)]. A Masked-Counter Zero is the logical AND of the Mask Register MASK with the Counter Register CT, compared with zero: [(MASK & CT) = 0000h]. ST62T32B ST62E32B 4.3.6 16-BIT REGISTERS Note: Care must be taken when using single-bit instructions (RES/SET/INC/DEC) 16-bit registers 0 ...
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... ST62T32B ST62E32B Reload/Capture Register High Byte (RLCP) Address: E9h - Read/ (Write if RELOAD bit set) D7-D0. These bits are the High byte (D15-D8) of the 16-bit Reload/Capture Register. Reload/Capture Register Low Byte (RLCP) Address: EAh - Read/ (Write if RELOAD bit set) D7-D0. These bits are the Low byte (D7-D0) of the 16-bit Reload/Capture Register ...
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... PDS bit in the ADC control reg- ister to “0”. If PDS=“1”, the A/D is powered and en- abled for conversion. This bit must be set at least ST62T32B ST62E32B one instruction before the beginning of the conver- sion to allow stabilisation of the A/D converter. This action is also needed before entering WAIT mode, since the A/D comparator is not automati- cally disabled in WAIT mode ...
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... ST62T32B ST62E32B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ply voltages used as analog references. ...
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... INTERRUPTS PROGRAMMABLE f OSC DIVIDER BAUD RATE x 8 ST62T32B ST62E32B 4.5.1 PORTS INTERFACING RXD reception line and TXD emission line are sharing the same external pins as two I/O lines. Therefore, UART configuration requires to set these two I/O lines through the relevant ports reg- isters. The I/O line common with RXD line must be ...
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... ST62T32B ST62E32B 4.5.2 CLOCK GENERATION The UART contains a built-in divider of the MCU internal clock for most common Baud Rates as shown in Table 20. Other baud rate values can be calculated from the chosen oscillator frequency di- vided by the Divisor value shown. The divided clock provides a frequency that is 8 times the desired baud rate ...
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... ST62T32B ST62E32B 4.5.5 INTERRUPT CAPABILITIES Both reception and transmission processes can in- duce interrupt to the core as defined in the inter- rupt section. These interrupts are enabled by set- ting TXIEN and RXIEN bit in the UARTCR register, and TXMT and RXRDY flags are set accordingly to the interrupt source ...
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... ST62T32B ST62E32B REGISTERS (Cont’d) UART Control Register (UARTCR) Address: D7h, Read/Write 7 RXRDY TXMT RXIEN TXIE N BR2 BR1 Bit 7 = RXRDY. Receiver Ready . This flag be- comes active as soon as a complete byte has been received and copied into the receive buffer. It may be cleared by writing a zero to it. Writing a one is possible ...
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... I/O Port 0 1 Data Reg Direction ST62T32B ST62E32B operation Sout has to be programmed as open- drain output. The SCL, Sin and Sout SPI clock and data signals are connected to 3 I/O lines on the same external pins. With these 3 lines, the SPI can operate in the ...
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... ST62T32B ST62E32B SERIAL PERIPHERAL INTERFACE(Cont’d) After 8 clock pulses (D7..D0) the output Q4 of the 4-bit binary counter becomes low, disabling the clock from the counter and the data/shift register. Q4 enables the clock to generate an interrupt on the 8th clock falling edge as long as no reset of the counter (processor write into the 8-bit data/shift register) takes place ...
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... Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant ST62T32B ST62E32B bits of the opcode with the byte following the op- code. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space ...
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... ST62T32B ST62E32B 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following par- agraphs describe the different types ...
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... X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected # . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register ST62T32B ST62E32B tent or an immediate value in relation with the ad- dressing mode. In CLR, DEC, INC instructions the operand can be any of the 256 data space ad- dresses ...
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... ST62T32B ST62E32B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations ...
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... JRR 2 JRZ 2 b7,rr, pcr pcr 1 JRS 2 JRZ b7,rr,ee e a,w pcr pcr Cycle Operand Bytes Addressing Mode ST62T32B ST62E32B LOW 6 7 0111 HI JRC a,(x) 0000 prc 1 ind JRC 4 LDI 1 e a,nn 0001 prc 2 imm JRC a,(x) ...
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... ST62T32B ST62E32B Opcode Map Summary(Continued) LOW 1000 1001 1010 HI 2 JRNZ JRNC abc e 0000 1 pcr 2 ext 1 2 JRNZ JRNC abc e 0001 1 pcr 2 ext 1 2 JRNZ JRNC abc e 0010 1 pcr 2 ext 1 2 JRNZ JRNC 4 ...
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... RthJA =Package thermal resistance (junc tion-to ambient Pint + Pport. DD Pint = (chip internal power Pport =Port power dissipation (determined by the user). Value -0 (sink) 50 150 -60 to 150 ST62T32B ST62E32B Unit V ( ( 71/86 175 ...
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... ST62T32B ST62E32B 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC Internal Frequency with OSG f 2) OSG enable I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the A/D conversion ...
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... T < INT A = 0mA = 5.0V Test Cond itions Min. = 5.0V + 5.0V 5mA OL = 5.0V + 5.0V +10mA OL = 5.0V +20mA OL = 5.0V - 5.0V -5.0mA 3 0mA = 5.0V ST62T32B ST62E32B Value Unit Typ. Max 0 0.1 0.8 V 0.1 0.8 1.3 V 100 200 350 900 0.1 1.0 A -16 - ...
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... ST62T32B ST62E32B 6.4 AC ELECTRICAL CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter (1) t Supply Recovery Time REC Minimum Pulse Width ( RESET pin WR NMI pin T EEPROM Write Time WEE Endurance EEPROM WRITE/ERASE Cycle Retention EEPROM Data Retention C Input Capacitance IN C Output Capacitance ...
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... Set-up Time SU t Hold Time h 6.8 ARTIMER16 ELECTRICAL CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter f Input Frequency on CP1, CP2 Pins IN t Pulse Width at CP1, CP2 Pins W ST62T32B ST62E32B Value Test Condi tions Min. Typ 3. 4.5V 125 DD Value Test Conditions Min. Typ. ...
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... ST62T32B ST62E32B 7 GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 41. 42-Pin Plastic Shrink Dual-In-Line Package Figure 42. 52-Pin Plastic Quad Flat Package 76/86 180 mm Dim. Min Typ A A1 0.51 A2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 b2 1.02 1.14 C 0.23 0.25 0.38 0.009 0.010 0.015 D 36.58 36.83 37.08 1.440 1.450 1.460 E 15.24 E1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 eA 15. ...
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... D1 35.56 E1 14.48 14.99 15.49 0.570 0.590 0.610 e G 14.12 14.38 14.63 0.556 0.566 0.576 G1 18.69 18.95 19.20 0.736 0.746 0.756 G2 G3 11.05 11.30 11.56 0.435 0.445 0.455 G4 15.11 15.37 15.62 0.595 0.605 0.615 CDIP42SW L 2. Value Test Conditions Min. Typ. ST62T32B ST62E32B mm inches Typ Max Min Typ Max 4.01 0.158 0.030 1.400 1.78 0.070 1.14 0.045 5.08 0.115 0.200 0.89 0.035 ...
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... ST62T32B ST62E32B 7.2 ORDERING INFORMATION Table 27. OTP/EPROM VERSION ORDERING INFORMATION Program Sales Type Memory (Bytes) ST62E32BF1 7948 (EPROM) ST62T32BB6 ST62T32BB3 7948 (OTP) ST62T32BQ6 ST62T32BQ3 78/86 182 I/O Temperature Range Package SDIP42W - SDIP42W 30 -40 to 125 C - PQFP52 -40 to 125 C ...
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FASTROM MCUs WITH A/D CONVERTER, 16 bit AUTO-RELOAD TIMER, EEPROM, SPI AND UART 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors ...
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... INTRODUCTION The ST62P32B is the Factory Advanced Service T echnique ROM (FASTROM) versions ST62T32B OTP devices. They offer the same functionality as OTP devices, selecting as FASTROM options the options de- fined in the programmable option byte of the OTP version. 1.2 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics ...
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... ST62P32B FASTROM MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference STMicroelectronics references Device ST62P32B Package Dual in Line Plastic[ ] Plastic Quad Flat (Tape & Reel) Temperature Range Watchdog Selection Software Activation [ ] Hardware Activation Ports Pull-Up Selection Yes ...
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ST62P32B Notes: 82/86 186 ...
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AUTO-RELOAD TIMER, EEPROM, SPI AND UART 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory ...
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... ST6232B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6232B is mask programmed ROM version of ST62T32B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form 0.5s min TEST 15 14V typ ...
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... ST6232B MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference STMicroelectronics references Device ST6232B Package Dual in Line Plastic[ ] Plastic Quad Flat (Tape & Reel) Temperature Range Special Marking Yes ” ” Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only. ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...