ISPLSI3256A-70LQI Lattice Semiconductor Corp., ISPLSI3256A-70LQI Datasheet
ISPLSI3256A-70LQI
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ISPLSI3256A-70LQI Summary of contents
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... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 3256A Functional Block Diagram Input Bus Generic TOE Logic Output Routing Pool (ORP) Blocks H3 H2 I I/O 2 I/O 3 I I/O 6 I/O 7 ...
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Description (continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 128 I/O cells, each of which is ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load conditions (See Figure 2) TEST CONDITION A 470 ...
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External Switching Characteristics 5 TEST 2 PARAMETER # COND Data Prop. Delay, 4PT Bypass, ORP Bypass pd1 Data Prop. Delay pd2 Clk Frequency with Internal Feedback max f max (Ext.) – ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 24 I/O Register Bypass iobp t iolat 25 I/O Latch Delay t 26 I/O Register Setup Time before Clock iosu t 27 I/O Register Hold Time after Clock ioh t 28 I/O ...
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Internal Timing Parameters 2 PARAMETER # Outputs t 46 Output Buffer Delay Output Buffer Delay, Slew Limited Adder obs t 48 I/O Cell OE to Output Enabled oen t 49 I/O Cell OE to Output Disabled odis ...
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Timing Model I/O Cell I/O Reg Bypass I/O Pin #24 (Input) Input Register D Q RST #52 # Reset Y3,4 #51 Y0,1,2 GOE0,1 TOE Derivations of su, h and co from the Product ...
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Power Consumption Power consumption in the ispLSI 3256A device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3. Typical Device Power Consumption vs fmax 400 300 200 ...
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Pin Description NAME PQFP/MQFP PIN NUMBERS I I/O 4 25, 26, 28, I I/O 9 32, 33, 34, I I/O 14 37, 38, 39, I I/O 19 42, 43, 44, I/O 20 ...
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Pin Configuration ispLSI 3256A 160-Pin MQFP and 160-Pin PQFP Pinout Diagram 1 GND 2 I/O 114 I/O 115 3 I/O 116 4 5 I/O 117 6 I/O 118 I/O 119 7 I/O 120 8 9 I/O 121 10 GND 11 ...
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Part Number Description ispLSI Device Family Device Number Speed MHz max MHz max MHz max Ordering Information FAMILY fmax (MHz) tpd (ns ispLSI 77 ...