STLC5411FN STMicroelectronics, STLC5411FN Datasheet
STLC5411FN
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STLC5411FN Summary of contents
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... ACTIVATION ONLY” IN NT1 IDENTIFICATION CODE AS PER STANDARD November 1996 STLC5411 2B1Q U INTERFACE DEVICE PLCC44 ORDERING NUMBER: STLC5411FN Plastic DIP28 ORDERING NUMBER: STLC5411P EASILY INTERFACEABLE WITH ST5451 (HDLC & GCI CONTROLLER), ST5421 SID- GCI TRANSCEIVER AND ANY OTHER GCI, GCI IDL or TDM COMPATIBLE DEVICES 1/72 ...
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STLC5411 INDEX DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PIN CONNECTIONS (Top view) PLCC44 MICROWIRE MODE DIP28 MICROWIRE MODE STLC5411 PLCC44 GCI MODE DIP28 GCI MODE 3/72 ...
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STLC5411 Figure 1: Block Diagram. 4/72 ...
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GENERAL DESCRIPTION STLC5411 is a complete monolithic transceiver for ISDN Basic access data transmission on twisted pair subscriber loops typical of public switched telephone networks. The device is fully compatible with both ANSI T1.601-1988 U.S. and CSE (C32-11) French specifications. ...
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STLC5411 PIN FUNCTIONS (no Specific Microwire / GCI Mode) Note: all pin number are referred to Plastic DIP28 package. Pin Name In/Out 1, 4 LO+, LO- Out, Out Transmit 2B1Q signal differential outputs to the line transformer. When used with ...
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PIN FUNCTIONS (specific Micro Wire mode) Pin Name In/Out 12 BCLK In Out Bit clock input or output depending of the CMS bit in CMR register. When BCLK is an input, its frequency may be any multiple of 8 KHz ...
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STLC5411 PIN FUNCTIONS (specific GCI mode) Pin Name In/Out 6 FSa In Out Input or Output depending of the configuration. FSa KHz clock which indicates the start of the frame on Bx and Br. 7 FSb Out ...
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PIN FUNCTIONS (specific GCI mode) Pin Name In/Out 22 RFS In Remote febe select: When tied to 0 the remote febe is not transferred. When tied to 1 febe is transparently reported. See figure 10. 25 AIS In Analog interface ...
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STLC5411 MULTIPLE FUNCTION PIN DESCRIPTION Pin 7: S0/FSb/TEST2 Function or In/Out conditions (*) MW(pin MO(pin MW(pin MO(pin (*) Only true if ANATST (internal test signal Pin 10: TSR~/SCLK/TCLK Function or ...
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MULTIPLE FUNCTION PIN DESCRIPTION Pin 14: DCLK/IO4/TEST1/TSYNC [R+] Function or In/Out conditions DEN(cr2 MW(pin DEN(cr2 CONF2(pin MO(pin MW(pin CONF2(pin MO(pin Pin 15: Dr/IO3/EC/LFS/TDOUT [R+] ...
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STLC5411 MULTIPLE FUNCTION PIN DESCRIPTION Pin 17: CCLK/S2/CONF2 Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Pin 18: CI/IO1/ES1/PLLD [R+] Function or In/Out conditions MW(pin CONF2(pin MO(pin) = ...
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MULTIPLE FUNCTION PIN DESCRIPTION Pin 25: LSD/SFSr/AIS Function or In/Out conditions MW(pin CONF2(pin MO(pin MW(pin CONF2(pin MO(pin Pin 26: INT/RES [R+] Function or In/Out conditions MW(pin ...
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STLC5411 FUNCTIONAL DESCRIPTION Digital Interfaces STLC5411 provides a choice between two types of digital interface for both control data and (2 B+D) basic access data. These are: a) General Circuit Interface: GCI. b) Microwire/Digital System Interface: W/DSI The device will ...
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To read a 12 bits message, the difference is: limited address field extended data field (D11 - D8 A0. The Write/Read back indicator doesn‘t exit. DIGITAL SYSTEM INTERFACE Two B channels, each at 64 kbit/s ...
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STLC5411 Bit Clock BCLK determines the data shift rate on the Digital Interface. Depending on mode se- lected, BCLK is an input which may be any multi- ple of 8 kHz from 256 kHz to 6176 kHz or an out- ...
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Figure 3: DSI Interface formats: SLAVE mode. STLC5411 17/72 ...
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STLC5411 GCI MODE The GCI is a standard interface for the intercon- nection of dedicated ISDN components in the dif- ferent equipments of the subscriber loop : In a Terminal, GCI interlinks the STLC5411, the ISDN layer 2 (LAPD) controller ...
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Figure 4b: GCI interface format. Figure 4b: GCI interface format GCI CHANNEL C Bx/ FSa 8 KHz BCLK GCI CHANNEL C ...
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STLC5411 Figure 4c: GCI multiplex examples, (slave mode). 20/72 ...
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Data is transmitted in both directions at half the data clock rate. The information is clocked by the transmitter on the front edge of the data clock and can be accepted by the receiver after 1 to 1.5 pe- riod ...
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STLC5411 Monitor channel The Monitor channel is used to write and read all STLC5411 internal registers. Protocol on the Monitor channel allows a bidirectional transfer of bytes between UID and a control unit with ac- knowledgement at each received byte. ...
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the high impedance state timer is implemented in the UID. This timer (when enabled) starts each time the sender starts a byte sending and waits for a pre acknow- ledgement. C/I channel The ...
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STLC5411 code is sent permanently by the UID until a new status change occurs in RXACT register. C1 bit is sent first to the line. LINE CODING AND FRAME FORMAT 2B1Q coding rule requires that binary data bits are grouped ...
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STLC5411 is frame-synchronized when two consecutive synchwords have been consecutively detected. Frame lock will be maintained until six consecu- tive errored sync-words are detected, which will cause the flywheel to attempt to re-synchronize ...
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STLC5411 isters description for details. When NT1-AUTO or NT-RR-AUTO mode is se- lected, bits ps1 and ps2 in M4 channel are con- trolled directly by biasing input pins ES1 and ES2 respectively. e.g. ps1 is sent continuously to the line ...
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Table 2: 2B1Q Encoding of 2B+ D Fields. Time Data B I Bit Pair Quat # (relative Bits 8 # Quats 4 Where first bit ...
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STLC5411 Table 4: NT-to-Network 2B1Q Superframe Technique and Overhead Bit Assignments. FRAMING Quat Positions 1-9 Bit Positions 1-18 Super Basic Frame Frame # # Sync Word 1 1 ISW ...
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Figure 7: Superframe I/O pin SFS STLC5411 29/72 ...
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STLC5411 Figure 8: Normalized output pulse form 30/72 ...
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Figure 9: EOC message processing mode. STLC5411 31/72 ...
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STLC5411 Figure 10: CRC Errors Processing (auto-mode) 32/72 ...
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Table 5: EOC message processing: local actions. NT1-AUTO: (eoc address 000 or 111) Message Code Operate 2B+D loopback 0101 0000 Operate B1channel Loopback 0101 0001 Operate B2 channel Loopback 0101 0010 Request Corrupted CRC 0101 0011 Notify of Corrupted CRC ...
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STLC5411 TEST FUNCTIONS Various test functions are provided for transmitted pulse waveform checking, power spectral density measurement and transmitter linearity. Three commands in TXACT register are provided. The associated test function is enabled as long as the command is not ...
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UID. GCI: when GCI ”NT master of the clocks”configura- tion is selected, UID provides the GCI clocks needed for control channel transfer; PUP control in- struction is provided to the UID by pulling ...
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STLC5411 ways to enter quiet mode: QM bit in CR6 register and QM primitive command to write in TXACT register; in this last case, any further primitive will clear quiet mode. AUTOMODE For all auto mode configurations, AIS pin allows ...
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Table 7a: RXACT (indication) and TXACT (command) codes CODES (GCI or MW, NON AUTO-MODE) RXACT (indications DP/LSD EIU – ...
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STLC5411 Table 7b: RXACT (indication) and TXACT (command) codes. CODES ...
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AR instruction forces UID through the ap- propriate sequence to activate the line by sending TN followed by SN1. Beeing in the U-only-active state (H8A), AR command forces the sai bit equal 1 to the line. Is intended to ...
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STLC5411 0101 (PDN): Power Down PDN command forces UID to power down state. It should normally be used after UID has been set in a known deactivated state, e. after a DI status indication has been reported. ...
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NOP operations. area 10/1FH: test registers: reserved. area 20/2FH: the configuration registers. OPR CR1 CR2 CR3 CR4 CR5 CR6 Read Write access. CR5 only usefull in GCI mode area 30/3FH: the time slot registers. ...
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STLC5411 and M56, both registers RXM4 and RXM56 are queued in the interrupt register stack. Bits act, dea, uoa, sai are dedicated to the activa- tion procedure. Validation is always done in ac- cordance with the ANSI rule: validation at ...
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SFS = 0: SFSx is an input that synchronizes the transmit superframe. SFS = 1: SFSx is an output indicating the Transmit Superframe mode SFSx is always an output. NTS mode Select. NTS = 0: ...
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STLC5411 UID activation/deactivation complies with the requirements for repetor equipment. ”LT” or ”NT” behaviour is selected by means of bit NTS. BP1 and BP2 break-points should be set equal one too. See state matrix for the detailed ...
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MOB = 1: All interrupts issued from RXM4, RXM56 RXEOC and masked still possible to read these registers via RXOH. CTC Corrupted Transmit CRC Control CTC = 0: Allows the normal calculation of the CRC for the transmitted ...
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STLC5411 second line section to the first line section and viceversa. RFS = 1: Transfert anomalies second section first section and viceversa allowed. RFS = 0: Transfert anomalies second section first section and viceversa not allowed. LFS Local febe select. ...
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Status Register (STATUS) (Read only) After reset: 85H PWDN RXFFU RXFFO TXFFU TXFFO PWDN Power down PWDN = 1: UID is in power down state PWDN = 0: UID is in power up state RXFFU RX FIFO ...
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STLC5411 Receive M5 and M6 overhead bits register (RXM56) (read only) After reset: 1FH - - - m51r m61r m52r When the line is fully activated (super frame syn- chronized), STLC5411 extracts the overhead bits. When one of the received ...
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EOC Receive EOC status register read. When EOC bit is set equal one, UID automatically loads the current value of RXEOC register in the interrupt stack independently of any status change. M4 Receive M4 overhead bits status register read. When ...
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STLC5411 Table 8: REGISTER ACCESS MESSAGES BYTE 1 FUNCTION AD7/4 AD3/1 AD0 NOP 0000 000 RESERVED 0001 XXX OPR W 0010 000 OPR R 0010 000 CR1 W 0010 001 CR1 R 0010 001 CR2 W 0010 010 CR2 R ...
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Table 8: REGISTER ACCESS MESSAGES (Continued) BYTE 1 FUNCTION AD7/4 AD3/1 AD0 TXM4 W 0100 000 TXM4 R 0100 000 TXM56 W 0100 001 TXM56 R 0100 001 TXACT W 0100 010 TXACT R 0100 010 BEC1 R 0100 011 ...
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STLC5411 Table 9: READ BACK MESSAGES BYTE 1 FUNCTION AD7/4 AD3/1 AD0 OPR 0010 000 1 CIE CR1 0010 001 1 FF1 CR2 0010 010 1 SFS CR3 0010 011 1 LB1 CR4 0010 100 1 EB1 CR5 0010 101 ...
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Figure 11: Transformer Design. 6 120T 5 LINE SIDE 8 (secondary) 120T 7 Line Interface Circuit It is very important, comply with ANSI, ETSI and French standards, that the recommended line in- terface circuit should be strictly adhered to. The ...
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STLC5411 Figure 12: Recommended connections. 54/72 ...
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Figure 13a: LT Application. STLC5411 55/72 ...
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STLC5411 Figure 13b: NT Application. 56/72 ...
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Figure 13c: RR Application. STLC5411 57/72 ...
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STLC5411 APPENDIX A - STATE MATRIX 58/72 ...
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STLC5411 59/72 ...
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STLC5411 APPENDIX B - ELECTRICAL PARAMETERS ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage CC V Input Voltage IN T Operting Temperature Range A T Storage TemperatureRange stg TRANSMISSION ELECTRICAL PARAMETERS Parameter LINE INTERFACE FEATURES Differential Input Resistance between LI+/LI- ...
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TIMING CHARACTERISTICS Symbol Parameter MASTER CLOCK FMCLK Frequency of MCLK Tolerance MCLK/XTAL Input Clock Jitter tWMH Clock Pulse Width, MCLK High Level tWML Clock Pulse Width, MCLK Low Level tRM Rise Time of MCLK tFM Fall Time of MCLK DIGITAL ...
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STLC5411 Figure 14: BCLK, FSA, FSB, SLAVE MODE, DELAYED MODE, FORMATS (MW ONLY). Figure 15: BCLK, FSA, FSB, SLAVE MODE, NON DELAYED MODE, FORMATS (MW ONLY). 62/72 ...
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Figure 16: BCLK, FSA, FSB, SLAVE MODE, FORMAT 4 ALWAYS NON DELAYED MODE, (MW AND GCI MODE). Figure 17: BCLK, FSA, FSB, MASTER MODE, DELAYED MODE, FORMATS (MW ONLY). Note Note 1 ...
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STLC5411 Figure 18: BCLK, FSA, FSB, MASTER MODE, NON DELAYED MODE, FORMATS 1 3 (MW ONLY). Figure 19: BCLK, FSA, FSB, MASTER MODE, FORMAT 4 ALWAYS NON DELAYED MODE, (MW AND GCI MODE). 64/72 ...
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Figure 20: BX, DX, BR, DR, SLAVE & MASTER, DELAYED & NON DELAYED, FORMATS (MW ONLY) Figure 21: BX, DX, BR, DR, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED, (MW & GCI MODE) STLC5411 65/72 ...
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STLC5411 Figure 22: SPECIAL CASE BR, DR, ONLY FIRST BIT OF THE FRAME, IN SLAVE AND NON DE- LAYED MODES FORMATS 1 3 (MW MODE), FORMAT 4 (MW & GCI MODE) Figure 23: TSRB, SLAVE & MASTER, DELAYED & NON ...
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Figure 24: TSRB, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED MODE (MW & GCI) Figure 25: SPECIAL CASE TSRB FIRST CHANNEL OF THE FRAME, IN SLAVE & NON DELAYED MODE, FORMATS 1 3 (MW MODE), FORMAT ...
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STLC5411 Figure 26: DCLK, DX CONTINUOUS MODE SLAVE & MASTER, DELAYED & NON DELAYED MODES ALL FORMATS IN MW MODE ONLY Figure 24: MCLK ALL MODES Figure 25: MW PORT Mode A 68/72 ...
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Figure 26: MW PORT Mode B STLC5411 69/72 ...
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STLC5411 PLCC44 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A 17.4 B 16.51 C 3.65 D 4.2 d1 2.59 d2 0.68 E 14.99 e 1.27 e3 12.7 F 0. 1.16 M1 1.14 70/72 inch MAX. MIN. ...
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DIP28 PLASTIC PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 33. 4.445 L 3.3 inch MAX. MIN. TYP. 0.025 0.018 0.31 0.009 0.050 37.34 16.68 ...
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STLC5411 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...