MT90500AL Mitel, MT90500AL Datasheet - Page 9

• Manufacturer Part Number: MT90500AL
• Description: 0.3-6.5V; +-10mA; multi-channel ATM AAL1 SAR
• Manufacturer: Mitel

Specifications of MT90500AL

• Dc: 00+

MT90500
Table 49 - TDM I/O Register ........................................................................................................................... 100
Table 50 - TDM Bus Type Register................................................................................................................. 101
Table 51 - Local Bus Type Register ................................................................................................................ 102
Table 52 - TDM Bus to Local Bus Transfer Register....................................................................................... 102
Table 53 - Local Bus to TDM Bus Transfer Register....................................................................................... 103
Table 54 - TX Circular Buffer Control Structure Base Register....................................................................... 103
Table 55 - External to Internal Memory Control Structure Base Register ....................................................... 103
Table 56 - TX Circular Buffer Base Address Register..................................................................................... 104
Table 57 - TDM Read Underrun Address Register ......................................................................................... 104
Table 58 - TDM Read Underrun Count Register............................................................................................. 104
Table 59 - Clock Module General Control Register......................................................................................... 104
Table 60 - Clock Module General Status Register .......................................................................................... 105
Table 61 - Master Clock Generation Control Register .................................................................................... 106
Table 62 - Master Clock / CLKx2 Division Factor............................................................................................ 107
Table 63 - Timing Reference Processing Control Register ............................................................................. 107
Table 64 - Event Count Register ..................................................................................................................... 108
Table 65 - CLKx1 Count - Low Register.......................................................................................................... 108
Table 66 - CLKx1 Count - High Register......................................................................................................... 108
Table 67 - DIVX Register ................................................................................................................................ 109
Table 68 - DIVX Ratio Register ....................................................................................................................... 109
Table 69 - SRTS Transmit Gapping Divider Register ..................................................................................... 109
Table 70 - SRTS Transmit Byte Counter Register .......................................................................................... 110
Table 71 - SRTS Receive Gapping Divider Register ...................................................................................... 110
Table 72 - SRTS Receive Byte Counter Register ........................................................................................... 110
Table 73 - Output Enable Registers ................................................................................................................ 111
Table 74 - Absolute Maximum Ratings ........................................................................................................... 112
Table 75 - Recommended Operating Conditions ............................................................................................ 112
Table 76 - DC Characteristics ......................................................................................................................... 112
Table 77 - Main TDM Bus Output Clock Parameters ...................................................................................... 114
Table 78 - Main TDM Bus Data Output Parameters ....................................................................................... 116
Table 79 - Main TDM Bus Input Clock Parameters......................................................................................... 117
Table 80 - Main TDM Bus Input Data Parameters .......................................................................................... 117
Table 81 - Local TDM Bus Clock Parameters ................................................................................................. 120
Table 82 - Local TDM Bus Data Output Parameters....................................................................................... 120
Table 83 - Local TDM Bus Data Input Parameters ......................................................................................... 122
Table 84 - Intel Microprocessor Interface Timing - Read Cycle Parameters................................................... 124
Table 85 - Intel Microprocessor Interface Timing - Write Cycle Parameters................................................... 125
Table 86 - Motorola Microprocessor Interface Timing - Read Cycle Parameters ........................................... 126
Table 87 - Motorola Microprocessor Interface Timing - Write Cycle Parameters............................................ 127
Table 88 - MCLK - Master Clock Input Parameters ........................................................................................ 128
Table 89 - External Memory Interface Timing - Clock Parameters ................................................................. 128
Table 90 - External Memory Interface Timing - Read Cycle Parameters........................................................ 128
Table 91 - External Memory Interface Timing - Write Cycle Parameters ........................................................ 128
Table 92 - Primary UTOPIA Interface Parameters - Transmit......................................................................... 131
Table 93 - Primary UTOPIA Interface Parameters - Receive.......................................................................... 132
Table 94 - Secondary UTOPIA Parameters Timing ........................................................................................ 133
Table 95 - SRTS Interface Parameters ........................................................................................................... 134
Table 96 - Message Channel Parameters....................................................................................................... 134
Table 97 - Boundary-Scan Test Access Port Timing ...................................................................................... 136
Table 98 - MT90500 Connections to 18-bit Synchronous SRAM.................................................................... 138
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